US9077606B2 - Data transmission device, data reception device, and data transmission method - Google Patents
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- US9077606B2 US9077606B2 US13/319,188 US201013319188A US9077606B2 US 9077606 B2 US9077606 B2 US 9077606B2 US 201013319188 A US201013319188 A US 201013319188A US 9077606 B2 US9077606 B2 US 9077606B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4915—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using pattern inversion or substitution
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
Definitions
- the present invention relates to data transmission devices, data reception devices, and data transmission methods for performing data transmission through parallel buses.
- Patent Literatures 1 through 4 disclose techniques for reducing the number of data transitions in data transmission using parallel buses.
- Patent Literature 1 discloses a technique for reducing the number of data transitions by converting transmission data into gray codes
- Patent Literature 2 discloses a technique for reducing the number of data transitions by adding or subtracting +1 to or from transmission data.
- the number of data transitions is reduced by inverting bits in original data when more than a half of the data is to be changed.
- Patent Literature 4 discloses a technique for reducing the number of data transitions in data transmission using a serial bus.
- the probabilities of occurrence of difference data with respect to neighboring pixels are biased (or high in the neighborhood of “0”), and by taking advantage of such characteristics of image data, codes having small numbers of transitions are allotted to numerical values each having a high probability of occurrence of difference data (“00000000” is allotted to “0”, “00000001” is allotted to “+1”, and “11111110” is allotted to “ ⁇ 1”, for example). Encoding is performed in this manner, and the number of data transitions is reduced.
- Patent Literature 1 Japanese Laid-Open Patent Publication No. H09-244589
- Patent Literature 2 Japanese Laid-Open Patent Publication No. 2000-152129
- Patent Literature 3 Japanese Laid-Open Patent Publication No. 2002-366107
- Patent Literature 4 Japanese Laid-Open Patent Publication No. 2006-157443
- Patent Literatures 1 through 3 Each of the techniques disclosed in Patent Literatures 1 through 3 is for general data, and is not particularly effective for image data as target data. According to Patent Literature 3, 1 bit needs to be added to the bus width of a conventional data bus, to send a notification showing whether or not there has been a bit inversion.
- Patent Literature 4 The technique disclosed in Patent Literature 4 is effective for image data.
- Patent Literature 4 concerns a technique involving a serial bus, and, according to Patent Literature 4, the number of data transitions is reduced by performing encoding with the use of a conversion table that is formed in such a manner that the number of transitions in a single value to be transmitted (or the number of transitions in a bit string) becomes small with respect to difference data with a high probability of occurrence.
- the difference data “0”, “+1”, and “ ⁇ 1” having high probabilities of occurrence are associated with the encoded data “00000000”, “00000001”, and “11111110”, as described above.
- the number of bit transitions can be restricted to a small value.
- the encoded data for example, “00000001” and “11111110” are transmitted in this order through an 8-bit parallel bus, the number of data transitions reaches the maximum number, 8.
- the conversion table suggested in Patent Literature 4 is effective with a serial bus, but is not effective for data transmission using parallel buses.
- the present invention has been made to solve the above problems, and an object thereof is to provide a data transmission device that can reduce the number of data transitions by taking advantage of the characteristics of image data in data transmission through parallel buses.
- a data transmission device is a data transmission device that transmits transmission data converted into encoded data, using n-bit (n being k ⁇ m, k and m being natural numbers each equal to or greater than 1) signal lines.
- the data transmission device includes: an arithmetic operation unit that generates difference data that represents the difference between first data for m bits of the transmission data and second data for m bits of previous transmission data; and an encoding unit that encodes the difference data and generates m-bit encoded data.
- the encoding unit performs encoding to associate the encoded data with the difference data in such a manner that the number of bit inversions with respect to the encoded data associated with the difference data “0” becomes smaller as the absolute value of the difference data becomes smaller.
- the data transmission device generates encoded data by performing encoding in such a manner that an n-bit code is associated with the difference data between data for n bits of transmission data and previous data for n bits.
- the number of bit inversions in the n-bit codes with respect to the n-bit codes associated with the difference data “0” becomes smaller as the absolute value of the difference data becomes smaller.
- FIG. 1 is a block diagram of a data transmission system according to a first embodiment of the present invention.
- FIG. 2 is an encoding table according to the first embodiment of the present invention.
- FIG. 3 shows an example of encoding according to the first embodiment of the present invention.
- FIG. 4 is a block diagram of a data transmission system according to a second embodiment of the present invention.
- FIG. 5 shows an example of encoding and arithmetic operations according to the second embodiment of the present invention.
- FIG. 6 is a block diagram of a data transmission system according to a third embodiment of the present invention.
- a data transmission device is a data transmission device that transmits transmission data converted into encoded data, using n-bit (n being k ⁇ m, k and m being natural numbers each equal to or greater than 1) signal lines.
- the data transmission device includes: an arithmetic operation unit that generates difference data that represents the difference between first data for m bits of the transmission data and second data for m bits of previous transmission data; and an encoding unit that encodes the difference data and generates m-bit encoded data.
- the encoding unit performs encoding to associate the encoded data with the difference data in such a manner that the number of bit inversions with respect to the encoded data associated with the difference data “0” becomes smaller as the absolute value of the difference data becomes smaller.
- FIG. 1 is a block diagram of a data transmission system according to a first embodiment of the present invention.
- the data transmission system 10 includes a data transmission device 100 that transmits data, and a data reception device 110 that receives data.
- transmission data is image data in an RGB format
- the data transmission device 100 is a system LSI
- the data reception device 110 is a display device. Those components form a display data transmission system.
- 8-bit data about the respective elements of RGB (24 bits in total) is transmitted in parallel between the data transmission device 100 and the data reception device 110 through 24-bit signal lines.
- the data transmission device 100 includes a delay unit 101 , an arithmetic operation unit 102 , and an encoding unit 103 .
- Image data that is transmission data is input to the data transmission device 100 in pixel sequential order. One frame of image data is input, followed by the input of the next frame of image data.
- the delay unit 101 delays transmission data that is input, and outputs the delayed transmission data to the arithmetic operation unit 102 .
- Transmission data is input to the arithmetic operation unit 102
- the previous transmission data that is output from the delay unit 101 is also input to the arithmetic operation unit 102 .
- the arithmetic operation unit 102 calculates the difference between the data about a pixel that is input directly to the arithmetic operation unit 102 , and the data about the previous pixel that is output from the delay unit 101 (the pixel data before the data about the pixel that is input directly to the arithmetic operation unit 102 ). Based on the difference, the arithmetic operation unit 102 generates difference data, and outputs the difference data to the encoding unit 103 .
- the encoding unit 103 receives the difference data that is output from the arithmetic operation unit 102 .
- the encoding unit 103 then encodes the difference data, and outputs the difference data as encoded data. Those operations are performed on the 8-bit data about the respective RGB elements.
- the 8-bit encoded data about the respective elements of RGB that is output from the encoding unit 103 is transmitted to the reception device 110 through the 8-bit signal lines (24 bits for all the elements of RGB).
- FIG. 2 is an encoding table to be used when the encoding unit 103 performs encoding.
- “0” is associated with “00000000”.
- Encoded data is allotted in such a manner that a value having a smaller absolute value has fewer bit inversions on the corresponding signal line with respect to “00000000” associated with “0”.
- the inverted bits between “00000000” associated with “0” and “00001011” associated with “20” are the three bits: the fifth bit, the seventh bit, and the eighth bit.
- the number of bit inversions is 3.
- “1”, which has the smaller absolute value, has a much smaller number of bit inversions with respect to “00000000” associated with “0” than “20”, which has the larger absolute value.
- the difference values between the neighboring pixels form a Laplace distribution. That is, the difference value between two neighboring pixels is highly likely to be “0”, and the probability of occurrence of “0” rapidly becomes lower as the absolute value of the difference value becomes larger.
- the number of bit inversions on the respective signal lines of the parallel buses can be reduced by using the encoding table shown in FIG. 2 . In this manner, the power consumption can be reduced, and the EMI can be lowered.
- the number of bit inversions can be reduced by using the encoding table of FIG. 2 , according to the following principle.
- the difference data at the present time is of course highly likely to be a value with a small absolute value typically including “0”, and the difference data at an earlier time (t ⁇ 1) is also highly likely to be a value with a small absolute value typically including “0”.
- the probability of a transition from a value with a smaller absolute value to a value with a smaller absolute value is higher. Accordingly, in a transition from a value with a smaller absolute value to a value with a smaller absolute value, the number of times a bit is inverted on the respective buses in data transmission can be made smaller by performing encoding in such a manner that the number of bit inversions on each of the parallel buses becomes smaller.
- the encoded data having “1” as the number of inversions of bits from “0” are associated with “ ⁇ 4” through “ ⁇ 1” and “+'” through “+4”, which are the difference data with smaller absolute values.
- the encoded data having “1” as the number of bit inversions are the encoded data containing only one “1” among the eight bits in a case where the encoded data associated with the difference data “0” is “00000000”.
- the encoded data having “2” as the number of bit inversions are associated with “ ⁇ 18” through “ ⁇ 5” and “+5” through “+18”, which are difference data with smaller absolute values except for “ ⁇ 4” through “+4”.
- the encoded data having “2” as the number of bit inversions are the encoded data containing two is among the eight bits in a case where the encoded data associated with the difference data “0” is “00000000”.
- Which one of the eights bits should be “1” is determined in such a manner that the number of transitions with respect to the encoded data associated with the difference data “+1” becomes smaller as the absolute value of difference data becomes smaller. Specifically, as for each set of the difference data “+5” through “+11”, the last bit is “1”, so that the number of inversions of bits from the difference data “+1” becomes 1. As for each set of the difference data “ ⁇ 5” through “ ⁇ 11”, the first bit is “1”, so that the number of inversions of bits from the difference data “ ⁇ 1” becomes 1.
- the encoded data having “3”, “4”, . . . as the numbers of inversions of bits from “0” are allotted in the same manner as above.
- the encoded data having the smaller numbers of bit inversions with respect to the encoded data associated with the difference data “0” are associated, as a rule, with the difference data having the smaller absolute values, as described above.
- the above described effect can be achieved, even if this rule is not applied to all the difference data.
- the data reception device 110 includes a decoding unit 113 , an arithmetic operation unit 112 , and a delay unit 111 .
- the decoding unit 113 inputs and decodes encoded data transmitted from the data transmission device 100 , to generate decoded data.
- the decoding unit 113 refers to the same table as the table used in the encoding by the encoding unit 103 of the data transmission device 100 , or refers to the table shown in FIG. 2 as a decoding table.
- the decoded data is the difference data generated by the data transmission device 100 .
- the decoding unit 113 decodes the encoded data having a smaller number of bit inversions with respect to the encoded data associated with the difference data “0”, to form decoded data having a smaller absolute value.
- the arithmetic operation unit 112 of the data reception device 110 generates and outputs operation data.
- the delay unit 111 delays the operation data that is output from the arithmetic operation unit 112 , and outputs the delayed data to the arithmetic operation unit 112 .
- the arithmetic operation unit 112 then adds the difference data obtained from the decoding unit 113 and the previous operation data that is output from the delay unit 111 , to output current operation data.
- the operation data is the original transmission data that is restored.
- FIG. 3 is a diagram showing an example of data encoding.
- FIG. 3 shows an example of data about a Y-coordinate line in a frame.
- the transmission data pixel values
- the transmission data are “20”, “21”, “109”, “109”, “110”, “110”, “109”, “109”, “109”, . . . in sequential order from “0” in the X-coordinate.
- the outputs of the delay unit 101 are “0”, “20”, “21”, “109”, “109”, “110”, “110”, “109”, . . . .
- the arithmetic operation unit 102 calculates the respective differences to obtain difference data “20”, “1”, “88”, “0”, “1”, “0”, “ ⁇ 1”, “0”, . . . , and outputs the difference data to the encoding unit 103 .
- the encoding unit 103 Based on the encoding table shown in FIG. 2 , the encoding unit 103 encodes the difference data as follows: “20” into “00001011”, “1” into “00000001”, “88” into “10010111”, “0” into “00000000”, “1” into “00000001”, “0” into “00000000”, “ ⁇ 1” into “10000000”, “0” into “00000000”, . . . . The encoding unit 103 then transmits the encoded data to the data reception device 110 .
- the data reception device 110 Based on the decoding table having the same contents as those of the encoding table shown in FIG. 2 , the data reception device 110 generates decoded data by decoding the received encoded data as follows: “00001011” into “20”, “00000001” into “1”, “10010111” into “88”, “00000000” into “0”, “00000001” into “1”, “00000000” into “0”, “10000000” into “ ⁇ 1”, “00000000” into “0”, . . . .
- the arithmetic operation unit 112 adds the decoded data to the outputs of the delay unit 111 (“0” being the initial value), to generate operation data “20”, “21”, “109”, “109”, “110”, “110”, “109”, “109”, . . . as reception data
- the reception data are equal to the transmission data in the data transmission device 100 .
- the number of bit inversions from the transmission data “20” to “21” is 2, and the number of bit inversions from the transmission data “21” to “109” is 4. Thereafter, the respective numbers of bit inversions are 5, 1, 1, 1, 1, 1, . . . . As can be seen from the above, in a case where the differences among neighboring data are small as in a natural image, the numbers of bit inversions can be restricted to small values as in the latter half of the example illustrated in FIG. 3 .
- the difference data about a color difference tends to have a higher probability of occurrence of a value in the neighborhood of “0” than the difference data about G. Therefore, the number of bit inversions can be made smaller by using transmission data about the color differences (R-G and R-B) between R and the other two elements, than by using the data about each elements of RGB as transmission data.
- FIG. 4 is a block diagram of a data transmission system according to a second embodiment of the present invention.
- the data transmission system 20 includes a data transmission device 200 that transmits data, and a data reception device 210 that receives data.
- the data transmission device 200 is a system LSI
- the data reception device 210 is a display device, as in the first embodiment.
- the data transmission system 20 is a display data transmission system formed by those devices, and transmission data is image data in an RGB format, as in the first embodiment.
- 8-bit data about each of the elements of RGB is transmitted in parallel between the data transmission device 200 and the data reception device 210 through 24-bit signal lines, as in the data transmission system 10 of the first embodiment.
- the data transmission device 200 includes a first delay unit 201 , a first arithmetic operation unit 202 , an encoding unit 203 , a second arithmetic operation unit 204 , and a second delay unit 205 .
- the data reception device 210 includes a second arithmetic operation unit 214 , a second delay unit 215 , a decoding unit 213 , a first delay unit 211 , and a first arithmetic operation unit 212 .
- the second arithmetic operation unit 204 and the second delay unit 205 are added to the components of the first embodiment at the output stage of the data transmission device 200 , and the second arithmetic operation unit 214 and the second delay unit 215 are added to the components of the first embodiment at the input stage of the data reception device 210 .
- the data transmission system 20 can further reduce the number of bit inversions.
- the operations of the first delay unit 201 , the first arithmetic operation unit 202 , and the encoding unit 203 are the same as those of the delay unit 101 , the arithmetic operation unit 102 , and the encoding unit 103 of the first embodiment, respectively.
- the second arithmetic operation unit 204 generates encoded operation data.
- the second delay unit 205 delays the encoded operation data generated by the second arithmetic operation unit 204 , and outputs the delayed encoded operation data to the second arithmetic operation unit 204 .
- the encoded data obtained from the encoding unit 203 is XORed with the previously encoded operation data that is output from the second delay unit 205 , and is output as encoded operation data. It should be noted that the second delay unit 205 outputs “00000000” as the initial value.
- the encoded operation data that is output from the second arithmetic operation unit 204 is sequentially transmitted to the data reception device 210 through 8-bit signal lines (24 bits in total for all the elements of RGB).
- the second delay unit 215 delays the encoded operation data transmitted from the data transmission device 200 , and outputs the delayed encoded operation data to the second arithmetic operation unit 214 .
- the encoded operation data is input from the second arithmetic operation unit 204 to the second arithmetic operation unit 214 , and the previously encoded operation data that is output from the second delay unit 215 is also input to the second arithmetic operation unit 214 .
- the encoded operation data that is directly input is XORed with the previously encoded operation data that is output from the second delay unit 215 , and is output as second operation data to the decoding unit 213 .
- the encoded data generated in the same manner as in the first embodiment is subjected to an operation at the second arithmetic operation unit 204 , and is turned into encoded operation data in the data transmission device 200 .
- the data transmission system 20 then transmits the encoded operation data to the data reception device 210 .
- the data reception device 210 an operation is performed on the encoded operation data, to generate the second operation data.
- the second operation data is equal to the encoded data that is generated in the data transmission device 200 . That is, the data reception device 210 restores the encoded data at the second arithmetic operation unit 214 .
- the operations of the decoding unit 213 , the first delay unit 211 , and the first arithmetic operation unit 212 are the same as those of the decoding unit 113 , the delay unit 111 , and the arithmetic operation unit 112 of the first embodiment, respectively.
- FIG. 5 is a diagram showing an example of data encoding and arithmetic operations in the second embodiment.
- the same example data as that shown in FIG. 3 is used. Referring to FIG. 5 , the operations of the second arithmetic operation unit 204 and the second delay unit 205 in the data transmission device 200 are described.
- the second arithmetic operation unit 204 receives the encoded data “00010011” as the first output from the encoding unit 203 , the encoded data “00010011” is XORed with the initial value “00000000”, which is output from the second delay unit 205 , and “00010011” is output as encoded operation data.
- the second delay unit 205 delays the encoded operation data “00010011”, and outputs the delayed data to the second arithmetic operation unit 204 .
- the second encoded data “00000001” is XORed with the previously encoded operation data “00010011” at the second arithmetic operation unit 204 , and encoded operation data “00010010” is output from the second arithmetic operation unit 204 . Thereafter, encoded data is XORed with previously encoded operation data in the same manner as above at the second arithmetic operation unit 204 , and “10000101”, “10000101”, “10000100”, “10000100”, “00000100”, “00000100”, . . . are output as encoded operation data from the second arithmetic operation unit 204 .
- the received encoded operation data “00010011”, “00010010”, “10000101”, “10000101”, “10000101”, “10000100”, “10000100”, “00000100”, “00000100”, . . . are XORed bitwise with the outputs of the second delay unit 215 (the initial value being “0”: “00000000”), which are “00000000”, “00010011”, “00010010”, “10000101”, “10000101”, “10000100”, “10000100”, “00000100”, . . . at the second arithmetic operation unit 214 .
- the second operation data “00010011”, “00000001”, “10010111”, “00000000”, “00000001”, “00000000”, “10000000”, “00000000”, . . . are output to the decoding unit 213 .
- the second operation data is equal to the encoded data obtained from the encoding unit 203 of the data transmission device 200 .
- the numbers of bit inversions before and after the transmission of the difference data “88” are as large as 4 and 5, as shown in FIG. 3 .
- the encoded data is not merely formed by encoding difference data, but is further XORed bitwise with the data transmitted at the previous time.
- the number of bit inversions prior to the transmission of the difference data “88” is as large as 5, but the number of bit inversions after the transmission of the difference data “88” is 0, as shown in FIG. 5 . That is, in the second embodiment, the number of bit inversions occurring after the appearance of difference data having a large value can be dramatically reduced.
- FIG. 6 is a block diagram of a data transmission system according to a third embodiment.
- the data transmission system 30 is a system formed by connecting a data write device 300 and a data read device 310 that are system LSIs to a storage device 320 as a memory device by memory buses.
- Write data and read data are image data in an RGB format.
- the data write device 300 includes a delay unit 301 , an arithmetic operation unit 302 , and an encoding unit 303 .
- the data read device 310 includes a delay unit 311 , an arithmetic operation unit 312 , and a decoding unit 313 .
- the data write device 30 C and the storage device 320 are connected by an 8-bit memory bus for the data about each of the elements of RGB (24 bits in total) and the storage device 320 and the data read device 310 are also connected by an 8-bit memory bus for the data about each of the elements of RGB (24 bits in total).
- the operations of the delay unit 301 , the arithmetic operation unit 302 , and the encoding unit 303 of the data write device 300 are the same as those of the delay unit 101 , the arithmetic operation unit 102 , and the encoding unit 103 of the data transmission device 100 of the first embodiment, respectively.
- the operations of the delay unit 311 , the arithmetic operation unit 312 , and the encoding unit 313 of the data read device 310 are the same as those of the delay unit 111 , the arithmetic operation unit 112 , and the decoding unit 113 of the data reception device 110 of the first embodiment, respectively.
- the outputs of the encoding unit 103 of the data transmission device 100 are input (transmitted) directly to the decoding unit 113 of the data reception device 110 .
- the encoded data that is output from the encoding unit 303 of the data write device 300 is written into the storage device 320 , and the decoding unit 313 of the data read device 310 reads the encoded data from the storage device 320 .
- the data write device 300 may be designed to be the same as the data transmission device 200 of the second embodiment, and the data read device 310 may be designed to be the same as the data reception device 210 of the second embodiment. In that case, the number of bit inversions in data transmission for writing and reading can be further reduced as in the second embodiment.
- an 8-bit data bus is used for each of the elements of RGB.
- the number of data bus bits is not limited to the above, and may be larger than or the smaller than the above, as long as 2 bits or more are allotted to each of the elements.
- a data transmission system may have data buses of 30 bits in total, having 10 bits allotted to each of the elements of RGB.
- the data to be transmitted is not limited to RGB data, and may be Y, U, and V (brightness and color difference) data, for example.
- the present invention may be suitably applied to any data showing a Laplace distribution like image data, and may not be necessarily applied to image data.
- RGB data is transmitted
- the data about two elements may be transmitted as the color differences with R (R-G and R-B).
- R-G and R-B the respective elements of RGB are regarded as independent of one another, and the same operation is performed on each one element (8 bits).
- the present invention is not limited to that.
- the encoded data associated with the difference data “0” is “00000000”.
- the encoded data associated with the difference data “0” is not necessarily “00000000”, and may be associated with any appropriate difference data.
- a data transmission system has the effect to reduce the number of data transitions on n-bit signal lines between a data transmission device and a data reception device, and thereby reduce the power consumption and lower the EMI.
- Such a data transmission system is useful as a data transmission device that performs data transmission through parallel buses or the like.
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Abstract
Description
- 10 data transmission system
- 100 data transmission device
- 101 delay unit
- 102 arithmetic operation unit
- 103 encoding unit
- 110 data reception device
- 111 delay unit
- 112 arithmetic operation unit
- 113 decoding unit
- 20 data transmission system
- 200 data transmission device
- 201 first delay unit
- 202 first arithmetic operation unit
- 203 encoding unit
- 204 second arithmetic operation unit
- 205 second delay unit
- 210 data reception device
- 211 first delay unit
- 212 first arithmetic operation unit
- 213 decoding unit
- 214 second arithmetic operation unit
- 215 second delay unit
- 30 data transmission system
- 300 data write device
- 301 delay unit
- 302 arithmetic operation unit
- 303 encoding unit
- 310 data read device
- 311 delay unit
- 312 arithmetic operation unit
- 313 decoding unit
- 320 storage device
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JP2009140307A JP5384210B2 (en) | 2009-06-11 | 2009-06-11 | Data transmission device, data reception device, and data transmission system |
PCT/JP2010/003860 WO2010143429A1 (en) | 2009-06-11 | 2010-06-10 | Data transmitting apparatus, data receiving apparatus and data transmitting method |
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US8571092B2 (en) * | 2011-10-14 | 2013-10-29 | Texas Instruments Incorporated | Interconnect coding method and apparatus |
JP5908260B2 (en) * | 2011-11-18 | 2016-04-26 | ハンファテクウィン株式会社Hanwha Techwin Co.,Ltd. | Image processing apparatus and image processing method |
KR20150090634A (en) | 2014-01-29 | 2015-08-06 | 삼성전자주식회사 | Display driving intergrated circuit, display driving device and operation method of display driving intergrated circuit |
EP3907950B1 (en) * | 2019-02-26 | 2023-12-20 | Mitsubishi Electric Corporation | Distribution shaping method, distribution shaping terminating method, distribution shaping encoder, distribution shaping decoder, and transmission system |
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JP2010288078A (en) | 2010-12-24 |
US20120072799A1 (en) | 2012-03-22 |
WO2010143429A1 (en) | 2010-12-16 |
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