JP2002366107A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of reducing effectively spurious radiation in the transmission line of a data signal. SOLUTION: When picture data are inputted to a driving data generating part 2, a data compressing part 7 compresses and codes the picture data into transmission data consisting of data quantities which are different respectively for every one horizontal line. Then, a bit rate calculating part 9 adjusts a transmission frequency in accordance with the data quantities of the compressed and coded data. After such transmission data are transmitted from the driving data generating part 2 to a source driving means and the data are decoded, a source signal is supplied to source bus lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display device such as a liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a structure in which two glass substrates are fixed to face each other, and a liquid crystal is sealed in a gap therebetween. A transparent common electrode is formed on one glass substrate, and a large number of transparent pixel electrodes are formed in a matrix on the other glass substrate,
A circuit for individually applying a voltage to each pixel electrode is formed.

This active matrix type liquid crystal display device has a pixel matrix PX (i, j) of m rows and n columns (i = 1 to m,
j = 1 to n). In order to display this pixel matrix, m source lines and n gate lines that are orthogonal to each other are provided, and a liquid crystal element is provided at the intersection of the source lines and the gate lines. Here, the source line and the gate line are lines for supplying a signal voltage. Further, the source line and the gate line are connected to a source driving unit for driving the source line and a gate driving unit for driving the gate line, respectively.

Next, the operation of the active matrix type liquid crystal display device will be described. In the active matrix type liquid crystal display device, n gate lines G (j) (j
= 1 to n), and an image is displayed on one screen every fixed frame period (usually about 60 Hz to 85 Hz). At the time of displaying an image, a control signal required for driving, which is usually input to an input signal driving data generation unit of the liquid crystal display device, is sent to a source driving unit and a gate driving unit.

At this time, although the data of each pixel is transmitted by a control signal, since the frame frequency is constant, it is necessary to increase the number of display pixels and the gradation depth of the panel due to high definition. Therefore, the transmission data increases. Therefore, in this case, measures such as increasing the transmission frequency and increasing the number of signal wirings are performed, but this causes a problem that unnecessary radiation increases.

[0006] To address this problem,
JP-A-8-179265 discloses a method of compressing and transferring data. As a method for compressing data, for example, Japanese Patent Application Laid-Open No. 9-218667 describes
A compression method by serial / parallel conversion is disclosed.

In order to reduce the unnecessary radiation, it is also effective to reduce the change points of the signal on the transmission line. For example, Japanese Patent Application Laid-Open No. 5-334206 discloses a method of inverting the polarity as a method of reducing unnecessary radiation by checking data between signal lines running in parallel. This method is quite effective as a method for reducing unnecessary radiation.

[0008]

However, the size of the liquid crystal display device is increased, so that the length of the wiring path and the frame is increased, the transmission frequency is increased due to the high definition, and the number of gradation bits is increased due to the improvement of the color depth. As a result, the amount of unnecessary radiation of the liquid crystal display device is further increased due to an increase in transmission lines caused by the above. Therefore, the above method is becoming insufficient as a measure for reducing unnecessary radiation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a display device capable of effectively reducing unnecessary radiation in a data signal transmission line. .

[0010]

In order to solve the above-mentioned problems, a display device according to the present invention comprises a source driver for driving a source bus line for supplying a source signal to pixel portions arranged in a matrix. Means, and a drive data generator for supplying transmission data to the source driver based on the input image data, wherein the drive data generator performs a predetermined algorithm on the input image data. A data encoding unit that encodes a predetermined data block and generates transmission data having a different data amount for each data block; and a data encoding unit that encodes each data block according to the data amount of the data encoded by the data encoding unit. Transmission frequency adjustment means for adjusting the transmission frequency of the transmission data for each block, wherein the source drive means The transmission data transmitted from the data generation unit is characterized in that it comprises a decoding means for decoding as the source signal.

In the above configuration, first, when image data is input to the drive data generation unit, the image data is encoded by the data encoding means into transmission data having a different data amount for each predetermined data block. You. Then, the transmission frequency is adjusted by the transmission frequency adjusting unit in accordance with the data amount of the encoded data for each data block. Such transmission data is transmitted from the driving data generation unit to the source driving unit, and after being decoded by the decoding unit, the source signal is supplied to the source bus line. That is, the transmission frequency of the transmission data transmitted from the driving data generation unit to the source driving unit differs for each data block, and the transmission frequencies are dispersed. When the transmission frequency is dispersed in this way, unnecessary radiation generated at a constant multiple of the transmission frequency is also dispersed, so that the peak value of the unnecessary radiation can be reduced.

Further, in the display device according to the present invention, in the above configuration, the algorithm used in the encoding by the data encoding means may reduce the data amount of the encoded data rather than the data amount of the unencoded data. A configuration including a case where the amount is larger may be included.

According to the above configuration, the above-mentioned algorithm includes a case where the data amount of the encoded data is larger than the data amount of the data before encoding. Can be bigger. Therefore, the peak value of unnecessary radiation can be reduced efficiently.

Further, in the display device according to the present invention, in the above configuration, the algorithm used in the encoding by the data encoding means may, on average, be larger than the data amount of the data before the encoding. The configuration may be such that the data amount of data is smaller.

[0015] According to the above configuration, the above-mentioned algorithm, on average, becomes smaller than the data amount of the data before encoding.
Since the data amount of the encoded data is smaller, the data amount of the transmission data transmitted from the driving data generation unit to the source driving unit can be reduced. Therefore, it is possible to reduce the number of transmission paths for transmitting transmission data from the driving data generation unit to the source driving unit, so that unnecessary radiation can be reduced. Further, a decrease in the amount of data means that a transmission frequency is reduced, so that unnecessary radiation can be further reduced. However,
In a strict sense, data is not compressed, and unnecessary radiation is reduced by lowering the transmission frequency.

Further, according to the display device of the present invention, a source driving means for driving a source bus line for supplying a source signal to a pixel portion arranged in a matrix is provided. A drive data generating unit for supplying transmission data to the source driving unit; and a plurality of transmission paths for transmitting transmission data from the driving data generation unit to the source driving unit. The data is distributed to the plurality of transmission paths, and the bit string of the transmission data allocated to each transmission path is
Dividing into a unit bit string having a predetermined number of bits, calculating a coding unit bit string by performing a predetermined logical operation on this unit bit string, comparing the original unit bit string with the coding unit bit string, A unit bit string selecting unit for selecting a smaller number as transmission data, and the source driving unit includes a decoding unit for decoding transmission data transmitted from the driving data generation unit as the source signal. It is characterized by.

In the above configuration, first, when image data is input to the drive data generation unit, the image data is distributed to a plurality of transmission paths, and the bit string of the transmission data distributed to each transmission path is It is divided into a unit bit string having a predetermined number of bits. Then, the unit bit string selecting means calculates an encoded unit bit string obtained by performing a predetermined logical operation on the unit bit string, and compares the original unit bit string with the encoded unit bit string to find that the number of change points is small. Is selected as the transmission data. Such transmission data is transmitted from the driving data generation unit to the source driving unit via each transmission path, and after being decoded by the decoding unit, the source signal is supplied to the source bus line. That is, since the change point of the transmission data transmitted in each transmission path can be reduced, the polarity inversion of the signal in the transmission path is reduced, and the unnecessary radiation can be reduced.

Further, in the display device according to the present invention, in the above configuration, the predetermined logical operation performed by the unit bit string selecting means is exclusive of a bit string in which "0" and "1" are alternately repeated. It may be configured to be logical OR.

According to the above configuration, an encoding unit bit string is calculated by performing an exclusive OR operation on a unit bit string and a bit string in which 0 "and" 1 "are alternately repeated. By comparing the bit string with the coding unit bit string, the one with the smaller number of change points is selected as the transmission data, and the maximum value of the change point of the bit string selected in this way is 2 bits of the unit bit string. That is, since the maximum value of the number of transition points of the transmission data transmitted in each transmission path can be reduced to half, unnecessary radiation can be further reduced.

Further, in the display device according to the present invention, in the above-mentioned configuration, the driving data generation unit may include a parallel bit string composed of bits input to the plurality of transmission paths at the same timing, and The number of transition points with the parallel running bit sequence consisting of the bits input in, and a polarity-reversed parallel running bit sequence obtained by inverting the polarity of the parallel running bit sequence consisting of the bits input at the same timing for the plurality of transmission paths; The configuration may further include polarity inversion selecting means for comparing the number of transition points with the parallel bit string composed of bits input at the next timing and selecting the smaller number of transition points as transmission data. Good.

According to the above configuration, first, a transition point between a parallel running bit sequence composed of bits input at the same timing to a plurality of transmission paths and a parallel running bit sequence composed of bits input at the next timing. Is calculated. Further, a change point between a polarity-inverted parallel bit sequence obtained by inverting the polarity of a parallel bit sequence consisting of bits input at the same timing for a plurality of transmission paths and a parallel bit sequence consisting of bits input at the next timing Is calculated. Then, the polarity inversion selecting means selects the one with the smaller number of change points as transmission data. That is, it is possible to reduce the change of each bit when the parallel bit string is transmitted. At this time, when comparison is made with the polarity-inverted bit string whose polarity has been inverted as described above, the maximum value of the number of transition points of each bit of the transmission data can be reduced to half, so that unnecessary radiation Can be greatly reduced.

Further, in the display device according to the present invention, in the above configuration, the driving data generation unit may include a parallel bit string composed of bits input to the plurality of transmission paths at the same timing, and And a code obtained by performing a predetermined logical operation on the parallel running bit string composed of the bits input at the same timing to the plurality of transmission paths. And comparing the number of transition points between the parallel running bit string and the parallel running bit string consisting of bits input at the next timing, and further comprising an encoding selecting means for selecting one having a smaller number of change points as transmission data. A configuration may be provided.

According to the above configuration, first, a transition point between a parallel running bit sequence composed of bits input at the same timing to a plurality of transmission paths and a parallel running bit sequence composed of bits input at the next timing. Is calculated. Furthermore, a coded parallel running bit sequence obtained by performing a predetermined logical operation on a parallel running bit sequence consisting of bits input at the same timing to a plurality of transmission paths, and a parallel running bit sequence consisting of bits input at the next timing The number of points of change from the bit string is calculated. Then, the encoding selection unit selects the one with the smaller number of change points as transmission data. That is,
Since it is possible to reduce the time change of each bit when the parallel bit string is transmitted, unnecessary radiation can be further reduced.

Further, in the display device according to the present invention, in the above configuration, the predetermined logical operation performed by the encoding selecting means is exclusive of a bit string in which “0” and “1” are alternately repeated. It may be configured to be logical OR.

According to the above configuration, an encoded parallel running bit sequence is calculated by performing an exclusive OR operation on the parallel running bit sequence and a bit sequence in which 0 "and" 1 "are alternately repeated. The maximum value of the change point of each bit when the parallel bit sequence thus selected is transmitted is one half of the number of bits of the parallel bit sequence. That is, the maximum value of the number of change points of each bit when the parallel bit stream is transmitted can be reduced to half, so that unnecessary radiation can be further reduced.

Further, the display device according to the present invention comprises a display panel comprising pixel portions arranged in a matrix, a source driving means for driving a source bus line for supplying a source signal to the pixel portion, and an input device. A drive data generation unit that supplies transmission data to the source drive unit based on the input image data. The drive data generation unit can represent each pixel data in the input image data on the display panel. Data conversion means for converting to the closest color among the various colors.

In the above configuration, first, when image data is input to the drive data generation unit, the input pixel data is converted to the closest color among the colors that can be expressed on the display panel by the data conversion means. Is converted. here,
In many cases, colors that can be expressed on a display panel have a narrower range than colors expressed by original pixel data. That is, the data converted by the data conversion means has a smaller amount of information than the original pixel data. Then, the transmission data thus converted is transmitted from the driving data generation unit to the source driving unit, and the source signal is supplied to the source bus line. Therefore, the information amount of transmission data transmitted from the driving data generation unit to the source driving unit can be reduced, so that the transmission frequency can be reduced and the number of required transmission paths is reduced. be able to. Therefore, unnecessary radiation can be reduced.

Further, according to the display device of the present invention, a source driving means for driving a source bus line for supplying a source signal to pixel units arranged in a matrix, A drive data generation unit that supplies transmission data to the source drive unit, wherein the drive data generation unit converts each pixel data in the input image data into a pixel value that allows a human to recognize the difference on the display screen. It is characterized by having visual model conversion means for conversion.

In the above configuration, first, when image data is input to the drive data generation unit, the visual model conversion means converts each of the input pixel data to a pixel on a display screen by which a human can recognize the difference. Converted to a value. Here, the range of pixel values on which a difference can be recognized by a human on the display screen is often narrower than the pixel value of the original pixel data. That is, the data converted by the visual model conversion means has a smaller amount of information than the original pixel data. Then, the transmission data thus converted is transmitted from the driving data generation unit to the source driving unit, and the source signal is supplied to the source bus line. Therefore, since the amount of information of the transmission data transmitted from the driving data generation unit to the source driving unit can be reduced, the transmission frequency can be reduced, and
The number of transmission paths required can be reduced. Therefore, unnecessary radiation can be reduced.

Further, in the display device according to the present invention, in the above configuration, the visual model conversion means calculates a luminance value of each pixel data in the input image data, and calculates a difference between the luminance values of the adjacent pixels. Is determined, and the difference between the luminance values and the difference between the luminance values at which a human can recognize the difference on the display screen is set, whereby the amount of information required for the pixel data is set. The pixel value may be converted into such a value as follows.

Human vision has a very sensitive property with respect to changes in luminance. Here, as in the above configuration, if the pixel data is converted by considering the difference in luminance value between adjacent pixels, the amount of information can be reduced in a range that cannot be recognized by humans.

[0032]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.
It is as follows.

The liquid crystal display device (display device) 1 according to the present embodiment is connected to an external information processing device via a video board for digitizing image data, for example, as shown in FIG. , A gate driving unit 4..., And a liquid crystal display panel (display panel) 5.

The drive data generator 2 generates a drive signal (drive data) for operating the source driver 3 and the gate driver 4 based on the image data input from the external information processing device. Circuit. The signals generated here are output to the source driving means 3 and the gate driving means 4, respectively.

The source driving means 3 includes a driving data generator 2
This is a circuit for applying a voltage to a source line arranged vertically to the liquid crystal panel in order to drive the liquid crystal display panel 5 based on a signal from the liquid crystal display panel. The source driving means 3 supplies a voltage based on the driving data to each source line.

The gate driving means 4 includes a driving data generation unit 2
In order to drive the liquid crystal display panel 5 based on a signal from the liquid crystal panel, a circuit for applying a voltage for driving an active matrix to gate lines horizontally arranged on the liquid crystal panel.
The gate driving means 3 applies a voltage to a gate line to be driven.

The liquid crystal display panel 5 is a circuit that operates by applying a voltage to the source line and the gate line by the source driving means 3 and the gate driving means 5, and displays an image based on input image data. Do.

The liquid crystal display panel 5 has a structure in which two glass substrates are fixed to face each other, and a liquid crystal is sealed in a gap therebetween. A transparent common electrode is formed on one glass substrate, a large number of transparent pixel electrodes are formed in a matrix on the other glass substrate, and a circuit for individually applying a voltage to each pixel electrode is provided. Is formed.

The liquid crystal display panel 5 has a pixel matrix PX (i, j) (i = 1 to m, j = 1 to n) of m rows and n columns. To display this pixel matrix, the orthogonal m
There are provided two source lines and n gate lines, and a liquid crystal element is provided at the intersection of the source line and the gate line. Then, the n gate lines G (j) (j = 1 to n) are sequentially scanned, so that the gate lines G (j) are scanned at regular intervals (usually 60 Hz to 85 Hz).
(approximately z), one screen of image is displayed.

As shown in FIG. 1, the drive data generation unit 2 includes a source signal generation unit 6, a data compression unit (data encoding unit) 7, a buffer memory 8, a bit rate calculation unit (transmission frequency adjustment unit) 9, The configuration includes a clock generation unit 10, a modulation data generation unit 11, and a gate signal generation unit 12.

The source signal generator 6 is configured to generate a source buffer 14 in the source driver 3 based on the image data.
(To be described later) and a source voltage generation unit 15 (to be described later)
Is a circuit that generates a signal for driving the. The data generated by the source signal generator 6 is output to the data compressor 7.

The data compression section 7 is a circuit for compressing data. The compressed data generated by the data compression unit 7 is output to the buffer memory 8 and the compression status is output to the bit rate calculation unit 9.

The buffer memory 8 is a circuit for temporarily storing compressed data. The compressed data temporarily stored in the buffer memory 8 is output to the modulation data generator 11.

The bit rate calculator 9 calculates the bit rate required for transmitting the compressed data based on the compression status.
This is a circuit that calculates the required frequency. The information on the frequency calculated by the bit rate calculator 9 is output to the clock generator 10.

The clock generator 10 is a circuit that generates a clock for transmitting compressed data based on frequency information. The clock generated by the clock generator 10 is output to the modulation data generator 11.

The modulation data generator 11 is a circuit for generating data to be transmitted to the source driver 3. The modulation data generator 11 outputs data read from the buffer memory to the source driver 3 in synchronization with the clock generated by the clock generator 14.

The gate signal generator 12 is a circuit for generating a control signal for controlling the gate driving means 4 based on display data. The control signal and the clock generated by the gate signal generation unit 12
Is output to

The source driving means 3, as shown in FIG.
The configuration includes a data decompression (decoding means), a source buffer 14, and a source voltage generation unit 15.

The data decompression unit 13 includes the drive data generation unit 2
Is a circuit that expands the data that has been compressed and converts it into voltage value information applied to each source line and a control signal. The information on the voltage value generated by the data decompression unit 13 is output to the source buffer 14.

The source buffer 14 is a circuit that stores one line of data and outputs the data to the source voltage generator 15 based on a control signal. Source voltage generator 1
Reference numeral 5 denotes a circuit that generates a voltage to be applied to a source line in the liquid crystal display panel 5. This source voltage generator 1
The voltage generated by 5 is applied to each source line for driving the liquid crystal.

The liquid crystal display device 1 of the present embodiment is configured as described above to reduce the amount of data transmitted between the drive data generator 2 and the source driver 3. As a result, reduction of the number of data transmission lines, reduction of unnecessary radiation due to lowering of the transmission frequency, and diffusion of unnecessary radiation peak due to change in frequency are realized, and unnecessary radiation is reduced. Hereinafter, the display operation of the liquid crystal display device 1 will be described more specifically.

As a specific example of the first embodiment, an 8-bit U
Consider a liquid crystal display device having an XGA frame frequency of 75 Hz. VESA (The Video Electronics Standards Assoc
According to the standard, this liquid crystal display device has the following specifications: gradation bit number 8 bits for each color number of horizontal pixels 1600 pixels number of vertical pixels 1200 pixels pixel clock 202.5 MHz horizontal frequency 93.750 kHz (2160 pixels) ) The vertical frequency is 75,000 Hz (1250 lines).

The display operation of the liquid crystal display device 1 of the present embodiment is performed in the following sequence. First, image data is input to the liquid crystal display device 1. This image data is first input to the drive data generator 2.

In the drive data generator 2, the input image data is first input to the source signal generator 6. The source signal generation unit 6 controls the source buffer 14 and the source voltage generation unit 15 in the source driving unit 3 based on the input image data, in order to control the source buffer 14 and the source voltage generation unit 15. , A control signal of a latch pulse LS indicating a timing of switching the output voltage to the voltage value recorded in the source buffer, and data of each pixel.

In the case of an 8-bit color liquid crystal display device, the data output from the source signal generator 6 is SSP (1
Bits), LS (1 bit), R0 to R7 (red data, 8 bits), G0 to G7 (green data, 8 bits), and B0 to B7 (blue data, 8 bits), totaling 26 bits. Drive data to be configured. FIG. 4 shows a diagram of one line of the drive data. In the figure, R0 to R7, G0 to G7, and B0 to B7
There is a gap between the end timing of the data and the pulse timing of the LS because the internal processing in the source driving unit 3 is delayed. The reason why the pulse width of LS is large is that the processing time of data switching of the source voltage generation unit 15 is taken into consideration. In the present embodiment, the interval between the data end timing and the LS pulse timing is 6 clocks, and the LS width is 3 clocks.
The data thus converted is output to the data compression unit 7.

In the data compression section 7, the start pulse SS
Processing is performed using data for one line from P to the latch pulse LS as one unit. In the present embodiment, 26-bit data is converted to 1600 clocks (1600 pixels).
+1 clock (SSP width) +6 clocks (data-LS
With a unit of (interval) +3 clocks (LS width) = 1610 clocks, a total of 41860 bits of data are processed. The data for one line is compressed in the data compression unit 7.

Examples of the compression method include a one-dimensional compression method, a Huffman coding method, an arismetric coding method, and the like. Any compression method may be adopted, and a method combining these compression methods may be used. May be adopted. In the present embodiment, a case will be described below in which data for one clock is encoded using Huffman encoding.

The Huffman coding method is a method of performing coding based on the existence ratio of each code. First, the codes having a fixed occurrence rate are a code when the SPP is “1” and a code when the LS is “1”, and the occurrence rate of the code when the SPP is “1” is 1610 minutes. 1, the occurrence rate of the code whose LS is "1" is 3/1610. In addition, since all the data become "0" in the six clocks from the end of the data to the LS, this code is generated with a probability of at least 6/1610. From the above, the smallest data amount after compression is R0 to R7, G0 to G7, B0.
The screen becomes a solid black screen composed of codes in which the data of B7 are all "0". At this time, the presence ratio and code length of each code are as shown in Table 1 below. The data amount after compression in this case is 1614 bits.

[0059]

[Table 1]

The largest data amount after compression is a screen in which the occurrence probabilities of “0” and “1” of the data of R0 to R7, G0 to G7, and B0 to B7 are evenly close. At this time, the presence ratio and code length of each code are as shown in Table 2 below. In Table 2, X means 0 or 1. In this case, the data amount after compression is 38510 bits.

[0061]

[Table 2]

As described above, the compressed data is 1614 to 385
It becomes 10 bits. The compressed data is stored in the buffer memory 8
Is stored in Then, information on the data amount after compression is output to the bit rate calculation unit 9.

The bit rate calculator 9 calculates the time between start pulses based on the control signal, and calculates the horizontal frequency of one line. Then, the clock frequency is calculated from the data amount of the compressed data sent from the data compression unit 7 and the number of signal lines between the drive data generation unit 2 and the source drive unit 3.

The clock frequency is: clock frequency = (horizontal frequency) × (data amount of compressed data (Bit)) /
(The number of signal lines). In the case of this embodiment, if the cycle of one line is 93.750 kHz and the number of signal lines is 20, the data amount is 1614 to 38.
Since it is 510 bits, the clock frequency is 7.56
It will take a value between 6 MHz and 180.516 MHz. The clock frequency thus determined is transmitted to the clock generator 10.

The clock generator 10 generates a clock in accordance with the clock frequency sent from the bit rate calculator 14. At this time, the clock is modulated to reduce EMI. However, the number of clocks per line is not reduced as a result of the modulation. Then, the generated clock is output to the modulation data generation unit 11.

The modulation data generator 11 reads out the compressed data stored in the buffer memory 8 using the clock generated by the clock generator 10. At this time, the write clock and the read clock of the buffer memory 8 are different. Therefore, the buffer memory 8 needs to be configured so that writing and reading can be performed with different clocks. Then, the modulation data generation unit 11
The clock generated by the clock generator 10 and the compressed data synchronized with the clock are output to the source driver 3.

The source driving means 3 includes a driving data generation unit 2
Receives the compressed data sent from. First, the data decompression unit 13 decodes and decompresses the input compressed data by performing the reverse procedure of the encoding performed in the data compression unit. As a result, the compressed data becomes SS
The data is returned to the data of P, LS, R0 to R7, G0 to G7, and B0 to B7. Then, these data are output to the source buffer 14.

The source buffer 14 receives the start pulse S
Based on the SP, information on the voltage applied to each source line is stored for each source line. The stored data and the latch pulse are output to the source voltage generation unit 15 at the timing of the latch pulse LS input after storing the data for one line.

The source voltage generator 15 generates a voltage to be supplied to each source line based on the information sent from the source buffer 14 and supplies it to each source line of the liquid crystal display panel 5. Further, it has a function of maintaining the potential until the next latch pulse LS is sent from the source buffer.

On the other hand, the gate signal generation section 12 in the drive data generation section 2 generates a control signal for driving the gate drive section 4 in synchronization with the output timing of the LS from the source voltage generation section 15, and generates the gate drive section. 4 is output. The control signal is a signal that enables the gate drive unit 4 to drive the gate line of the line displayed by the output of the switched source line based on the synchronization signal of the image data.

The gate driving means 4 includes the driving data generation unit 2
A voltage is applied to the gate line of the liquid crystal display panel 5 based on the control signal sent from. Thus, one line is displayed.

By the above processing, one line can be displayed, and by repeating this for all the horizontal lines of the screen, the entire screen can be displayed. The reason why the data is compressed and expanded line by line is to make the luminance of the screen uniform. This is because the time for one line is equal to the charging time of the liquid crystal. If the charging time is different, the potential charged in the liquid crystal changes and the luminance changes, so that the luminance uniformity of the screen is impaired.

However, the processing related to data compression / expansion must not be performed for each line (horizontal line), but may be performed for each predetermined data block as described below.

For example, when the data in one horizontal line is excessive, it is more efficient to divide the data into a plurality of data blocks in one horizontal line and perform the processing. This is because if the amount of data to be processed increases, the delay time for the processing also increases, so that it is necessary to increase the scale of the hardware that performs the processing.

When the number of data in one horizontal line is too small, it is more efficient to process the data included in a plurality of horizontal lines as one data block. this is,
This is because if the number of data included in one data block is too small, the change in the compression ratio becomes small and the efficiency becomes poor.

In the case of a large liquid crystal module, the left half and the right half are processed independently, or substrates are arranged vertically to process odd and even data independently. There are cases. As described above, when one horizontal line is divided in a hardware manner, processing must be performed by dividing the data into data blocks corresponding to the respective horizontal lines.

When data transmission is performed after performing data compression according to such a sequence, it is possible to reduce the data transfer amount in the path from the driving data generation unit 2 to the source driving means 3. In this embodiment, the transmission frequency is from 202.5 MHz to 7.566 MHz to 180.5 MHz.
Since the transmission speed is reduced to 16 MHz and the number of transmission lines is reduced from 26 to 20, unnecessary radiation can be reduced accordingly. Assuming that the transmission frequency is 94.041 MHz, which is the average value, in the calculation, the reduction amount is reduced by about 6.7 dB because the power is proportional to the square of the frequency, and reduced by about 1.1 dB due to the reduction of the transmission line. I do. Further, since the driving frequency is spread by the difference of the transfer information amount between each line, the peak of the unnecessary radiation amount is reduced at a frequency which is a constant multiple of the transmission frequency. In addition, since the wiring area can be reduced, driving components such as a substrate can be reduced in size.

Embodiment 2 Another embodiment of the present invention will be described below with reference to FIGS. 5 to 7. The components having the same functions as those described in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The liquid crystal display device (display device) 1 according to the present embodiment is connected to an external information processing device via a video board for digitizing image data, for example, as in the first embodiment. As shown in FIG. 5, a driving data generator 16, source driving means 17, gate driving means 4, and a liquid crystal display panel (display panel) 5 are provided. That is, the liquid crystal display device 1 according to the present embodiment has the same configuration as the configuration shown in FIG. 2 in the first embodiment, except that the internal configurations of the drive data generation unit and the source drive unit are different. It is different.

As shown in FIG. 6, the drive data generation section 16 includes a source signal generation section 18, an EXOR conversion section (unit bit string selection means) 19, and a polarity conversion section (polarity inversion selection means).
20 and a gate signal generation unit 21.

The source signal generator 18 is a circuit for generating a control signal for operating the source driver 17 from image data. The control signal created by the source signal generator 18 is output to the EXOR converter 19.

The EXOR conversion section 19 calculates the number of signal changes between the case where the control signal is transmitted as it is and the case where the signal and the matrix (010101010101... Is a circuit for comparing. As a result of the comparison, the EXOR conversion unit 19 converts the signal having the smaller change point and the selection information into the polarity conversion unit 20.
Output to

The polarity conversion unit 20 is a circuit that monitors all signal lines used in transmission and compares a case where the signal is transmitted as it is with each clock and a case where the polarity of the signal is inverted. The signal of the polarity converter 20 that is determined to have a small number of change points and the selection information are output to the source driver 17.

The gate signal generating section 21 is a circuit for generating a control signal for controlling the gate driving means 4 based on the display data. The gate signal generation unit 21 outputs a control signal and a clock to the gate driving unit 4.

As shown in FIG. 7, the source driving means 17 includes a polarity decoder 22, an EXOR decoder 23, a source buffer 24, and a source voltage generator 25.

The polarity decoding section 22 is provided with the driving data generation section 16.
This is a circuit that decodes the data sent from, based on the polarity information included in the data. The data decoded by the polarity decoding unit 22 is output to the EXOR decoding unit 23.

The EXOR decoding section 23 is a circuit for decoding based on the exclusive OR information included in the data of the polarity decoding section 22. The data decoded by the EXOR decoding unit 23 is output to the source buffer 24.

The source buffer 24 includes the EXOR decoding unit 2
3 is a circuit for temporarily storing the data for one line sent from 3. And this source buffer 24
The data is output to the source voltage generator 25 based on the control signal.

The source voltage generator 25 is a circuit for generating a voltage applied to the source line of the liquid crystal display panel 5 for driving the liquid crystal.

The liquid crystal display device 1 according to the present embodiment is configured as described above, so that it is possible to reduce a change point in the transmission data between the drive data generator 16 and the source driver 17. Has become. As a result, it is possible to reduce a voltage change that is a source of unnecessary radiation, and to reduce unnecessary radiation. Hereinafter, the display operation of the present liquid crystal display device will be described more specifically.

As a specific example of this embodiment, an 8-bit UX
Consider a liquid crystal display device with a GA frame frequency of 75 Hz.
According to the VESA standard, this liquid crystal display device has the following specifications: the number of gradation bits 8 bits for each color number of horizontal pixels 1600 pixels number of vertical pixels 1200 pixels pixel clock 202.5 MHz horizontal frequency 93.750 kHz (2160 pixels) The vertical frequency is 75.000 Hz (1250 lines).

The display operation in the liquid crystal display device 1 of the present embodiment is performed in the following sequence. First, image data is input to the liquid crystal display device 1. This image data is first input to the drive data generator 16.

In the drive data generator 16, the input image data is first input to the source signal generator 18.
The source signal generation unit 18 outputs a signal to the source buffer 24 in the source driving unit 17 based on the input image data.
And a start pulse SSP indicating the start of scanning of one line of data to control the source voltage generation unit 25, and a latch pulse indicating the timing of switching the output voltage to the voltage value recorded in the source buffer 24 It is converted into an LS control signal and data of each pixel.

In the case of an 8-bit color liquid crystal display device, the data output from the source signal generator 18 is SSP
(1 bit), LS (1 bit), R0 to R7 (red data, 8 bits), G0 to G7 (green data, 8 bits), and B0 to B7 (blue data, 8 bits), totaling 26 The drive data is composed of bits. The data converted in this way is output to the EXOR conversion unit 19.

The EXOR conversion unit 19 is configured to output the transmission signal between the driving data generation unit 16 and the source driving units 17.
R0 to R7, G0 to G7 representing information of each pixel,
The processing is performed for each of the signal lines B0 to B7.

First, the number of bit changes (the number of times of changing from 0 → 1 or 1 → 0) of data in a specific section of one signal line (for example, for one line, for one source driving means, etc.) is counted. . Next, for each bit of the same data,
An exclusive OR with data in which 0s and 1s are alternately arranged such as "0101010101 ..." is calculated. Then, the number of bit changes in the calculation result is counted, and the number of bit changes is compared.

For example, “10010110000101”
Assume a data sequence of "0000100100". The change point of this data is 13. This data sequence and "010101010101010101101010"
When the exclusive OR of “10” is calculated, “1100001” is obtained.
101000001011100110 ", and the change point at this time is 11. As a result, the number of change points is smaller when the exclusive OR is taken, so that the one taking the exclusive OR is selected.

The maximum value of the change point of the sequence selected by this operation is one half of the number of data. In the case where the number of pixels in one line is 1600, a maximum of 1600 change points occur in normal transmission, but according to the above method,
Only a maximum of 800 transition points will occur. Then, the selected data having the smaller number of changes and the conversion information are output to the polarity converter 20.

In the above, data of a specific section of one signal line, ie, a unit bit string,
It is configured to calculate an encoding unit bit string by performing an exclusive OR operation with a bit string in which 0s and 1s are alternately arranged, such as “0101010101...”. Here, a bit string of “1010101010...” May be used instead of the bit string of “0101010101.

Further, for the unit bit string, 0
It is also possible to calculate an encoding unit bit string by performing an exclusive OR operation with an arbitrary bit string having the same number of 1s and 1s, and select the one with the smallest change number as transmission data. In this case, the number of changes may be further reduced.

As means for comparing the number of changes,
A comparator or the like can be used.

The polarity converter 20 is provided with the drive data generator 16
R0 to R7, G0 to G7, B0 representing information of each pixel in the transmission signal between the source driving means 17 and.
The number of bit changes of each of the signals B7 to B7 is counted. When the polarity is reversed, (data bit number)-
(The number of bit changes) is the number of changes.

For example, the n-th pixel signal of a certain line is (R0-R7, G0-G7, B0-B7) = (10
010100001010000100110), and the output of the (n-1) th pixel signal is (R0 to R7,
G0-G7, B0-B7) = (00101100001)
010001001101), there are 14 change points. When the polarity of the n-th signal is inverted, (RO to R
7, GO-G7, BO-B7) = (011010011)
110101111011001). The number of change points at this time is ten. As a result, the polarity inversion is selected.

The maximum value of the change point in this operation is one half of the bit number of the pixel signal. That is, in a normal transmission, 24 change points occur for a 24-bit signal, but according to the above method, only a maximum of 12 change points occur. Then, the signal having the smaller change point and the information of the polarity inversion are output to the source driver 17.

The source driver 17 receives the data sent from the drive data generator 16. First, the polarity decoding unit 22 extracts the information of the polarity inversion from the data sent from the driving data generation unit 16, and restores the part where the polarity inversion has been performed based on the information. And
The data restored in the polarity decoding unit 22 is output to the EXOR decoding unit 23.

The EXOR decoding unit 23 extracts exclusive OR information from the input data, and based on the extracted information,
The data of the signal line to which exclusive OR is applied,
The exclusive OR of “0101010101...” And the same data as used for encoding is calculated, and SSP, LS,
The information is returned to R0 to R7, G0 to G7, and B0 to B7. The returned data is output to the source buffer 24.

The source buffer 24 supplies the start pulse S
Based on the SP, information on the voltage applied to each source line is stored for each source line. The stored data and the latch pulse are output to the source voltage generation unit 25 at the timing of the latch pulse LS input after storing the data for one line.

The source voltage generation section 25 generates a voltage to be supplied to each source line based on the information sent from the source buffer 24 and supplies the voltage to the source line of the liquid crystal display panel 5. Further, it has a function of maintaining the potential until the next latch pulse LS is sent from the source buffer 24.

On the other hand, the gate signal generation unit 21 in the drive data generation unit 16
A control signal for driving the gate driving means 4 is generated in synchronism with the output timing of, and output to the gate driving means 4. The control signal is a signal that allows the gate drive unit 4 to drive the gate line of the line displayed by the output of the switched source line based on the synchronization signal of the image data.

The gate driving means 4 includes the driving data generator 1
A voltage is applied to the gate line of the liquid crystal display panel 5 based on the control signal sent from the control signal 6. This gives 1
A line is displayed.

By the above processing, one line can be displayed, and by repeating this for all the horizontal lines on the screen, the entire screen can be displayed. When transmission is performed according to such a sequence, it is possible to reduce the number of change points of transmission data in a path from the driving data generation unit 16 to the source driving units 17.
In the present embodiment, the maximum number of change points can be reduced to one half by the processing by the EXOR conversion unit 19 and the maximum number of change points can be further reduced to one half by the processing by the polarity conversion unit 20. It will be a fraction. Maximum number of change points is 4
When it is reduced by a factor of 1, the maximum unnecessary radiation is reduced by about 6 dB.

[Embodiment 3] Another embodiment of the present invention will be described below with reference to FIGS. The components having the same functions as those described in each of the above-described embodiments will be denoted by the same reference numerals, and description thereof will be omitted.

The liquid crystal display device (display device) 1 according to the present embodiment is connected to, for example, an external information processing device via a video board for digitizing image data, similarly to the first and second embodiments. As shown in FIG. 8, a driving data generator 26, source driving means 27, gate driving means 4, and a liquid crystal display panel (display panel) 5 are provided. That is, the liquid crystal display device 1 according to the present embodiment differs from the liquid crystal display device 1 in the first embodiment in FIG.
And the configuration shown in FIG. 5 and the configuration shown in FIG. 5 in the second embodiment. The different point is that the internal configurations of the drive data generation unit and the source drive unit are different. .

As shown in FIG. 8, the drive data generation unit 26 includes a source signal generation unit 28, an EXOR1 conversion unit (unit bit string selection unit) 29, an EXOR2 conversion unit (encoding selection unit) 30, and a gate signal generation unit 31. Is provided.

The source signal generator 28 is a circuit for generating a control signal for operating the source driver 27 from image data. The control signal created by the source signal generator 28 is output to the EXOR1 converter 29.

The EXOR1 conversion unit 29 provides, for each signal line,
This circuit compares the number of signal changes between the case where the control signal is transmitted as it is and the case where an exclusive OR of the signal and the matrix (0101010101...) Is obtained. Then, the EXOR1 conversion unit 29 calculates
The signal with the smaller change point and the selection information are output to the EXOR2 conversion unit 30.

The EXOR2 conversion unit 30 monitors all the signal lines used for transmission, and outputs an E-
The exclusive OR with the XOR2 reference signal (1/2 is "0" and the remaining half is "1") is calculated, and the signal obtained by inverting the polarity of the EXOR2 reference signal with respect to the signal. This is a circuit for performing a comparison with a case where an exclusive OR is calculated. Then, as a result of the comparison, the EXOR2 conversion unit 30 outputs the signal having the smaller change point and the selection information to the source driving unit 27. The EXOR1 conversion unit 2
The EXOR circuit 9 and the EXOR2 conversion section 30 need not necessarily be EXOR circuits as long as they can extract a change point, and can be realized by, for example, a comparator.

The gate signal generating section 31 is a circuit for generating a control signal for controlling the gate driving means 4 based on the display data. The gate signal generator 31 outputs a control signal and a clock to the gate driving unit 4.

As shown in FIG. 10, the source driver 27 has an EXOR2 decoder 32, an EXOR1 decoder 33, a source buffer 34, and a source voltage generator 35.

The EXOR2 decoding unit 32 decodes the data sent from the drive data generation unit 26 based on the exclusive OR information added in the EXOR2 conversion unit 30 included in the data. Circuit. This E
The data decoded by the XOR2 decoding unit 32 is EXO
This is output to the R1 decoding unit 33.

The EXOR1 decoding section 33 is a circuit for decoding based on the exclusive OR information added in the EXOR1 conversion section 29 and included in the data input from the EXOR2 decoding section 32. The data decoded by the EXOR1 decoding unit 33 is output to the source buffer 34.

The source buffer 34 is a circuit for temporarily storing one line of data sent from the EXOR1 decoding unit 33. And this source buffer 34
Transmits data based on the control signal to the source voltage generation unit 3.
5 is output.

The source voltage generator 35 is a circuit for generating a voltage applied to the source line of the liquid crystal display panel 5 for driving the liquid crystal.

The liquid crystal display device 1 according to the present embodiment is configured as described above, so that it is possible to reduce a change point in transmission data between the driving data generation unit 26 and the source driving means 27. Has become. As a result, a voltage change that is a source of unnecessary radiation can be reduced, and unnecessary radiation can be reduced. Hereinafter, the display operation of the present liquid crystal display device will be described more specifically.

As a specific example of this embodiment, an 8-bit UX
Consider a liquid crystal display device with a GA frame frequency of 75 Hz.
According to the VESA standard, this liquid crystal display device has the following specifications: the number of gradation bits 8 bits for each color The number of horizontal pixels 1600 pixels The number of vertical pixels 1200 pixels Pixel clock 202.5 MHz Horizontal frequency 93.750 kHz (2160 pixels) The vertical frequency is 75.000 Hz (1250 lines).

The display operation in the liquid crystal display device 1 of the present embodiment is performed in the following sequence. First, image data is input to the liquid crystal display device 1. The image data is first input to the drive data generation unit 26.

In the drive data generator 26, the input image data is first input to the source signal generator 28.
The source signal generation unit 28 controls the source buffer 34 in the source driving unit 27 based on the input image data.
And a start pulse SSP indicating the start of scanning of one line of data in order to control the source voltage generation unit 35, and a latch pulse indicating the timing of switching the output voltage to the voltage value recorded in the source buffer 34 It is converted into an LS control signal and data of each pixel.

In the case of an 8-bit color liquid crystal display device, data output from the source signal generation unit 28 is SSP
(1 bit), LS (1 bit), R0 to R7 (red data, 8 bits), G0 to G7 (green data, 8 bits), and B0 to B7 (blue data, 8 bits), totaling 26 The drive data is composed of bits. The data thus converted is output to the EXOR1 conversion unit 29.

The EXOR1 converter 29 includes R0 to R7, G0 to G7 representing information of each pixel in the transmission signal between the drive data generator 26 and the source driver 27.
7, processing is performed for each of the signal lines B0 to B7.

First, the number of bit changes (the number of times of changing from 0 → 1 or 1 → 0) of data in a specific section of one signal line (for example, one line, one source driving means, etc.) is counted. . Next, for each bit of the same data,
An exclusive OR with data in which 0s and 1s are alternately arranged such as "0101010101 ..." is calculated. Then, the number of bit changes in the calculation result is counted, and the number of bit changes is compared.

For example, “10010110000101”
Assume a data sequence of "0000100100". The change point of this data is 13. This data sequence and "010101010101010101101010"
When the exclusive OR of “10” is calculated, “110000” is obtained.
1101000001011100110 ", and the change point at this time is 11. As a result, the number of change points is smaller when the exclusive OR is obtained, so that the exclusive OR is selected.

The maximum value of the change point of the sequence selected by this operation is の of the number of data. In the case where the number of pixels in one line is 1600, a maximum of 1600 change points occur in normal transmission, but according to the above method,
Only a maximum of 800 transition points will occur. Then, the data with the smaller number of changes selected in this way and its conversion information are output to the EXOR2 conversion unit 30.

In the above description, data of a specific section of one signal line, that is, a unit bit string,
It is configured to calculate an encoding unit bit string by performing an exclusive OR operation with a bit string in which 0s and 1s are alternately arranged, such as “0101010101...”. Here, a bit string of “1010101010...” May be used instead of the bit string of “0101010101.

Further, 0 is added to the unit bit string.
It is also possible to calculate an encoding unit bit string by performing an exclusive OR operation with an arbitrary bit string having the same number of 1s and 1s, and select the one with the smallest change number as transmission data. In this case, the number of changes may be further reduced.

As means for comparing the number of changes,
A comparator or the like can be used.

The EXOR2 converter 30 includes R0 to R7, G0 to G, which represent information of each pixel in the transmission signal between the drive data generator 26 and the source driver 27.
7, in each clock of the exclusive OR calculation result of the signals B0 to B7 and the EXOR2 reference signal and the exclusive OR calculation result of the signal and the signal obtained by inverting the polarity of the EXOR2 reference signal Count the number of bit changes,
The number of bit changes is compared.

For example, if the reference signal is (R0-R7, G0
G7, B0 to B7) = (01010101010101)
0101010101), and the n-th pixel signal of a certain line is (R0 to R7, G0 to G7, B0 to B
7) = (100101100001010000100)
110) and the output of the (n-1) th pixel signal is (R0-R7, G0-G7, B0-B7) = (0010)
11000010100001001101).
The calculation result of the exclusive OR with the EXOR2 reference signal is (1
100000110100000101110011), and there are 16 change points. The calculation result of the exclusive OR with the signal obtained by inverting the EXOR2 reference signal is (001)
111001011111010001100), and the number of change points is eight. EX with few changes
An exclusive OR with a signal obtained by inverting the polarity of the OR2 reference signal is selected.

The maximum value of the change point in this operation is one half of the bit number of the pixel signal. That is, in a normal transmission, 24 change points occur for a 24-bit signal, but according to the above method, only a maximum of 12 change points occur. Then, the signal having the smaller change point and the information of the polarity inversion are output to the source driver 27.

In the above description, the n-th pixel signal of a certain line, that is, a parallel bit string composed of bits input at the same timing to a plurality of transmission paths, has 0 bits such as “0101010101. An exclusive-OR operation is performed with a bit string in which 1 and 1 are alternately arranged to calculate an encoded parallel running bit string. Here, a bit string of “1010101010...” May be used instead of the bit string of “0101010101.

Further, for the parallel bit string, 0
It is also possible to calculate the coded parallel running bit sequence by performing an exclusive OR operation with an arbitrary bit sequence having the same number of 1 and 1 as the transmission data. In this case, the number of changes may be further reduced.

As means for comparing the number of changes,
A comparator or the like can be used.

The source driver 27 receives the data sent from the drive data generator 26. First, EXO
The R2 decoding unit 32 extracts the exclusive OR information added by the EXOR2 converting unit 30 from the data sent from the driving data generating unit 26, and restores the portion to which the exclusive OR information is applied to the original. . Then, the restored data is output to the EXOR1 decoding unit 33.

The EXOR1 decoding unit 33 extracts the exclusive OR information added by the EXOR1 conversion unit 29 from the input data. Then, based on the information, the exclusive OR of “0101010101...” And the same data used for encoding is calculated for the data of the signal line to which the exclusive OR is applied, and the SSP, L
S, return to the information of R0 to R7, G0 to G7, B0 to B7. The returned data is output to the source buffer 34.

The source buffer 34 supplies the start pulse S
Based on the SP, information on the voltage applied to each source line is stored for each source line. Then, the stored data and the latch pulse are output to the source voltage generation unit 35 at the timing of the latch pulse LS input after storing the data for one line.

The source voltage generator 35 generates a voltage to be supplied to each source line based on the information sent from the source buffer 34, and supplies it to the source line of the liquid crystal display panel 5. Further, it has a function of maintaining the potential until the next latch pulse LS is sent from the source buffer 34.

On the other hand, the gate signal generator 31 in the drive data generator 26
A control signal for driving the gate driving means 4 is generated in synchronism with the output timing of, and output to the gate driving means 4. The control signal is a signal that enables the gate drive unit 4 to drive the gate line of the line displayed by the output of the switched source line based on the synchronization signal of the image data.

The gate driving means 4 includes the driving data generation unit 2
A voltage is applied to the gate line of the liquid crystal display panel 5 based on the control signal sent from the control signal 6. by this,
The display of the first line is performed.

By the above processing, one line can be displayed, and by repeating this for all the horizontal lines of the screen, the entire screen can be displayed. When the transmission is performed according to such a sequence, the number of change points of the transmission data in the path from the driving data generation unit 26 to the source driving units 27 can be reduced.
In the present embodiment, the maximum change point can be reduced to half by the processing by the EXOR1 conversion unit 29 and further reduced to half by the processing by the EXOR2 conversion unit 30. It will be a fraction. When the maximum number of change points becomes a quarter, the maximum unnecessary radiation amount decreases by about 6 dB.

[Embodiment 4] Another embodiment of the present invention will be described below with reference to FIGS. The components having the same functions as those described in each of the above-described embodiments will be denoted by the same reference numerals, and description thereof will be omitted.

The liquid crystal display device (display device) 1 according to the present embodiment is connected to an external information processing device via, for example, a video board for digitizing image data, similarly to the above embodiments. As shown in FIG. 11, a driving data generator 36, source driving means 37, gate driving means 4, and a liquid crystal display panel (display panel) 5 are provided. That is, the liquid crystal display device 1 according to the present embodiment differs from the liquid crystal display device 1 in the first embodiment in FIG.
The difference is that the internal configurations of the drive data generation unit and the source drive unit are different.

As shown in FIG. 12, the drive data generator 36 includes a source signal generator 38, an LUT encoder (data converter) 39, and a gate signal generator 40.

The source signal generator 38 is a circuit for generating a control signal for operating the source driver 37 from image data. The control signal created by the source signal generator 38 is output to the LUT encoder 39.

The LUT encoding section 39 is a circuit that performs encoding using an LUT (lookup table). The encoded data generated by the LUT encoding unit 39 is output to the source driving unit 37.

The gate signal generating section 40 is a circuit for generating a control signal for controlling the gate driving means 4 based on the display data. The gate signal generator 31 outputs a control signal and a clock to the gate driving unit 4.

As shown in FIG. 13, the source driver 37 has an LUT decoder 41, a source buffer 42, and a source voltage generator 43.

The LUT decoding section 41 includes the driving data generation section 3
6 is a circuit that decodes the data sent from 6 by referring to the LUT. The data decoded by the LUT decoding unit 41 is output to the source buffer 42.

The source buffer 42 has the LUT decoding unit 41
This is a circuit for temporarily storing the data for one line sent from. Then, the source buffer 42 outputs data to the source voltage generator 43 based on the control signal.

The source voltage generator 43 is a circuit for generating a voltage applied to the source lines of the liquid crystal display panel 5 for driving the liquid crystal.

With the liquid crystal display device 1 of the present embodiment configured as described above, unnecessary radiation can be reduced by reducing the number of data transmission lines and lowering the transmission frequency. Hereinafter, the display operation of the present liquid crystal display device will be described more specifically.

The display operation in the liquid crystal display device 1 of the present embodiment is performed in the following sequence. First, image data is input to the liquid crystal display device 1. This image data is first input to the drive data generator 36.

In the drive data generator 36, the input image data is first input to the source signal generator 38.
The source signal generation unit 38 controls the source buffer 42 in the source driving unit 37 based on the input image data.
And a start pulse SSP indicating the start of scanning of one line of data to control the source voltage generation unit 43, and a latch pulse indicating the timing of switching the output voltage to the voltage value recorded in the source buffer 42 It is converted into an LS control signal and data of each pixel.

In the case of an 8-bit color liquid crystal display device, the data output from the source signal generator 38 is SSP
(1 bit), LS (1 bit), R0 to R7 (red data, 8 bits), G0 to G7 (green data, 8 bits), and B0 to B7 (blue data, 8 bits), totaling 26 The drive data is composed of bits. The data thus converted is output to the LUT encoding unit 39.

The LUT encoding section 39 converts the display data of each pixel included in the data using an LUT created in advance. L used here
The UT is a table for converting a color to be displayed by image data into a color closest to the color that can be expressed by the liquid crystal display panel 5. By performing conversion using such an LUT, unused color data is deleted, and information is compressed. This will be described in detail below.

The display conditions of the input image data and the display conditions of the liquid crystal display panel 5 are different from each other in terms of gradation curve, contrast and the like. Therefore, in order to perform a representation faithful to the image data, it is preferable to perform the above-described LUT conversion on the image data.

By performing such a conversion, the colors of a plurality of input image data are assigned to the colors of one liquid crystal display device, so that the amount of information is reduced. More specifically, for example, (R, G, B) = (0, 0, 0), (1,
The four codes of (0,0), (0,1,0), (0,0,1) are (R, G, B) = (0,0) in the liquid crystal display device.
If it is converted to (0,0), the amount of information is reduced because the code is reduced by three. As described above, by reducing the amount of information, it becomes possible to reduce the frequency of the transmission path and the transmission signal line.

The data thus converted is output to the source driver 37. Here, the image data is created on the assumption that it is displayed on a CRT display. Therefore, the data is based on the premise that the gradation curve is represented by a curve called γ = 2.2. If this curve is a monitor capable of displaying 256 gradations, the luminance Vx of gradation x is Vx = (x / 25)
5) It is expressed by ＾ 2.2 × (white luminance).

However, even if the liquid crystal display device has good performance, the black luminance is only about 1/500 of the white luminance, so that it is difficult to express several tens gradations close to black. When the black luminance is 1/500 of the white luminance, V0 to V15 in gray gradation fall into this area. Therefore, when these gradations are displayed on the liquid crystal display device, the liquid crystal display device has a display state in which the black luminance is closest, so that all the data of these gradations are assigned to the black code in the liquid crystal display device. . Conversely, colors that can be expressed by the same number of liquid crystal display devices are not used.

Since the chromaticity of the liquid crystal display device is shifted due to a change in gradation, it is necessary to correct the shift.
When such a correction is made, again, a plurality of color data
In a liquid crystal display device, it will be expressed in the same color,
Unused codes will result.

The source driver 37 receives the data sent from the drive data generator 36. First, LUT
The decoding unit 41 adds the data deleted by the LUT encoding unit to the data sent from the drive data generation unit 36, and returns the data of the color of the liquid crystal display panel 5 closest to the input image data. Then, the returned data is converted into information of a voltage applied to each source line of the liquid crystal display panel 5 and a control signal. This information is output to the source buffer 42.

The source buffer 42 supplies the start pulse S
Based on the SP, information on the voltage applied to each source line is stored for each source line. Then, at the timing of the latch pulse LS input after the data for one line is accumulated, the stored data and the voltage applied to the source line are changed to the voltage value stored at that time. The signal is output to the source voltage generator 43.

The source voltage generator 43 generates a voltage to be supplied to each source line based on the information sent from the source buffer 42, and supplies the voltage to the source line of the liquid crystal display panel 5. Further, it has a function of maintaining the potential until a control signal for changing the next voltage value is sent from the source buffer 42.

On the other hand, the gate signal generation section 40 in the drive data generation section 36 generates a control signal for driving the gate drive section 4 in synchronization with the switching in the source buffer 42 and outputs the control signal to the gate drive section 4. . The control signal is a signal that enables the gate drive unit 4 to drive the gate line of the line displayed by the output of the switched source line based on the synchronization signal of the image data.

The gate driving means 4 includes the driving data generation unit 2
A voltage is applied to the gate line of the liquid crystal display panel 5 based on the control signal sent from the control signal 6. by this,
The display of the first line is performed.

With the above processing, one line can be displayed, and by repeating this for all the horizontal lines of the screen, the entire screen can be displayed. When transmission is performed according to such a sequence, the information amount of transmission data in the path from the driving data generation unit 26 to the source driving unit 27... Decreases, so that the frequency of the transmission path and the transmission signal line are reduced. It becomes possible.

[Embodiment 5] Another embodiment of the present invention will be described below with reference to FIGS. The components having the same functions as those described in each of the above-described embodiments will be denoted by the same reference numerals, and description thereof will be omitted.

The liquid crystal display device (display device) 1 according to the present embodiment is connected to an external information processing device via a video board for digitizing image data, for example, as in the above embodiments. As shown in FIG. 14, a driving data generator 46, source driving means 47, gate driving means 4, and a liquid crystal display panel (display panel) 5 are provided. That is, the liquid crystal display device 1 according to the present embodiment differs from the liquid crystal display device 1 in the first embodiment in FIG.
The difference is that the internal configurations of the drive data generation unit and the source drive unit are different.

As shown in FIG. 15, the driving data generator 46 includes a source signal generator 48, a stimulus value converter 49, a visual model calculator (visual model converter) 50, a bit allocator 51, and a quantizer. 52, a line memory 53, a buffer memory 54, a bit rate calculator 55, a clock generator 56, a modulation data generator 57, and a gate signal generator 58.

The source signal generator 48 is a circuit for generating a control signal for operating the source driver 47 from image data. The control signal created by the source signal generator 48 is output to the tristimulus value converter 49.

The tristimulus value converter 49 converts the information of each pixel into a CIE (Commission International Commission: Commission International).
al de l'Eclairage) is converted into tristimulus values X, Y, Z of 1931. Then, the converted data is output to the visual model calculation unit 50 and the quantization unit 52.

The visual model calculation unit 50 recognizes that the human eye has a characteristic that the sensitivity to the edge of the luminance is strong and the sensitivity to the absolute value of the luminance and the absolute value of the chromaticity is weak. Calculate the precision required for the stimulus value. Then, the amount of information required for each pixel is output to the bit distribution unit 51.

The bit distribution unit 51 creates a pixel block by combining several pieces of pixel data, and determines the required number of bits required for each pixel block. Data of the required number of bits in each pixel block is output to the quantization unit 52 and the bit rate calculation unit 55.

The quantizing section 52 calculates the value of the scale factor of the tristimulus value in each pixel block, divides the value of the tristimulus value in each pixel by the scale factor, and quantizes the numerical value by the allocated number of bits. Become
Then, from the quantization unit 52, the control signal, the scale factor, the number of allocated bits, and the quantized value of the tristimulus value are output to the buffer memory 54, and the information of Y of the tristimulus value is output to the line memory 53. Is done.

The line memory 53 is a memory for storing data, and stores the Y data in the tristimulus values for one line. The buffer memory 54 is a memory for storing data, and is a memory for storing compressed data. The buffer memory 54 needs to be able to execute input and output with different clocks.

The bit rate calculator 55 is a circuit that calculates a transmission bit rate from data of a required number of bits, and further calculates a clock frequency required for data transfer from the number of signal lines to be transmitted. Information on the clock frequency calculated by the bit rate calculator 55 is output to the clock generator 56.

The clock generator 56 is a circuit for generating a clock from information on the clock frequency. The clock generated by the clock generator 56 is transmitted to the modulation data generator 57.

The modulation data generator 57 is a circuit for generating data to be transmitted to the source driver 47. The modulation data generator 57 reads data from the buffer memory 54 in synchronization with the clock generated by the clock generator 56 and outputs the data to the source driver 47.

The gate signal generating section 58 is a circuit for generating a control signal for controlling the gate driving means 4 based on the display data. The gate signal generator 58 outputs a control signal and a clock to the gate driving means 4.

As shown in FIG. 16, the source driving means 47 includes an inverse quantization section 59, a three-stimulus value inverse conversion section 60, a source buffer 61, and a source voltage generation section 62.

The inverse quantization section 41 includes a driving data generation section 46
Is a circuit that returns the data sent from the device to tristimulus values. The tristimulus value data and the control signal generated by the inverse quantization unit 41 are output to the tristimulus value inverse transform unit 60.

The tristimulus value inverse conversion unit 60 is a circuit for returning tristimulus values to information of each pixel. From the tristimulus value inverse conversion unit 60, information of each pixel and a control signal are output to the source buffer 61.

The source buffer 61 is a circuit for temporarily storing one line of data sent from the tristimulus value inverse converter 60. And this source buffer 61
Transmits data based on the control signal to the source voltage generator 6.
Output to 2.

The source voltage generator 62 is a circuit that generates a voltage applied to the source line of the liquid crystal display panel 5 for driving the liquid crystal.

The liquid crystal display device 1 of the present embodiment is configured as described above, so that the number of data transmission lines is reduced, unnecessary radiation is reduced by lowering the transmission frequency, and the frequency is changed. By diffusion of unnecessary radiation peak,
Unwanted radiation can be reduced. Hereinafter, the display operation of the present liquid crystal display device will be described more specifically.

The display operation in the liquid crystal display device 1 of the present embodiment is performed in the following sequence. First, image data is input to the liquid crystal display device 1. The image data is first input to the drive data generation unit 46.

In the drive data generator 46, the input image data is first input to the source signal generator 48.
The source signal generation unit 48 generates a source buffer 61 in the source driving unit 47 based on the input image data.
And a start pulse SSP indicating the start of scanning of one line of data to control the source voltage generator 62, and a latch pulse indicating the timing of switching the output voltage to the voltage value recorded in the source buffer 61 It is converted into an LS control signal and data of each pixel.

In the case of an 8-bit color liquid crystal display device, the data output from the source signal generator 48 is the SSP
(1 bit), LS (1 bit), R0 to R7 (red data, 8 bits), G0 to G7 (green data, 8 bits), and B0 to B7 (blue data, 8 bits), totaling 26 The drive data is composed of bits. The data thus converted is output to the tristimulus value converter 49.

The tristimulus value converter 49 calculates R,
From the G and B data, ie, the chromaticity data and luminance data of each pixel, the tristimulus values X, Y,
Calculate Z. Here, Y of the tristimulus values represents luminance. Then, the tristimulus value conversion unit 49 transmits the tristimulus values X, Y, and Z and the control signal to the visual model calculation unit 50. In the present embodiment, the tristimulus value converter 49
Are converted into X, Y, and Z, but are not limited thereto. For example, X, x, and
y, L ^* , a ^* , b ^*, etc. may be used.

The visual model calculation unit 50 calculates the required number of bits based on a human perception model. This calculation result is output to bit allocation section 51. Hereinafter, the calculation algorithm in the visual model calculation unit 50 will be described.

The human eye has a very sensitive characteristic with respect to the change in the luminance Y data due to the function of the brain.
Based on the characteristics of the human eye, the required number of bits is calculated by the following algorithm. 1) From the values of X, Y, and Z, a luminance difference that can be recognized by a human is obtained, and this value is set as Mask _h . 2) A luminance difference that can be displayed by the liquid crystal display device is determined from the values of X, Y, and Z, and this value is defined as Mask _m . 3) Mask _h and Mask _m are compared, and the larger one is set as Mask _lt . 4) Compare the Y values of adjacent pixels, and determine the difference
If there is more than _lt , the required number of bits is the number of digits up to which the difference can be expressed.

[0200] The bit distribution unit 51 determines the number of bits used for encoding each pixel. Here, the number of bits that can be transmitted in one line between the drive data generation unit 46 and the source driving unit 47 is referred to as a transmission allowable bit number. The bit distribution unit 51 first forms a pixel group by grouping continuous pixels. Then, bits are allocated to each pixel group based on the required number of bits. As a bit allocation procedure for each pixel group, the required number of bits is sequentially allocated to each pixel group, and the allocation is terminated when the number of transmission-permitted bits is exhausted.

Information on the number of bits allocated to each pixel group as described above is output to the quantization unit 52. The remainder of the number of bits allowed for transmission is output to the bit rate calculator 55.

[0202] The quantization unit 52 performs data quantization.
First, the maximum value of each of the X, Y, and Z data of each pixel group is obtained. The scale factor is calculated from the maximum value. That is, three scale factors of X, Y, and Z are set for each pixel group. Next, the X, Y, and Z values of each pixel are normalized by the scale factor of the pixel group to which the pixel belongs. Next, according to the number of bits allocated to each pixel group, bits are extracted from the higher order of the normalized data. This data will be referred to as mantissa XYZ data.

[0203] The scale factor, the number of allocated bits, the mantissa XYZ data, and the control signal are stored in the buffer memory 54. Further, mantissa XYZ data of the value of Y and data dequantized by the scale factor are stored in the line memory 53.

The line memory 53 stores the driving data
6 is stored. This data is used in calculating the visual model for the next line. The buffer memory 54 serves as a cache for temporarily storing data to be transmitted and synchronizing with the modulated clock.

The bit rate calculator 55 calculates the clock cycle based on the clock cycle when the number of bits is allowed to transmit and the remaining number of bits sent from the bit allocator 51. The calculation is obtained by the following formula: clock cycle = [clock cycle at the time of the number of allowable transmission bits] × [number of allowable transmission bits] / ([number of allowable transmission bits] − [number of remaining bits]).
This clock cycle is transmitted to the clock generator 56.

The clock generator 56 generates a clock in accordance with the clock cycle sent from the bit rate calculator 55. At this time, the clock is modulated to reduce EMI. However, the number of clocks per line is not reduced as a result of the modulation. Then, the clock generated by the clock generator 56 is output to the modulation data generator 57.

The modulation data generator 57 reads the compressed data stored in the buffer memory 54 using the clock generated by the clock generator 56. At this time, the write clock and the read clock of the buffer memory 54 are different. Therefore, the buffer memory 5
4 needs to adopt a configuration in which writing and reading can be performed by different clocks. Then, the modulation data generation unit 57
The clock generated by the clock generator 56 and the compressed data synchronized with the clock are output to the source driver 47.

The source driver 47 receives the compressed data sent from the drive data generator 46. First, the inverse quantization unit 59 returns the X, Y, and Z data of each pixel from the mantissa XYZ data of the compressed data, the scale factor, and the number of allocated bits. The X, Y, and Z data and the control signal are output to the tristimulus value inverse conversion unit 60.

In the tristimulus value inverse conversion unit 60, the X, Y, Z values of each pixel are returned to R, G, B gradation data. Then, the R, G, B gradation data is converted into voltage information applied to each source line of the liquid crystal display panel 5 and output to the source buffer 61 together with a control signal.

The source buffer 61 receives the start pulse S
After SP, information on the voltage applied to each source line is stored for each source line. Then, at the timing of the latch pulse LS input after the data for one line is accumulated, the stored data and the voltage applied to the source line are changed to the voltage value stored at that time. The signal is output to the source voltage generator 62.

[0211] The source voltage generator 62 generates a voltage to be supplied to each source line based on the information sent from the source buffer 61, and supplies it to the source line of the liquid crystal display panel 5. Further, it has a function of maintaining the potential until a control signal for changing the next voltage value is sent from the source buffer 61.

On the other hand, the gate signal generation section 58 in the drive data generation section 46 generates a control signal for driving the gate drive section 4 in synchronization with the switching in the source buffer 61, and outputs the control signal to the gate drive section 4. . The control signal is a signal that enables the gate drive unit 4 to drive the gate line of the line displayed by the output of the switched source line based on the synchronization signal of the image data.

The gate driving means 4 includes a driving data generation unit 4
A voltage is applied to the gate line of the liquid crystal display panel 5 based on the control signal sent from the control signal 6. by this,
The display of the first line is performed.

By the above processing, one line can be displayed, and by repeating this for all the horizontal lines of the screen, the entire screen can be displayed. When transmission is performed according to such a sequence, the amount of information of transmission data on the path from the driving data generation unit 26 to the source driving unit 27 can be reduced by deleting data that cannot be recognized by human senses. . Therefore, it is possible to reduce the frequency of the transmission path and the transmission signal line.

[0215]

As described above, in the display device according to the present invention, the source driving means for driving the source bus lines for supplying the source signals to the pixel portions arranged in a matrix, and the input image data And a drive data generation unit for supplying transmission data to the source drive unit, based on which, the drive data generation unit encodes the input image data for each predetermined data block by a predetermined algorithm. A data encoding unit for generating transmission data having a different data amount for each data block, and transmitting the transmission data for each data block according to the data amount of the data encoded by the data encoding unit. Transmission frequency adjusting means for adjusting the frequency, wherein the source driving means is transmitted from the driving data generating unit The transmission data is configured to includes a decoding means for decoding as the source signal.

As a result, the transmission frequency of the transmission data transmitted from the driving data generation unit to the source driving means is dispersed, and unnecessary radiation generated at a constant multiple of the transmission frequency is also dispersed. This has the effect that the value can be reduced.

Further, in the display device according to the present invention, the algorithm used in the encoding by the data encoding means is such that the data amount of the data after encoding is larger than the data amount of the data before encoding. It may be configured to include the case where

As a result, in addition to the effect of the above configuration, the dispersion of the transmission frequency can be increased.
There is an effect that the peak value of the unnecessary radiation can be efficiently reduced.

Further, in the display device according to the present invention, the algorithm used for encoding in the data encoding means, on average, is smaller than the data amount of the data before encoding.
A configuration may be adopted in which the data amount of the encoded data is smaller.

With this, in addition to the effect of the above configuration, it is possible to reduce the number of transmission paths for transmitting transmission data from the driving data generation unit to the source driving unit.
There is an effect that unnecessary radiation can be reduced.
Further, a reduction in the amount of data means a reduction in the transmission frequency, so that there is an effect that unnecessary radiation can be further reduced.

Further, according to the display device of the present invention, the source driving means for driving a source bus line for supplying a source signal to the pixel portions arranged in a matrix, A drive data generating unit for supplying transmission data to the source driving unit; and a plurality of transmission paths for transmitting transmission data from the driving data generation unit to the source driving unit. The data is distributed to the plurality of transmission paths, and the bit string of the transmission data allocated to each transmission path is
Dividing into a unit bit string having a predetermined number of bits, calculating a coding unit bit string by performing a predetermined logical operation on this unit bit string, comparing the original unit bit string with the coding unit bit string, A configuration including unit bit string selection means for selecting a smaller number as transmission data, and the source driving means including decoding means for decoding transmission data transmitted from the driving data generation unit as the source signal. It is.

[0222] This makes it possible to reduce the number of transition points of transmission data transmitted on each transmission path, thereby reducing the polarity inversion of the signal on the transmission path and reducing unnecessary radiation. Play.

Further, in the display device according to the present invention, the predetermined logical operation performed by the unit bit string selecting means is:
A configuration in which “0” and “1” are exclusive ORs with a bit string that is alternately repeated may be adopted.

Thus, in addition to the effect of the above configuration, the maximum value of the change point of the selected bit string is の of the number of bits of the unit bit string. That is, since the maximum value of the number of transition points of the transmission data transmitted in each transmission path can be reduced to half, there is an effect that unnecessary radiation can be further reduced.

[0225] In the display device according to the present invention, the driving data generation section may include a parallel bit string composed of bits input to the plurality of transmission paths at the same timing, and a bit sequence input at the next timing. The number of transition points with the parallel running bit sequence consisting of: a polarity-reversed parallel running bit sequence obtained by inverting the polarity of the parallel running bit sequence consisting of bits input to the plurality of transmission paths at the same timing; A configuration may further be provided which comprises a polarity inversion selecting means for comparing the number of change points with the parallel bit sequence of bits to be performed and selecting the one with the smaller number of change points as transmission data.

Thus, in addition to the effect of the above configuration, it is possible to reduce the change of each bit when the parallel bit stream is transmitted. At this time, when comparison is made with the polarity-inverted bit string whose polarity has been inverted as described above, the maximum value of the number of transition points of each bit of the transmission data can be reduced to half, so that unnecessary radiation Can be greatly reduced.

Further, in the display device according to the present invention, the drive data generation unit may include a parallel bit string composed of bits input to the plurality of transmission paths at the same timing, and a bit input at the next timing. And the number of transition points with the parallel running bit sequence consisting of: a parallel running bit sequence consisting of bits input to the plurality of transmission paths at the same timing; The configuration further includes an encoding selection unit that compares the number of transition points with a parallel bit string composed of bits input at the next timing and selects the one with the smaller number of transition points as transmission data. Is also good.

With this, in addition to the effect of the above configuration, it is possible to reduce the time change of each bit when the parallel running bit string is transmitted, so that the unnecessary radiation can be further reduced. To play.

Further, in the display device according to the present invention, the predetermined logical operation performed by the encoding selecting means is “0”.
And "1" may be an exclusive OR of a bit string that is alternately repeated.

With this, in addition to the effect of the above configuration, the maximum value of the number of change points of each bit when the parallel bit stream is transmitted can be reduced to half.
There is an effect that unnecessary radiation can be further reduced.

[0231] The display device according to the present invention includes a display panel including pixel portions arranged in a matrix, source driving means for driving a source bus line for supplying a source signal to the pixel portion, and an input device. A drive data generation unit that supplies transmission data to the source drive unit based on the input image data. The drive data generation unit can represent each pixel data in the input image data on the display panel. In this configuration, data conversion means for converting the color to the closest color is provided.

As a result, the amount of information of transmission data transmitted from the driving data generation unit to the source driving unit can be reduced, so that the transmission frequency can be reduced and the required transmission path can be reduced. The number can be reduced. Therefore, there is an effect that unnecessary radiation can be reduced.

The display device according to the present invention comprises a source driving means for driving a source bus line for supplying a source signal to a pixel portion arranged in a matrix, and A drive data generation unit that supplies transmission data to the source drive unit, wherein the drive data generation unit converts each pixel data in the input image data into a pixel value that allows a human to recognize the difference on the display screen. This is a configuration including visual model conversion means for conversion.

As a result, the amount of information of transmission data transmitted from the driving data generation unit to the source driving means can be reduced, so that the transmission frequency can be reduced and the required transmission path can be reduced. The number can be reduced. Therefore, there is an effect that unnecessary radiation can be reduced.

Further, in the display device according to the present invention, the visual model conversion means calculates a luminance value of each pixel data in the input image data, finds a difference between luminance values of adjacent pixels, and obtains the luminance value. The amount of information required for the pixel data is set by comparing the difference between the values and the difference between the luminance values at which a human can recognize the difference on the display screen. It may be configured to convert to a value.

Thus, in addition to the effect of the above configuration, if the pixel data is converted by taking into account the difference in luminance value between adjacent pixels, the amount of information can be reduced in a range that cannot be recognized by humans. This has the effect that it can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a drive data generation unit included in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of the liquid crystal display device.

FIG. 3 is a block diagram illustrating a schematic configuration of a source driving unit included in the liquid crystal display device.

FIG. 4 is a diagram showing an outline of drive data for one line.

FIG. 5 is a block diagram illustrating a schematic configuration of a liquid crystal display device according to another embodiment of the present invention.

FIG. 6 is a block diagram illustrating a schematic configuration of a drive data generation unit included in the liquid crystal display device.

FIG. 7 is a block diagram showing a schematic configuration of source driving means provided in the liquid crystal display device.

FIG. 8 is a block diagram showing a schematic configuration of a liquid crystal display device according to still another embodiment of the present invention.

FIG. 9 is a block diagram illustrating a schematic configuration of a drive data generation unit included in the liquid crystal display device.

FIG. 10 is a block diagram showing a schematic configuration of source driving means provided in the liquid crystal display device.

FIG. 11 is a block diagram illustrating a schematic configuration of a liquid crystal display device according to still another embodiment of the present invention.

FIG. 12 is a block diagram illustrating a schematic configuration of a drive data generation unit included in the liquid crystal display device.

FIG. 13 is a block diagram showing a schematic configuration of source driving means provided in the liquid crystal display device.

FIG. 14 is a block diagram showing a schematic configuration of a liquid crystal display device according to still another embodiment of the present invention.

FIG. 15 is a block diagram illustrating a schematic configuration of a drive data generation unit included in the liquid crystal display device.

FIG. 16 is a block diagram showing a schematic configuration of source driving means provided in the liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2.16.26.36.46 Drive data generation part 3.17.27.37.47 Source driving means 4. Gate driving means 5. Liquid crystal display panel 6.18.28.38.48 Source signal generation part 7 Data compression unit (Data encoding unit) 8.54 Buffer memory 9.55 Bit rate operation unit (Transmission frequency adjustment unit) 10.56 Clock generation unit 11.57 Modulation data generation unit 12.21.31.40.58 Gate signal generation unit 13 Data decompression unit (decoding means) 14.24.34.42.61 Source buffer 15.25.35.43.62 Source voltage generation unit 19 EXOR conversion unit 20 Polarity conversion unit (polarity inversion selection unit) 22) Polarity decoding unit 23 EXOR decoding unit (unit bit string selection unit) 29 EXOR1 conversion unit (unit bit string selection unit) 30 EXOR2 conversion unit (encoding selection unit) 32 EXOR2 decoding unit 33 EXOR1 decoding unit 39 LUT encoding unit (data conversion unit) 41 LUT decoding unit 49 3 stimulus value conversion unit 50 visual model calculation unit (visual model conversion unit) 51 bits Distribution unit 52 Quantization unit 53 Line memory 59 Inverse quantization unit 60 3 Stimulus value inverse transformation unit

Claims (11)

[Claims] 1. A source driving means for driving a source bus line for supplying a source signal to a pixel portion arranged in a matrix, and transmission data is supplied to the source driving means based on input image data. A drive data generation unit that encodes the input image data for each predetermined data block by a predetermined algorithm, and transmits the transmission data having a different data amount for each data block. And a transmission frequency adjusting unit that adjusts a transmission frequency of the transmission data for each data block according to a data amount of data encoded by the data encoding unit. Source driving means decodes the transmission data transmitted from the driving data generation unit as the source signal That it comprises a decoding means for display device characterized. 2. An algorithm used for encoding in the data encoding means includes a case where the data amount of encoded data is larger than the data amount of data before encoding. The display device according to claim 1, wherein: 3. An algorithm used in encoding by said data encoding means, on average, the data amount of data after encoding is smaller than the data amount of data before encoding. 3. The display device according to claim 1, wherein 4. A source driving unit for driving a source bus line for supplying a source signal to pixel units arranged in a matrix, and supplying transmission data to the source driving unit based on input image data. And a plurality of transmission paths for transmitting transmission data from the drive data generation section to the source driving means, wherein the drive data generation section converts the input image data into the plurality of transmission paths. In addition, the bit string of the transmission data allocated to each transmission path is divided into a unit bit string having a predetermined number of bits, and a coding unit bit string obtained by performing a predetermined logical operation on the unit bit string is calculated. Comparing the original unit bit string and the coding unit bit string, and comprising a unit bit string selecting means for selecting one having a smaller number of change points as transmission data, Display source drive means, characterized in that the transmission data transmitted from the drive data generating unit and a decoding means for decoding as the source signal. 5. A predetermined logical operation performed by said unit bit string selecting means is an exclusive OR of a bit string in which "0" and "1" are alternately repeated. The display device according to the above. 6. A change in a parallel running bit sequence composed of bits input at the same timing to the plurality of transmission paths and a parallel running bit sequence composed of bits input at the next timing. The number of points,
A change point between a polarity-reversed parallel running bit sequence obtained by inverting the polarity of a parallel running bit sequence consisting of bits input at the same timing with respect to the plurality of transmission paths and a parallel running bit sequence consisting of bits input at the next timing. 5. The apparatus according to claim 4, further comprising polarity inversion selecting means for comparing the number of change points with the number of change points and selecting the smaller number as transmission data.
Or the display device according to 5. 7. A method according to claim 1, wherein said drive data generating section changes a parallel running bit sequence consisting of bits input at the same timing to said plurality of transmission paths and a parallel running bit sequence consisting of bits input at the next timing. The number of points,
An encoded parallel running bit sequence obtained by performing a predetermined logical operation on a parallel running bit sequence consisting of bits input at the same timing to the plurality of transmission paths, and a parallel running sequence consisting of bits input at the next timing 7. The coding method according to claim 4, further comprising an encoding selection unit that compares the number of transition points with the bit string and selects the one having a smaller number of transition points as transmission data. Display device. 8. A method according to claim 7, wherein said predetermined logical operation performed by said encoding selecting means is an exclusive OR of a bit string in which "0" and "1" are alternately repeated. The display device according to the above. 9. A display panel comprising pixel units arranged in a matrix, source driving means for driving a source bus line for supplying a source signal to the pixel units, and: A drive data generation unit that supplies transmission data to the source drive unit, wherein the drive data generation unit converts each pixel data in the input image data into a color closest to a color that can be expressed on the display panel. A display device comprising data conversion means for converting the data into a data. 10. A source driving unit for driving a source bus line for supplying a source signal to pixel units arranged in a matrix, and supplying transmission data to the source driving unit based on input image data. A driving data generation unit that converts each pixel data in the input image data into a pixel value that allows a human to recognize the difference on a display screen. A display device, comprising: 11. The visual model conversion means calculates a luminance value of each pixel data in input image data, finds a difference in luminance value between adjacent pixels, and calculates a difference between the luminance value and
The amount of information required for the pixel data is set by comparing the luminance value difference on the display screen with which a human can recognize the difference, and the pixel data is converted to a pixel value that becomes the information amount. The display device according to claim 10, wherein: