JP2005049885A - Image processor and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor and an image processing method that perform image processing not inferior to a normal raster image even when memory capacity is reduced, and decrease transmission capacity while suppressing deterioration in image quality in data transmission of a raster image. <P>SOLUTION: The image processor decreases the number of bit planes of a 1st raster image as an original image and then increases the number of bit planes of the bit-plane number decreased image to below the number of bit planes of the original image to generate a 2nd raster image. This apparatus has a 1st image processing means of performing multi-valued dither processing with a two-dimensional dither matrix when the number of bit planes of the 1st raster image is decreased, a 2nd image processing means of adding bits based upon the two-dimensional dither matrix that the 1st image processing means used when the number of bit planes of the bit-plane number decreased raster image is increased, and a selecting means of outputting the 1st or 2nd raster image. The selecting means selects the raster image when the original image is a still image and the 1st raster image when the original image is a moving image. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus and an image processing method, and more particularly to an image processing apparatus and image for improving image quality in image processing of a display having a memory for storing raster images and improving transmission efficiency of raster images from a computer to a display. It relates to the processing method.

  Currently, a method of transmitting a raster image for each frame frequency is used as an image transmission method from a computer to a display. This method is wasteful when the amount of data transmission is large and still images are displayed.

  As a method for reducing the data transmission amount, a method of transmitting an image after compressing the image into a file format such as JPEG or GIF is conceivable. However, in order to perform compression and decompression processing for each frame, an arithmetic processing unit that performs high-speed operation is necessary, which leads to an increase in cost.

  On the other hand, as a method to reduce the waste of transmission in still image display, there is a method of installing a frame memory that stores the raster image built in the display side and interrupting data transmission when displaying a still image. It is done. This is particularly effective in portable information devices and the like because it can simultaneously reduce power consumption.

  For displays mounted on portable information devices, it is particularly important to reduce power consumption and chip area. In order to satisfy this requirement, in still image display, it is desirable that the image stored in the memory is displayed and the capacity of the memory unit that occupies a large chip area is small. Thus, by accumulating images in the memory, the power consumption during data transmission is reduced, and by reducing the memory capacity, the chip area is reduced.

  To reduce the memory capacity, a method of compressing image data is conceivable. However, an image compression method such as JPEG format or GIF format requires an image processing unit for decompression, and the effect of reducing chip area and power consumption is diminished.

  As another method, it is conceivable to reduce the number of bit planes of the raster image. Here, the number of bit planes is the number of bits n of data representing the gradation in a digital image quantized with the power of 2 n, and indicates the number of bits n. As a method for reducing the number of bit planes, there are a multi-value dither method, a fixed threshold method, and the like, and details thereof are disclosed in Non-Patent Document 1. Unlike the image compression methods such as the JPEG format and the GIF format, these multi-value dither method and fixed threshold method do not need to expand a compressed image.

  FIG. 38 is a block diagram showing a schematic configuration of a conventional image processing apparatus. As a bit plane compression example of a raster image using the conventional multi-value dither method with reference to FIG. 38, a configuration including a display image display unit that transmits a 6-bit raster image of each RGB color from a computer and performs 6-bit display for each color Will be described.

  First, the lower 2 bits of the 6-bit raster image 1 of each color are sent to the comparator 12. The threshold generation unit 11 generates a dither matrix based on the systematic dither, and outputs a 2-bit value uniquely determined from the input image pixel (XY coordinate value) to the comparator 12.

  The comparator 12 compares the lower 2 bits sent from the raster image 1 with the 2-bit value sent from the threshold value generator 11, and when the value sent from the threshold value generator 11 is larger, “ 1 ”is output to the selector 13 in other cases.

  Based on the output value from the comparator 12, the selector 13 outputs to the memory 2 the upper 4 bits of the raster image 1 as they are or the value obtained by subtracting 1 from them. Each color 4-bit image stored in the memory 2 adds the value of the upper 2 bits of the 4 bits as the lower bits of the input 4-bit value in the bit adding unit 14 and the image display unit 3 as a 6-bit image. Output to.

  With such a configuration, the number of bit planes is reduced by the multi-value dither method, and a 6-bit image of each color is displayed in a pseudo manner.

  On the other hand, in Patent Document 1, a digitized input signal is level-compressed and transmitted, and a maximum value is detected in a digital signal for level expansion of the transmitted compressed signal, and then a dither value is added according to the maximum value. After that, a digital signal processing apparatus (hereinafter, referred to as a first prior art) including circuits for compressing a level and subtracting a dither value after level expansion is disclosed.

With such a configuration, an output with little error is obtained in a digitized audio signal which is a one-dimensional signal.
Japanese Patent Publication No. 2-8493 The Institute of Image Electronics Engineers, “New Image Image Handbook”, First Edition, Corona, March 31, 1993, p. 41-51

However, the conventional multi-value dither method and fixed threshold method have the problem that by reducing the number of bit planes, false contours, false colors are generated, graininess, etc., and the image quality deteriorates. It was.
As a display form on the display, there is a technique called superimpose. This is a technique for displaying different screens such as “characters” on a certain display screen. In this case, since a plurality of screens (for example, images and characters) must be prepared as the input image, the data capacity of the input image increases, and the input image is stored in the memory or the bus width is limited. It becomes difficult to transmit via a certain transmission line.
Furthermore, on a display having a small maximum display screen resolution such as a portable terminal, it is necessary to scroll the image when displaying a large image such as a map. Although this scroll display is a simple operation at first glance, there is a problem in that the amount of rewriting of the display memory increases, and the power consumption increases accordingly.

  As shown in FIG. 39A, when an image is displayed on a display device such as a display, an image signal is input to each pixel along a line in the main scanning direction, and the image signal is input in the sub scanning direction. By repeating a plurality of lines, an image signal is input to all pixels.

Here, consider a case where the first prior art is applied to image display. In this example, the dither cycle is 4 bits.
As shown in (b), when the number of pixels in the main scanning direction of the display device is 4n + 1, the periodicity appears in the dither in both the main scanning direction and the sub-scanning direction. small. This is the same when the number of pixels in the main scanning direction of the display device is 4n + 2 or 4n + 3. That is, when the number of pixels in the main scanning direction of the display device does not include the dither period as a factor, image quality deterioration due to image compression / expansion is small.
However, when the number of pixels in the main scanning direction of the display device is 4n, in other words, when the number of pixels in the main scanning direction of the display device includes the dither period as a factor, as shown in FIG. Although dither periodicity appears in the image, dither periodicity is not observed in the sub-scanning direction, and image quality deterioration due to image compression / decompression increases.

In the case of the dither processing for the raster image, the smaller the dither period, the higher the frequency of the fine noise, so the degradation of the image quality can be reduced. However, in general, the number of pixels in the main scanning direction of the display device is a number (480, 720, 840, etc.) including “2” to “6” as factors, so the first conventional technique is used for image display. When applied, the state shown in FIG. 39C is obtained, and the image quality deteriorates as the image is compressed / expanded.
If the dither cycle is increased so as not to be a factor in the number of pixels in the main scanning direction of the display device, the high-frequency minute noise that is the original purpose of the dither processing cannot be obtained. As a result, the image quality deteriorates.

Further, when the first prior art is applied as it is, in order to specify which digit of the digital signal consisting of a plurality of bits the dither value is added, a maximum value detection circuit is provided on the compression side, A signal indicating what number the most used digit bit is must be transmitted to the receiving side together with the digital signal at any time. Further, when storing the compressed digital signal in a memory or the like, it is necessary to store a signal indicating the number of the most used digit bits together with the digital signal.
However, a configuration for performing such processing is not preferable as a configuration applied to an image processing apparatus such as a display because the circuit becomes complicated and power consumption and a chip area increase.

Further, the first prior art does not suggest any processing method with the maximum value and the minimum value of the digital signal. For this reason, an image processing apparatus such as a display that frequently displays “white” as a maximum value (for example, character output or display of geometric figures) or “black” as a minimum value is frequently used. Will result in deterioration. This is because graininess tends to be seen in “black” and “white” display.
As described above, when the first prior art is applied to image processing as it is, the image quality is deteriorated due to the compression / decompression of the image.

  Therefore, when the first conventional technique is applied to image display, a dither matrix configuration suitable for a raster image that is a two-dimensional signal must be applied. Furthermore, since the gradation value of a pixel is biased depending on the type (character display or natural image display), it is desirable to perform image processing more suitable for a raster image.

  Further, in the image display of the display device, not all images are compressed. For example, in the case of moving image display, an image is subjected to compression / expansion processing for each frame, which increases power consumption and calculation amount. Therefore, it is not desirable to compress / expand an image.

  The present invention has been made to solve the above-described problems, and performs image processing comparable to a normal raster image even if the memory capacity is reduced, and transmits not only the memory capacity but also the data transmission of the raster image. An object of the present invention is to provide an image processing apparatus and an image processing method capable of reducing transmission capacity while suppressing image quality deterioration. It is another object of the present invention to provide an excellent image processing apparatus and image processing method capable of reducing the power consumption and the amount of calculation by making efficient use of image transmission and memory using such image processing.

In order to achieve the above object, the present invention selects, as a first aspect, whether to output an original raster image as it is, to decrease and increase the number of bit planes, or to output a compressed / expanded image. An image processing apparatus that can be used is provided.
A first aspect of the present invention is an image processing apparatus shown in any of the following 1-1 to 1-3.
1-1: After reducing the number of bit planes of the first raster image that is the original image, the number of bit planes of the raster image with the reduced number of bit planes is increased to be equal to or less than the number of bit planes of the original image. An image processing apparatus for generating a raster image of the first image processing means, wherein when reducing the number of bit planes of the first raster image, a first image processing means for performing multi-value dither processing using a two-dimensional dither matrix; A second image processing means for performing bit addition processing based on the two-dimensional dither matrix used by the first image processing means when increasing the number of bit planes of the raster image whose number of planes has decreased; An image processing apparatus comprising: selection means for selecting and outputting either an image or a second raster image.
1-2: After reducing the number of bit planes of the first raster image that is the original image, the number of bit planes of the raster image with the reduced number of bit planes is increased to be equal to or less than the number of bit planes of the original image. An image processing apparatus for generating a raster image of the first image processing means, wherein when reducing the number of bit planes of the first raster image, a first image processing means for performing multi-value dither processing using a two-dimensional dither matrix; When increasing the number of bit planes of a raster image whose number of planes has decreased, bit addition processing is performed based on the two-dimensional dither matrix used by the first image processing means, and the signal value of the original image and the number of bit planes are calculated. A second image processing means for adding an offset value so as to minimize a difference between the average value of all the dither values of the increased raster image, and the first raster image and the second raster. The image processing apparatus characterized by having a selection means for selecting and outputting one of the image.
1-3: An image processing apparatus that compresses and expands data of a first raster image that is an original image to generate a second raster image, and first image processing that compresses the first raster image Means, second image processing means for generating a second raster image by decompressing the data compressed by the first image compression means, and selecting either the first raster image or the second raster image And an output selecting unit.
In configurations 1-1 and 1-2 of the first aspect of the present invention, the first and second raster images are RGB color images in which each color of the RGB signal has the same number of bit planes, and The amount of reduction in the number of planes is preferably the largest for the B signal and the smallest for the G signal.
In any of the configurations of the first aspect of the present invention, the storage unit stores the raster image data obtained by the first image processing unit, and the second image processing unit stores the storage unit. It is preferable to read the compressed raster image data stored in the image and perform image processing. Further, it is preferable that the first and second image processing means perform image processing so that the maximum value and the minimum value of the element components of the raster image do not change before and after the image processing. The second image processing unit is preferably formed on the same substrate as the driver circuit of the display device. The first image processing means is preferably formed on the same substrate as the driver circuit of the display device.

According to the first aspect of the present invention, for example, when the original image is a moving image, the original image is output as it is, and when the original image is a still image, the number of bit planes is decreased and increased, or compression / By outputting the expanded image, it is possible to display the image without using a storage unit (for example, a memory) when displaying a moving image.
Therefore, when the number of bit planes is reduced and increased, or when image compression / decompression is necessary, and when it is not necessary to perform these processes (such as when displaying moving images), the operation of the storage means is stopped. It is possible to reduce power consumption.
Note that in the case where the image processing device of this embodiment is applied to a display device in which a driver circuit is formed over a substrate (for example, a glass substrate), the image processing device can be formed over the substrate in the same process. Therefore, if the image processing apparatus of this aspect is applied to a display device, a reduction in area due to memory saving and low power consumption can be realized.

In order to achieve the above object, according to the second aspect of the present invention, whether the raster image that is the original image is output as it is, whether the number of bit planes is decreased and increased, or a compressed / expanded image is output. The image processing method which can select is provided.
A second aspect of the present invention is an image processing method shown in any one of the following 2-1 to 2-3.
2-1: After reducing the number of bit planes of the first raster image that is the original image, the number of bit planes of the raster image is increased to be less than or equal to the number of bit planes of the original image to generate a second raster image. An image processing method, wherein a selection step for selecting which of the first and second raster images is to be output;
A first image processing step for performing multi-value dither processing using a two-dimensional dither matrix when reducing the number of bit planes of the first raster image, and bits of the raster image processed in the first image processing step A second image processing step for performing bit addition processing based on the two-dimensional dither matrix used in the first image processing step when increasing the number of planes, and among the first raster image and the second raster image An image processing method comprising: an output step for outputting one selected in the selection step.
2-2: After reducing the number of bit planes of the first raster image that is the original image, the number of bit planes of the raster image with the reduced number of bit planes is increased to be less than or equal to the number of bit planes of the original image. In the image processing method for generating the raster image, a selection step for selecting which of the first and second raster images is to be output, and when the number of bit planes of the first raster image is reduced, A first image processing step that performs multi-value dither processing using a dimensional dither matrix, and a step in the first image processing step when increasing the number of bit planes of the raster image processed in the first image processing step. Bit addition processing based on the two-dimensional dither matrix, the signal value of the original image, and the average value of all the dither values of the raster image with the number of bit planes increased A second image processing step for adding an offset value so as to minimize the difference between the first raster image and an output step for outputting one of the first raster image and the second raster image selected in the selection step. An image processing method.
2-3: An image processing method for generating a second raster image by compressing data of a first raster image, which is an original image, and then decompressing the compressed raster image data. A selection step for selecting which of the two raster images to output, a first image processing step for compressing the first raster image, and decompressing the data compressed in the first image processing step, An image processing method comprising: a second image processing step for generating two raster images; and an output step for outputting one of the first and second raster images selected in the selection step.
In configurations 2-1 and 2-2 of the second aspect of the present invention, the first raster image is an RGB color image in which each color of the RGB signal has the same number of bit planes, and the number of bit planes is the same. The amount of decrease is preferably the largest for the B signal and the smallest for the G signal.
In any of the image processing methods according to the second aspect of the present invention, after the first image processing step, the raster image data obtained by the first image processing step is stored in the storage unit. The second image processing step preferably includes reading the raster image data stored in the storage means and performing image processing. In addition to this, the storage means is preceded by the storage means. If the storage capacity is smaller than the raster image data obtained in the first image processing step, the raster image data obtained in the first image processing step is compressed below the storage capacity of the storage means. It is more preferable to have further. In the selection step, it is preferable that the second raster image is selected when the original image is a still image, and the first raster image is selected when the original image is a moving image. Further, after the selection step, when the first raster image is selected in the selection step, there is further provided a processing stop step for stopping the image processing by the first image processing step and the second image processing step. It is preferable. In the first and second image processing steps, it is preferable to perform image processing so that the maximum value and the minimum value of the element components of the first raster image and the second raster image match.

According to the second aspect of the present invention, for example, when the original image is a moving image, it is output as it is, and when it is a still image, the number of bit planes is decreased and increased, or compression / By outputting the expanded image, it is possible to display the image without using a storage unit (for example, a memory) when displaying a moving image.
Therefore, the apparatus that executes the image processing method of this aspect performs only when it is necessary to reduce and increase the number of bit planes and compress / decompress the image, and when these processes do not need to be performed (such as when displaying a moving image). It is possible to reduce the power consumption by stopping the operation of the storage means.

  According to the present invention, compression / decompression of a bitmap image to be sent to a display device can be performed with a small number of logics, and the memory capacity and transmission capacity can be reduced.

  In addition, according to the present invention, since the error with the original image is smaller than that of the multi-value dither method, the bit added image can suppress graininess and false color that appear when the error is large. A high-quality display can be obtained.

  Further, according to the present invention, for example, a compressed image can be selected when a still image is displayed, and can be displayed as it is without performing image processing when a moving image is displayed. Therefore, since it is possible to display without moving through the storage means (for example, a memory) at the time of displaying a moving image, it is possible to reduce the power consumption by stopping the operation of the storage means.

According to the present invention, in superimpose display, a natural image is compressed / expanded for 1 bit, and the obtained 1-bit capacity is applied to character information, thereby increasing the memory capacity. It is possible to perform the superimpose process without incurring the problem.
Even when an image larger than the maximum resolution of a display device such as a map is displayed, the image can be stored with a small memory capacity by the compression / decompression processing of the number of bit planes, and the image is re-acquired from the outside. Scroll display on the display device without any problem. Thereby, the power consumption accompanying image display can be reduced.

  In addition, according to the present invention, it is possible to obtain an image transmission apparatus and an image processing method that improve transmission capacity efficiency. For example, if you want to transmit raster image data of 6 bits for each color of RGB (18 bits in total) using a transmission path with a bus width of only 16 bits, the data is parallelized by applying bit plane compression to the raster image. It becomes possible to transmit.

Further, according to the present invention, it is possible to obtain an image receiving apparatus that achieves efficient transmission capacity in a transmission path for receiving an image.
In other words, it is possible to reduce the number of transmission paths for receiving images and increase the transmission efficiency by receiving an image in which the number of bit planes is reduced from the original image. It becomes. Further, by increasing the number of bit planes of the received image, it is possible to obtain an image that is comparable to the image quality compared to the original image.

  Further, according to the present invention, in a display device in which a drive circuit is formed on a substrate (for example, a glass substrate), the image processing device can be formed on the substrate using the same process. Therefore, when the present invention is applied to a display device, a reduction in area due to memory saving and low power consumption can be realized.

  The principle of the present invention is that a noise addition process called a dither process is performed to reduce the number of bit planes, and the number of bit planes is increased by a process opposite to the noise addition process. This minimizes the error component caused by the above. By doing so, the graininess can be reduced and the false color can be suppressed.

For example, consider a case where a 6-bit signal is converted into a 4-bit signal by multi-level dither processing and the 4-bit signal is expanded into a 6-bit signal. Here, if the dither matrix in the multi-value dither processing is based on systematic dither, 6-4 = 2-bit dither, so that any of dither components 00, 01, 10, and 11 in binary number is the input signal. To be added. When the inputted 6-bit signal is X and the dither component is D, the multi-value dither processing can be expressed by the following equation.
Y = int ((X−D) / 4)

  Here, int (X) represents an integer component of X. Dividing by 4 corresponds to conversion from 6 bits to 4 bits. For example, if the input signal is 37 (binary number 100101), the multi-value dither processing will use 9 (1001) if the dither component is 00, 9 (1001) if 01, and 8 (1000 if 10). ), 11 is converted to 8 (1000).

Next, the 4-bit signal is expanded to the 6-bit signal. The conversion formula at that time is shown below.
Z = 4 × Y + D + 2

  Here, when the constant of 2 is removed, it can be seen that Y = (Z−D) / 4, which is the reverse of the multi-value dither process. Based on the above conversion formula, when the signal having the above input signal of 37 (binary number 100101) is converted, the dither component is 38 (100110) when it is 00, 39 (100111) when it is 01, and 36 when it is 10. In the case of (100100) and 11, 37 (100101). The constant 2 in the conversion formula is an offset value added so that the average value of the converted signal takes the closest value to the input signal.

  When this conversion result is compared with the conventional 6-bit conversion of multi-value dither, according to the conventional conversion, the upper 2 bits of the 4 bits are added as the lower 2 bits. 100110) and 01 are converted into 38 (100110), 10 is converted into 34 (100010), 11 is converted into 34 (100010), and so on.

  As is apparent from this, according to the conversion processing of the present invention, it is understood that the overall value is close to the input signal. This indicates that the present invention can reduce graininess and suppress false colors.

  Here, a raster image converted from a 6-bit signal to a 4-bit signal is expanded to 6 bits. However, the present invention is not limited to this, and can be expanded to 5 bits. In this case, arithmetic processing is performed using the upper bits of the dither component. Specifically, the calculation of Z = 2 × Y + int (D / 2) +1 is performed. In such a configuration, it is possible to reduce graininess and false color even for a raster image expanded to 5 bits.

Here, as a process by multi-value dithering, here, the dither value is subtracted and then quantized, and then the dither value is added. By adding the dither value, the error near “white” which is the maximum gradation is minimized. This is because, as shown in FIG. 6 later, as a result of adding the dither value, all outputs of gradations larger than the gradation displaying “white” (gradation value 63 in FIG. 6) display “white”. Since it is rounded to the gradation, the error near “white” is the smallest among all gradations. With such a configuration, it is possible to minimize the error of “white” display, which is the maximum gradation, eliminate the graininess peculiar to dithering, and suppress gradation collapse near the “white” display.
For geometrical figures such as letters and maps, all signal components have a maximum gradation of “white”, and one of the signal components has a maximum gradation of “red”, “blue”, “green”, “yellow” Etc. are often used. For this reason, the present invention improves the display quality of such an image. This is a novel effect / action unique to the present invention that cannot be obtained by the first prior art.

  The present invention can improve the image quality by subjecting each pixel to a very simple process similar to multi-level dither.

As a signal configuration of the raster image in the present invention, in addition to the RGB signal described above, a signal composed of a luminance signal such as YCbCr and a chromaticity signal, a luminance signal such as an HSV or LCH signal, a saturation signal, and a hue signal are configured. Various signals can be applied, such as the generated signal.
Although multi-value dither processing is shown here as an example of image processing, the present invention is not limited to this, and any image processing that can obtain the above-described action may be used. In particular, an image processing method that performs reverse image processing when the number of bit planes decreases and increases is effective.

  Hereinafter, an image processing apparatus, an image transmission apparatus, and an image processing method according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 to 37 show preferred embodiments of an image processing apparatus, an image transmission apparatus, and an image processing method according to the present invention.

<First Embodiment>
FIG. 1 is a flowchart showing a processing flow of an image processing method according to the first embodiment of the present invention.

The image processing method according to this embodiment will be described. When a raster image is input to the image processing apparatus (step S1), a process for reducing the number of bit planes is performed on the input raster image (step S2). The raster image with the reduced number of bit planes is accumulated by being input to the memory (step S3). Thereafter, the raster image stored in the memory is read, and a process for increasing the number of bit planes is performed on the raster image (step S4).
At this time, it is desirable that the process of reducing the number of bit planes and the process of increasing the number of bit planes can be performed with a small number of logics. Furthermore, it is desirable that the number of logics for image processing is sufficiently smaller than the number of memory logics (such as the number of transistors and cells) that can be reduced by this processing. Usually, since the number of required logics in the process for reducing and increasing the number of bit planes is small, the number of bit planes can be preferably reduced and increased. For example, as a process for reducing the number of bit planes, there is "bit dropping", so-called "predetermined bit truncation". In this case, it is not necessary to perform arithmetic processing.

  With the above image processing method, it is possible to reduce the memory capacity in the image display processing. Further, since the compression ratio ((data volume before compression−data capacity after compression) / data capacity before compression) is constant in the decrease / increase of the number of bit planes, the image data of the original image is compressed and stored in the memory. It is easy to execute various image processing in an image processing apparatus (display system) that decompresses and displays the stored image data.

In the present embodiment, the case where the process of storing the image data of the raster image in the memory during the process of reducing and increasing the number of bit planes has been described as an example. However, the present invention is not limited to this. Instead of the process of storing the image data of the raster image in the memory, the process of transmitting the image data of the raster image via a transmission path having a predetermined bus width may be performed.
For example, the transmission path between the functional unit that performs the bit plane number decreasing process and the functional unit that performs the bit plane number increasing process does not have a sufficient bus width to transmit the raster image in the state of the original image. Think about the case. In this case, by reducing the number of bit planes, the number of bit planes of the raster image is reduced to the number of transmittable bit planes, and the raster image with the reduced number of bit planes is transmitted. After that, by increasing the number of bit planes of the raster image by the bit plane number increasing process and then outputting to the image display unit or the like, the raster image can be displayed on the image display unit or the like.
As described above, if the image processing method performs processing that cannot be performed on a raster image when the number of bit planes is in the state of the original image between the bit plane number decreasing process and the bit plane number increasing process, the same as above. The effect is obtained.

  In addition, although the reduction method and the increase method of the number of bit planes are described by showing some examples in other embodiments, dither processing is performed as a method for decreasing the number of bit planes, and reduction processing is performed as a method for increasing the number of bit planes. It is preferable to perform the reverse processing because the image compression / decompression can be performed with little deterioration in image quality.

<Second Embodiment>
FIG. 2 is a block diagram showing a schematic configuration of an image processing apparatus according to the second embodiment of the present invention. In FIG. 2, after the raster image 1 of 6 bits for each color of RGB sent from the computer is processed in the first stage 4 of the image processing unit, the raster image of 4 bits for each color is stored in the memory 2, and the stored 4 bit raster for each color. The image is converted into 6 bits for each color in the rear stage 5 of the image processing unit and output to the image display unit 3 capable of displaying 6 bits. Although FIG. 2 shows a block configuration for one color of RGB, the same configuration is also provided in parallel for the other two colors.

  The front stage 4 of the image processing unit includes a threshold value generation unit 11A, a comparator 12, a selector 13, and a subtracter. Of the 6-bit gradation data of the input raster image 1, the lower 2 bits are sent to the comparator 12, and the comparator 12 compares it with the 2-bit signal output from the threshold value generator 11A.

FIG. 3 is a plan view showing an output signal generation method of the threshold value generation unit.
Here, a matrix of organized dither is used as the threshold value. The threshold generation unit 11A generates an output signal based on the xy coordinate value (x, y) of the input pixel. In FIG. 3, [xmod 2] indicates a remainder obtained by dividing the X coordinate value (x) of the pixel by 2, and [ymod 2] indicates a remainder obtained by dividing the Y coordinate value (y) of the pixel by 2. An output value is generated from the results of [xmod 2] and [ymod 2].

  The comparator 12 outputs 1 when A <B, where A is the lower 2-bit value of the 6-bit gradation data of the input raster image 1 and B is the output value of the threshold value generator 11a. In other cases, 0 is output to the selector 13 as a SEL signal. This SEL signal becomes the select signal of the selector 13.

  The selector 13 receives the value of the upper 4 bits of the 6-bit gradation data of the input raster image 1 and the value obtained by subtracting 1 from the subtractor, and the SEL signal output from the comparator 12 is 0. If the SEL signal is 1, the value obtained by subtracting 1 from the subtractor is output, and the 4-bit output signal of the first stage 4 of the image processing unit is obtained.

FIG. 4 is a schematic diagram showing the processing in the former stage of the image processing unit.
Here, in each pixel (image position) on the horizontal axis, a process of converting the 6-bit input gradation indicated by the left vertical axis into the 4-bit output gradation indicated by the right vertical axis is performed. For example, “♦” at the leftmost pixel position indicates that the input gradation is “011110”. Since this value is between the threshold values “011111” and “011011”, it is thinned between horizontal lines drawn between them. The output gradation is indicated by “■”, and the output gradation at this time is “0110”. The above process is performed for each pixel position to convert the raster image 1 which is 6-bit gradation data into a 4-bit output gradation.
When the threshold value and the input gradation value are the same, the value is converted to the closest 4-bit value that is higher than the threshold value. In other words, if the threshold value and the input tone value are the same, the value closest to the threshold value among the 4-bit tone values above the threshold value in the figure is the output tone value. Selected.
In FIG. 4, the pre-stage 4 of the image processing unit converts to a 4-bit gradation based on a threshold value that changes according to the xy coordinate value (x, y) of the input pixel. In this way, by converting from 6 bits for each color to 4 bits for each color, a raster image with a reduced number of bit planes is accumulated in the memory 2.

  The raster image in which the number of bit planes stored in the memory 2 is reduced is converted into 6 bits for each color in the subsequent stage 5 of the image processing unit and sent to the image display unit 3. The rear stage 5 of the image processing unit includes a bit adding unit 14 and a threshold value generating unit 11B. Here, the threshold value generator 11B has the same configuration as the threshold value generator 11A.

FIG. 5 is a circuit diagram showing an internal configuration of the bit adding unit.
The bit adding unit 14 adds the OR of all the 4-bit signals output from the memory 2 as the lower bits, and adds the 2 bits output from the threshold generation unit 11B to the signal that has become 5 bits. The adder 17 adds the upper bits of the signal. Further, the 5-bit signal obtained from the adder 17 is used as an upper bit, and a 6-bit signal added with the lower bit signal output from the threshold value generation unit 11 is output to the image display unit 3.

  One specific example is shown. In the case of the memory signal 1000 and the threshold signal 11, the 5-bit signal input to the adder 17 is 10001, and the 1-bit signal is 1, so the output of the adder 17 is 10010. The 6-bit output signal obtained by adding the lower-order bit signal 1 of the threshold signal is 100101.

Here, all the ORs of the 4-bit signals are taken and added as the lower bits in order to minimize the signal error between the input and output. FIG. 6 shows a signal (4-bit value) and an output signal (6-bit value) accumulated in the memory 2 with respect to the input signal and the output value of the threshold value generator.
In the figure, each input signal and the signal value in the threshold value generator are shown in decimal. The signal stored in the memory is a decimal representation of a 4-bit gradation value, and each output signal is a decimal representation of a 6-bit gradation value.
It can be seen that the maximum error is 2 when the input signal is 7 or more and the maximum error is 3 when the input signal is 6 or less. Further, an output signal by multi-value dither (prior art), an average value for each input signal, a difference between the average value and the input signal value, and a standard deviation of the output signal are also shown.

  It can be said that the smaller the difference between the average value and the input signal, the smaller the color change and the luminance change, and the better the gradation, and the smaller the standard deviation is, the less the graininess. Compared to the error of the prior art, the difference between the average value and the input signal value of this embodiment is almost improved, the standard deviation is reduced at most gradations, and takes a stable low value. I understand that. This indicates that in the present embodiment, the color error and graininess appearing in the prior art are suppressed.

  In the case where the output from the memory 2 is simply combined into 6 bits with the output from the memory 2 as the upper 4 bits and the output from the threshold value generator 11 as the lower 2 bits without taking all ORs of the 4 bit signals, The difference between the input signal values is −1.5, and color changes and luminance changes appear as compared with the case where OR is taken. However, the input signals 2 to 40 have the effect of making the difference from the input signal smaller than in the prior art.

  Further, in FIG. 6, in the case of the input signals 0 to 3, the output signals are the same because the signals accumulated in the memory are the same. If the tone reproducibility of the input signal is desired, the tone of the input signal may be replaced. This gradation conversion of the input signal means conversion of the input signal, for example, (new input signal) = INT ((input signal before replacement) × 60/63 + 3)). Here, INT (A) Means the integer component of A.

  Further, regarding the maximum gradation and the minimum gradation, it is desirable that all dither values be the same before and after the above processing. For example, in addition to the above-described replacement of the gradation, it can be realized by adding a condition that when the signal value stored in the memory is 0, the dither value is not added to the output value. Of course, other processing methods may be used as long as the processing satisfies the above conditions.

  Further, the image processing unit front stage 4 is expressed using the selector 13 and the comparator 12, but the same output can be obtained even if expressed by the subtractor and the quantizer 18, as shown in FIG. . The quantizer 18 has a function of outputting the upper 4 bits of the 6 input bits as they are.

  5 and 7, the series of processing in the image processing unit front stage 4 and the image processing unit rear stage 5 is performed by subtracting the output from the threshold generation unit 11A in the image processing unit front stage 4 from the image processing unit rear stage 5. You can see that it is adding. Thus, it can be seen that the occurrence of graininess and false colors can be suppressed by minimizing the influence of the dither processing on the image quality.

  In the present embodiment, the systematic dither is used in the threshold value generation unit, but the present invention is not limited to this. In other words, the above-described effects can be obtained with a two-dimensional dither matrix in which the same pattern is repeated with a minute length as one cycle in either the vertical or horizontal direction of the image. Note that the smaller the dither matrix cycle, the higher the frequency of periodic noise, making it less noticeable as noise. Therefore, a two-dimensional dither matrix having a two-pixel period is most preferable in both vertical and horizontal directions.

  Further, the threshold generation unit 11B has the same configuration as the threshold generation unit 11A. Therefore, as shown in FIG. 8, only one threshold value generation unit 11 may be provided as a configuration in which the threshold value generation units 11A and 11B are switched and used. In this case, it is only necessary to control whether the output of the threshold generation unit 11 is an input to the comparator 12 or an input to the bit addition unit 14. FIG. 8 shows an example of the control method.

  In FIG. 8, the control signal SEL <b> 2 entering the selector 13 </ b> A and the demultiplexer 15 is output from the input / output switching control unit 16. The input / output switching control unit 16 selects and outputs 0 as SEL2 when the output of the threshold generation unit 11 is sent to the comparator 12, and selects and outputs 1 when sending it to the bit addition unit 14.

  As described above, as the second embodiment of the present invention, the raster image 1 is subjected to image processing to reduce the number of bit planes, and the image processing unit pre-stage 4 and the output signal (raster image) of the pre-image processing unit are accumulated. 2 and an image processing unit rear stage 5 for returning the number of bit planes of the raster image from the memory 2 to the original number of bit planes, and performing reverse processing in the image processing unit front stage 4 and the image processing unit rear stage 5 An image processing apparatus that performs the above has been described. With the above configuration, it is possible to reduce the chip area and power consumption while minimizing the influence on the image quality.

  In addition, by increasing / decreasing the number of bit planes in the pre-stage 4 of the image processing unit and the post-stage 5 of the image processing unit by a multi-value dither method, an image processing apparatus with a simplified configuration of the image processing unit can be obtained.

It is also possible to adopt a configuration in which image processing is performed by software.
FIG. 9 is a flowchart illustrating an example of the image processing method in the former stage of the image processing unit in the present embodiment, and FIG. 10 is a flowchart illustrating an example of the image processing method in the subsequent stage of the image processing unit in the present embodiment. In FIGS. 9 and 10, both the image processing unit front stage and the image processing unit rear stage processing have a software configuration, but there is no problem if only one of them has a software configuration and the other has a hardware configuration.

  FIG. 9 shows an image processing method when the input signal is 6 bits and the number of bit planes at the time of compression is b bits (where b is an integer of 2 to 6). In the first stage 4 of the image processing unit, the input signal gradation I (6 bits), the X coordinate x of the pixel, and the Y coordinate y of the pixel are input (step S11). Next, a dither matrix necessary for generating a threshold value is defined (step S12). Here, among the dither matrix of 4 × 4 systematic dither, called [Bayer array], [[10,4,6,8], [12,0,2,14], [7,9,11,5], [3,15,13,1]] is adopted.

  Then, a threshold value is generated based on the pixel coordinate values x and y (step S13). The threshold generation method is as shown in the figure. xmod4 indicates the remainder of dividing x by 4. Here, the reason why the dither matrix is divided by a power of 2 is that the threshold value differs depending on the number of bits b of the output gradation and becomes a value corresponding to each number of bits. For example, if b = 4, the threshold takes a 2-bit value. Since the value of the dither matrix is 4 bits, it is divided by 2 ^ (4-2) = 4 to obtain 2 bits.

  In step S14, the threshold value d is subtracted from the input signal gradation to cut off the lower bits. In the above example, since b = 4, the lower 2 bits are discarded when 6-4 = 2, and the upper 4 bits are output.

  In FIG. 10, in the latter stage 5 of the image processing unit, the input signal gradation I is b bits, and the X coordinate x and Y coordinate y of the pixel are input (step S21). In step S22 and step S23, the same configuration as that of the image processing unit front stage 4 is used. If the input signal I is 0, the output Iout = d. Otherwise, as shown in step S24, I is an upper bit, d is a lower bit, and 2 ^ in order to reduce the error from the original signal. The one with (5-b) added is output. This 2 ^ (5-b) corresponds to the OR component shown in FIG.

With the algorithm as described above, the image processing apparatus equivalent to the image processing apparatus shown in FIG. 2 can be realized as a configuration in which image processing is performed by software.
The flowcharts shown in FIGS. 9 and 10 are examples, and the present invention is not limited to this as long as the configuration satisfies the present embodiment.

<Third Embodiment>
FIG. 11 is a block diagram illustrating a first configuration example of an image processing apparatus according to the third embodiment of the present invention. The difference from the second embodiment of the present invention is that the raster image 1 is sent to the image display unit 3 as it is between the image processing unit rear stage 5 and the image display unit 3 or the raster image from the memory 2 is displayed as an image. And a selector 13B for selecting whether to send to the unit 3, and a memory use switching control unit 6 for performing selection control in the selector 13B.

  The memory switching control unit 6 controls the selector 13B according to the image to be sent to the image display unit 3. For example, when still image display is performed, since the image is not rewritten, in order to display the image stored in the memory 2, “1” is output from the memory use switching control unit 6 and the selector 13B Sends the raster image output from the rear stage 5 of the image processing unit to the image display unit 3. On the other hand, when moving image display is being performed, the raster image 1 is not stored in the memory, but is displayed as it is on the image display unit 3, so that the memory use switching control unit 6 outputs “0” to the selector 13B.

  With the above-described configuration, moving image / still image switching display is possible, and still image display can be performed with a small chip area and reduced power consumption.

  FIG. 12 is a block diagram illustrating a second configuration example of the image processing apparatus according to the third embodiment of the present invention. In FIG. 12, when the output signal of the memory use switching control unit 6 is “0”, that is, when the raster image 1 is displayed as it is on the image display unit 3 without going through the memory 2, the processing ON / OFF control unit 7 is displayed. Control is performed to stop the processing of the image processing unit front stage 4, the memory 2, and the image processing unit rear stage 5. Thus, by stopping the processing of the image processing unit front stage 4, the memory 2, and the image processing unit rear stage 5, the power consumption can be reduced.

<Fourth Embodiment>
FIG. 13 is a block diagram showing a schematic configuration of an image processing apparatus according to the fourth embodiment of the present invention. The difference from the third embodiment of the present invention shown in FIG. 11 is that the configuration of the bit adding unit 14A and the output from the memory use switching control unit 6 are input to the gradation control unit 7, and the gradation control unit 7 is used to control the gradation of the image display unit 3.

  FIG. 14 is a block diagram showing a schematic configuration of the bit adding unit in the fourth embodiment of the present invention. The bit addition unit 14A performs bit combination with the output from the memory 2 as the upper 4 bits and the output from the threshold value generation unit 11B as the lower 2 bits, and outputs them to the selector 13B. This is a very simplified configuration compared to the bit adding unit 14 in the second embodiment of the present invention shown in FIG.

  FIG. 15 is a diagram illustrating values of an input signal, a signal stored in a memory, and an output signal from the subsequent stage of the image processing unit according to the fourth embodiment of the present invention. As shown in FIG. 15, it can be seen that the average value of the output signal is smaller than the input signal by changing the configuration of FIG. 5 to FIG. In this state, when the display is switched by the selector 13B, a difference occurs in the brightness of the display image. Therefore, the gradation control unit 7 performs display gradation change control. That is, when the output of the memory use switching display unit 6 is “0”, the gradation control unit 7 performs normal gradation control. When the output is “1”, the gradation control unit 7 is shown in FIG. In this way, the output gradation is adjusted so as to have a larger value than the output signal of FIG. This makes it possible to obtain images with substantially the same brightness even when the display is switched by the selector 13B (that is, when the memory 2 is used).

  There are several possible configurations for the gradation control unit 7. For example, a lookup table may be formed and the input signal may be replaced. Also, in the hardware configuration, when the image display unit is an analog gradation type LCD (liquid crystal display) or organic EL (electroluminescent) display, the VT characteristic of the liquid crystal is determined according to the value of the memory use switching control unit 6. A method of changing the value of the gradation voltage of the liquid crystal so as to change may be mentioned.

  With the above configuration, it is possible to provide an image processing apparatus having a configuration with almost no processing in the rear stage 5 of the image processing unit as compared with the first and second embodiments of the present invention.

<Fifth Embodiment>
FIG. 17 is a block diagram showing a schematic configuration of an image processing apparatus according to the fifth embodiment of the present invention. The difference from the third embodiment of the present invention shown in FIG. 11 is that the number of bit planes stored in the memory 2 is 4, 5, and 3 for R, G, and B, respectively. In this configuration, the memory capacity is the same as that of the third embodiment of the present invention.

  The reason why a large number of bit planes are allocated to G and a small number of bit planes is allocated to B is that the granularity that causes a reduction in image quality in multi-value dither processing is more dependent on the luminance difference than the color difference. G has the greatest influence on the luminance component, and B has the least influence. By setting it as such a structure, a granular feeling can further be suppressed. If the number of bit planes is configured as described above in normal multilevel dither processing, the B color error increases, and the flesh color image quality deteriorates.

  FIG. 18 is a diagram illustrating values of an input signal at a pixel gradation B, a signal accumulated in a memory, and an output signal from the latter stage of the image processing unit in the fifth embodiment of the present invention. Further, an output signal by multi-value dither (prior art), an average value for each input signal, a difference between the average value and the input signal value, and a standard deviation of the output signal are also shown. It can be seen that the standard deviation of the present embodiment is reduced in almost all gradations and stably takes a low value as compared with the error of the prior art. This indicates that even if the number of bit planes changes, color errors and graininess are suppressed in this embodiment.

  In FIG. 17, since a 4-bit memory is used for the R component of the raster image, the same processing as that of the image processing unit pre-stage 4 and the image processing unit post-stage 5 shown in the second embodiment of the present invention is performed. However, in the G component and the B component, the configuration of the threshold value generation unit and the bit width sent to each unit are different. FIG. 19 shows the configuration of the image processing unit front stages 4G and 4B and the image processing unit rear stages 5G and 5B. In FIG. 19, the threshold generation units 11G and 11B generate output signals by the generation method shown in FIG.

  With the configuration as described above, luminance errors in RGB color display can be reduced, and an image having an image quality comparable to that of a normal 6-bit display with less graininess can be obtained.

  Furthermore, in FIG. 17, as with the second embodiment of the present invention, it is also possible to adopt a configuration in which only one threshold value generator is provided as a whole. FIG. 21 shows an example of the configuration. The threshold value generator 11 shown in FIG. 21 uses the generation method of the threshold value generator 11B shown in FIG. 20, and the output to the R component is the upper 2 bits and the output to the G component is the upper 1 Use only bits. As a result, it is not necessary to provide a threshold generation unit for each RGB component, and efficiency can be improved.

<Sixth Embodiment>
Up to now, an image processing apparatus has been described in which a 6-bit raster image of each color is stored in a 4-bit memory and a high-quality image is displayed on an image display unit capable of displaying 6 bits of each color based on the data. Here, an image processing apparatus capable of performing display corresponding to 6 bits by using FRC (Frame Rate Control) for an image display unit capable of displaying 4 bits for each color will be described.

  FRC is a method of increasing displayable gradations by periodically changing gradations in an image display device with limited gradation display. For example, in an image display device capable of displaying from 0 to 15 gradations, if the display gradation is periodically changed as 14, 14, 14, 15 with 4 frames as one period, the displayable gradation is 15 × 4 + 1 = 61 gradations, which corresponds to almost 6-bit display.

  FIG. 22 is a block diagram showing a schematic configuration of an image processing apparatus according to the sixth embodiment of the present invention. The difference from the second embodiment of the present invention shown in FIG. 2 is that an FRC image processing unit rear stage 9 is provided instead of the image processing unit rear stage 5 in FIG. VSync is input, and the image display unit 3A can display 4 bits for each color. For convenience, only one block of RGB is shown here.

  Hereinafter, the description will be focused on the rear stage 9 of the FRC image processing unit. The rear stage 9 of the FRC image processing unit includes a threshold generation unit 11B that generates a threshold based on the XY coordinates of the pixel, a 2-bit counter 19 that counts VSync, a threshold generation unit 11B, and a 2-bit counter 19 Of the output from the memory 2 and the output from the memory 2, the value obtained by adding 1 to the output according to the carry value is output to the image display unit 3, or as it is And a selector 13 for setting whether to output a value to the image display unit 3.

  The threshold value generator 11B performs output as shown in FIG. This is the same as the output value of the second embodiment of the present invention. The 2-bit counter 19 is counted every time VSync is input, and its output value changes from 00 → 11 → 01 → 10 → 00 →. The state transition table is shown in FIG. As shown in FIG. 23, the next state is the same as the output value.

  Carry generating unit 20 sets a carry value based on the threshold value output from threshold value generating unit 11B and the output value of 2-bit counter 19. FIG. 24 shows the relationship among the threshold value, the counter output value, and the carry output value. When (threshold value)> (counter output value), “1” is output, and otherwise, “0” is output. In this way, four frames are defined as one cycle, and carry for the threshold value is generated in the cycle.

  Then, a signal to be output by the selector 13 is selected based on the carry value. When the carry value is “0”, an output value from the memory 2 is output to the image display unit 3. When the carry value is “1”, a value obtained by adding 1 to the output value from the memory 2 is output to the image display unit 3.

  FIG. 25 shows values of an input signal, a signal stored in the memory, and an output signal from the rear stage of the FRC image processing unit in the sixth embodiment of the present invention. Further, an output signal by multi-value dither (prior art), an average value for each input signal, a difference between the average value and the input signal value, and a standard deviation of the output signal are also shown. Here, the output signal is originally 4 bits, but in order to compare an error with the input signal, a value obtained by converting 4 bits → 6 bits is used. Further, the output signal from the rear stage 9 of the FRC image processing unit is an average value for four frames (one cycle) obtained by the rear stage 9 of the FRC image processing unit. It can be seen that the standard deviation of the present embodiment is reduced in almost all gradations and stably takes a low value as compared with the error of the prior art. It can also be seen from the comparison with the results in FIG. From this, it can be seen that an image having a picture quality equivalent to 6 bits can be obtained by using the present invention even in an image display device capable of displaying 4 bits and 4 bits.

  With the configuration as described above, it is possible to obtain an image processing apparatus that has higher image quality than the conventional multilevel dither processing and does not require a 6-bit memory as in the conventional FRC.

<Seventh embodiment>
A seventh embodiment in which the present invention is preferably implemented will be described. FIG. 26 is a block diagram illustrating a configuration example of an image processing apparatus according to the seventh embodiment of the present invention. The difference from the third embodiment of the present invention is that a compression processing unit 4A and an expansion processing unit 5A are provided instead of the image processing unit front stage 4 and the image processing unit rear stage 5.

  The memory switching control unit 6 controls the selector 13B according to the image to be sent to the image display unit 3. For example, when still image display is performed, since the image is not rewritten, in order to display the image stored in the memory 2, “1” is output from the memory use switching control unit 6 and the selector 13B Sends the raster image output from the expansion processing unit 5A to the image display unit 3. On the other hand, when moving image display is being performed, the raster image 1 is not stored in the memory 2 but is displayed as it is on the image display unit 3, so that “0” is output from the memory use switching control unit 6 to the selector 13 </ b> B.

With the above-described configuration, moving image / still image switching display is possible, and still image display can be performed with a small chip area and reduced power consumption. This switching display can be applied to any compression processing unit 4A and expansion processing unit 5A, instead of the specific compression / decompression processing as in the image processing unit front stage 4 and the image processing unit rear stage 5. Moreover, it has a great effect.
In other words, the compression processing unit 4A and the expansion processing unit 5A have a specific relationship (for example, the two-dimensional dither matrix is the same) with respect to the image signal input to the memory 2 and the image signal read from the memory 2. There is no need to perform compression / decompression processing.
For example, the compression processing unit 4A and the expansion processing unit 5A perform compression / expansion processing on the image signal input to the memory 2 and the image signal read from the memory 2 using different two-dimensional dither matrices. Also good. That is, the compression processing unit 4A and the decompression processing unit 5A may include threshold value generation units having different configurations.
In addition, it is clear that the same effect can be obtained even if the compression / decompression processing performed by the compression processing unit 4A and the decompression processing unit 5A is not a processing using a two-dimensional dither matrix but another processing method. .

<Eighth Embodiment>
An eighth embodiment in which the present invention is preferably implemented will be described. FIG. 27 is a block diagram showing a configuration example of an image processing apparatus according to the eighth embodiment of the present invention. This image processing apparatus further includes a processing ON / OFF control unit 7 in addition to the configuration of the image processing apparatus according to the seventh embodiment. When the output signal of the memory use switching control unit 6 is “0”, that is, when the raster image 1 is displayed as it is on the image display unit 3 without going through the memory 2, the processing ON / OFF control unit 7 Control is performed to stop the processing of 4A, the memory 2, and the decompression processing unit 5A.

  In the image processing apparatus according to the present embodiment, when the memory use switching control unit 6 outputs “0”, that is, when the memory 2 is not used, the processing ON / OFF control unit 7 includes the compression processing unit 4A and the memory 2. The processing of the decompression processing unit 5A is stopped. Thereby, in addition to obtaining the same effect as the image processing apparatus according to the tenth embodiment, it is possible to further reduce power consumption.

<Ninth embodiment>
A ninth embodiment in which the present invention is preferably implemented will be described. FIG. 28 is a block diagram illustrating a configuration example of an image processing apparatus according to the ninth embodiment of the present invention. The difference from the image processing apparatus according to the third embodiment is that the image has the same capacity as the display capacity of the image display unit 3 capable of displaying 6 bits each with a resolution of X * W and Y (ie, an image of X * Y pixels). It is the point which has the memory 2 which can accumulate | store.
In the present specification, the “resolution of the display device” represents the maximum number of pixels that can be displayed on one screen in the horizontal and vertical directions by the display device (for example, the image display unit 3). For example, a display device having a resolution of 640 × 480 has 640 pixels in the horizontal direction and 480 pixels in the vertical direction, and can display an image smaller than this in one screen.
“Image resolution” is the total number of pixels constituting the image as the product of the number of pixels in the vertical direction and the number of pixels in the horizontal direction, for example, an image with a resolution of 640 × 480. Is an image that occupies an area represented by a rectangle of 640 pixels in the horizontal direction and 480 pixels in the vertical direction.

  In such a case, for example, as shown in FIG. 28, when a double image (X * 2Y) in the vertical direction of the resolution (X * Y) of the image display unit 3 is input as the raster image 1, All images can be stored in the memory 2 by compressing at a compression ratio of 1/2 in the pre-processing unit 4, that is, by halving the number of bit planes. In other words, all the images input as the raster image 1 and having pixels twice the resolution of the image display unit 3 in the vertical direction can be stored in the memory 2. Then, the arbitrary area of the size of X * Y of the input image can be expanded in the latter stage 5 of the image processing unit, and the image display unit 3 can display the arbitrary area of the image larger than the resolution. As described above, even if an image is not input from the outside every frame period, the image stored in the memory 2 is an image having a large resolution such as a scroll image (in other words, the number of pixels is larger than the resolution of the image display unit 3). Even a large number of images) can be displayed.

  When image display is performed without going through the memory 2, X * Y is the maximum resolution of the input image. In other words, when the input image input as the raster image 1 is smaller than X * Y pixels, the memory use switching control unit 6 outputs “0” to the selector 13B, and the raster image 1 is directly transmitted without going through the memory 2. The image is displayed on the image display unit 3.

Although the input image in this example is an image for two continuous screens, the present invention is not limited to this, and it goes without saying that the same effect can be obtained with images of two or more different screens.
In other words, for example, when two raster images of X * Y pixels are stored in the memory 2, each raster image can be stored in the memory 2 by performing the same compression process in the preceding stage 4 of the image processing unit. Is possible. Each raster image can be read out from the memory 2 and subjected to expansion processing in the latter stage 5 of the image processing unit, and then displayed on the image display unit 3.

Thus, according to the present embodiment, when an image having a resolution m times that of the image display unit 3 (m is an arbitrary positive number) is input as the raster image 1, the input image is compressed to 1 / m. And stored in the memory 2. Therefore, even if the input image is a raster image having more pixels than the resolution of the image display unit 3, it can be stored in the memory 2.
Further, by performing expansion processing on the image signal of the image stored in the memory 2 in the latter stage 5 of the image processing unit, the image display unit 3 can display an arbitrary region of an image larger than the resolution.
Furthermore, even if an image is not input from the outside every frame period, the image stored in the memory 2 has an image with a large resolution such as a scroll image (in other words, a larger number of pixels than the resolution of the image display unit 3). Even an image) can be displayed.

<Tenth embodiment>
A tenth embodiment preferably implementing the present invention will be described. FIG. 29 is a block diagram illustrating a configuration example of an image processing apparatus according to the tenth embodiment of the present invention. The image processing apparatus according to the present embodiment includes a selector 13C between the image processing unit front stage 4 and the memory 2, the image processing unit rear stage 5 and the selector 13B, and further controls the selectors 13C and 13D. Is different from the image processing apparatus according to the ninth embodiment in that it has a memory input signal switching control unit 27 for performing the above.

  The memory input signal switching control unit 27 refers to the resolution of the input image or the like and selects whether the image stored in the memory 2 is a compressed image or an uncompressed image. In the following description, the compressed image or the uncompressed image is selected by referring to the resolution. However, the present invention is not limited to this, and the compressed image or the uncompressed image is referred to by referring to the data capacity of the image such as the number of bit planes. Needless to say, it may be selected.

  For example, when the number of pixels of the raster image 1 is X * Y and the memory 2 is used, the memory input signal switching control unit 27 outputs “0” to the selector 13C and the selector 13D, and the memory usage switching unit 6 “1” is output to 13B. As a result, uncompressed images are stored in the memory 2, and uncompressed images are displayed on the image display unit 3.

  Further, when the memory 2 is used when the number of pixels of the raster image 1 is X * 2Y, the memory input signal switching unit 27 outputs “1” to the selectors 13C and 13D, and the memory use switching unit 6 outputs “1” to the selector 13B. 1 "is output. As a result, the image compressed in the first stage 4 of the image processing unit is stored in the memory 2, and the image read from the memory 2 and expanded in the second stage 5 of the image processing unit is displayed on the image display unit 3.

  When the number of pixels of the raster image 1 is X * Y and the memory 2 is not used, it is the same as the first configuration example of the present embodiment, and the memory use switching control unit 6 outputs “0” to the selector 13B. The raster image 1 is directly displayed on the image display unit 3 without going through the memory 2.

  With the configuration described above, it is possible to select whether the image to be stored in the memory 2 is a compressed image or an uncompressed image. In the case where priority is given to the size of the displayable image over the image quality, it is possible to accumulate an image that does not fit on one screen such as a map by selecting a compressed image. In addition, when priority is given to image quality as in the case of a natural still image, by selecting an uncompressed image, an adaptive image processing apparatus excellent in image quality and memory efficiency can be obtained.

<Eleventh embodiment>
An eleventh embodiment in which the present invention is preferably implemented will be described. FIG. 30 is a block diagram illustrating a configuration example of an image processing apparatus according to the eleventh embodiment of the present invention. In the present embodiment, a raster image 1 that is an original image is divided into an image 1A and character information 1B and input to an image processing apparatus.
The image processing apparatus according to the present embodiment is different from the image processing apparatus according to the ninth embodiment in that an image composition unit 28 is provided. The image composition unit 28 generates a composite image of the image 1A with the number of bit planes increased in the latter stage 5 of the image processing unit and the character information 1B.

  Consider a case where a raster image, which is an input image, is divided and input into two layers of image 1A (number of pixels X * Y; 6 bits) and character information 1B (number of pixels X * Y; 1 bit). The composite image in the uncompressed state is 6 bits + 1 bit = 7 bits data in each pixel of X * Y. Since the maximum amount of data that can be stored in the memory 2 is 6-bit data in each pixel of X * Y, a composite image in an uncompressed state cannot be stored in the memory 2.

  In such a case, the memory use switching control unit 6 outputs “1” to the selector 13B and inputs the image 1A to the front stage 4 of the image processing unit. In the first stage 4 of the image processing unit, the compression process similar to the above is performed on the image 1A, and the number of bit planes of the image 1A is reduced from “6” to “5”. The total data amount of the image 1A and the character information 1B with the reduced number of bit planes is 5 bits + 1 bit = 6 bits in each X * Y pixel, and can be stored in the memory 2. It becomes.

  Further, the image 1A in which the number of bit planes read from the memory 2 is reduced to “5” is subjected to the same expansion processing in the latter stage 5 of the image processing unit, and the number of bit planes is changed from “5” to “6”. Will be increased. The image composition unit 28 generates a composite image of the image 1A having the increased number of bits in the latter stage 5 of the image processing unit and the character information 1B read from the memory 2. This composite image is displayed on the image display unit 3.

As described above, in the image processing apparatus according to the present embodiment, when a raster image is divided and input into two layers and cannot be stored in the memory 2 without being compressed, the data of at least one layer is compressed, or The number of bit planes can be reduced and stored in the memory 2, and two layers obtained by expansion or increase in the number of bit planes can be combined and displayed.
For example, as shown in FIG. 30, when the image 1A is a normal 6-bit image and the character information 1B is 1-bit character information, the image composition unit 28 can realize character overlay display. . Further, image display is possible without providing a new memory for overlay display.

  Furthermore, the image processing apparatus according to the present embodiment can independently change the image 1A and the character information 1B. For example, when considering a clock that displays time as a still image and character information 1B as the image 1A, only the character information 1B is acquired at a predetermined interval (for example, every second and every minute) and input to the memory 2. Thus, the processing in the image processing unit front stage 4, the memory 2, and the image processing unit rear stage 5 can be omitted. Thereby, when the raster image 1 is displayed on the image display unit 3, it is possible to reduce power consumption.

  In this embodiment, multi-gradation video and text information are given as examples of two layers constituting a raster image. However, the present invention is not limited to this, and other configurations, for example, superposition of two videos. Such a configuration is also applicable.

<Twelfth embodiment>
A twelfth embodiment preferably implementing the present invention will be described. FIG. 31 is a block diagram illustrating a configuration example of an image processing apparatus according to the twelfth embodiment of the present invention. In the present embodiment, a signal for displaying the raster image 1 is divided into two layers of an image 1A and a control signal 29 for each pixel and is input to the image processing apparatus.
The image processing apparatus according to the present embodiment differs from the image processing apparatus according to the ninth embodiment in that when the image 1A and the control signal 29 cannot be stored in the memory 2 without being compressed, the image 1A is compressed or bit-plane. The number is reduced and stored in the memory 2, and the image obtained by the expansion or the increase in the number of bit planes is displayed on the image display unit 3 based on the control signal 29.

  Consider a case in which a signal for displaying the raster image 1 is divided and input into two layers of an image 1A (number of pixels X * Y; 6 bits) and a control signal 29 (1 bit) for each pixel. The sum of the data amounts of the image 1A and the control signal 29 is 6 bits + 1 bit = 7 bits of data for each pixel of X * Y. Since the maximum amount of data that can be stored in the memory 2 is 6 bits of data for each pixel of X * Y, a signal for displaying the raster image 1 cannot be stored in the memory 2 in an uncompressed state.

  In such a case, the memory use switching control unit 6 outputs “1” to the selector 13B, and inputs a signal for displaying the raster image 1 to the front stage 4 of the image processing unit. In the first stage 4 of the image processing unit, the compression process similar to the above is performed on the image 1A, and the number of bit planes of the image 1A is reduced from “6” to “5”. The total amount of data of the image 1A with the reduced number of bit planes and the control signal 29 of each pixel is 5 bits + 1 bit = 6 bits of data amount for each pixel of X * Y, and is stored in the memory 2 It becomes possible.

  Further, the image 1A in which the number of bit planes read from the memory 2 is reduced to “5” is subjected to the same expansion processing in the latter stage 5 of the image processing unit, and the number of bit planes is changed from “5” to “6”. Will be increased. The image 1A with the increased number of bit planes is displayed on the image display unit 3 based on the control signal 29 for each pixel read from the memory 2.

  As described above, in the image processing apparatus according to the present embodiment, the signal for displaying the raster image 1 is divided and input into at least one image and at least one control signal. When possible, at least one image can be compressed or stored in the memory 2 with a reduced number of bit planes, and an image obtained by decompression or increasing the number of bit planes can be displayed based on a control signal.

  Furthermore, the image processing apparatus according to the present embodiment can change the image 1A and the control information 29 independently. This is the same as in the fourteenth embodiment. For example, by updating only the control information 29 of the image 1A and control information 29 stored in the memory 2, the image processing unit front stage 4, the memory 2 and the image processing are updated. The processing in the rear part 5 can be omitted. Thereby, when the raster image 1 is displayed on the image display unit 3, it is possible to reduce power consumption.

<Thirteenth embodiment>
In the configuration having the memory up to the twelfth embodiment of the present invention described above, the image processing apparatus has been described which can reduce the memory capacity and power consumption and can obtain an image quality comparable to the conventional technology. In the thirteenth and fourteenth embodiments of the present invention, in addition, the transfer capacity can be reduced in transferring a raster image from the first device to the second device. The configuration will be described below.

  FIG. 32 is a block diagram showing a schematic configuration of an image transmission apparatus according to the thirteenth embodiment of the present invention. In FIG. 32, an image transmission apparatus according to a thirteenth embodiment of the present invention includes a first apparatus 7 that transmits a raster image and a second apparatus 8 that receives the raster image. In the first device 7, the raster image 1 having 6-bit gradation for each color is converted into 4-bit gradation for each color in the front stage 4 of the image processing unit and transmitted to the second device 8. In the second device 8, the raster image received from the first device 7 is processed in the latter stage 5 of the image processing unit, returned to a raster image of 6-bit gradation for each color, and output to the image display unit 3.

  Here, the pre-stage 4 of the image processing unit and the post-stage 5 of the image processing unit have the same configurations as those described in the above embodiments.

  With the above configuration, it can be seen that there is almost no image quality degradation in the transmission of the raster image from the first device 7 to the second device 8, and image transmission can be performed with a small transmission capacity. This is effective in the case where the image transmission capacity is insufficient or in reducing the number of transmission paths between the first device and the second device.

Note that the second device 8 included in the image transmission device according to the present embodiment also represents a preferred embodiment of the image reception device according to the present invention.
The image receiving apparatus according to the present invention receives a raster image having a smaller number of bit planes than the original image, as in the second apparatus 8, and compares the received image with the original image by increasing the number of bit planes. As a result, an image comparable to the image quality can be obtained. Further, since the image with the number of bit planes reduced from the original image is received on the transmission side, the image can be received efficiently.
For example, the number of bit planes has been reduced on the transmission side when it is desired to receive a raster image of 6 bits for each color (18 bits in total) in a device having a transmission path for receiving an image of only a 16-bit bus width. By receiving the raster image of the state and increasing the number of bit planes of this image, it is possible to receive in parallel each color an image that is comparable in quality to the original image.

<Fourteenth embodiment>
FIG. 33 shows an image transmission apparatus according to the fourteenth embodiment of the present invention. This image transmission device includes a first device 7 that transmits a raster image and second devices 8a, 8b, and 8c that receive the raster image. Note that the bus widths of the transmission paths between the first device 7 and the second devices 8a, 8b, and 8c are 15 bits, 12 bits, and 9 bits, respectively.
The first device 7 includes an image processing unit front stage 4, a bit plane reduction number control unit 50, a selector 51, and a demultiplexer 52. The first stage 4 of the image processing unit reduces the number of bit planes (6-bit gradation for each color) of the raster image 1 to a predetermined value, and selects a raster image having the number of bit planes according to an instruction from the bit plane reduction number control unit 50. To 51. The bit plane reduction number control unit 50 controls the selector 51 according to which of the second devices 8a to 8c transmits the raster image 1 and performs image processing on an image having the number of bit planes suitable for the receiving device. Output to the front stage 4. Further, the demultiplexer 52 is controlled, and the image processing unit front stage 4 selects the transmission path of the raster image in which the number of bit planes is reduced.
The second device 8a includes an image processing unit rear stage 8a and an image display unit 3a. The rear stage 5a of the image processing unit performs the same processing on the 5-bit raster image of each color transmitted from the first device 7 and restores it to a 6-bit raster image of each color. The image display unit 3 displays the raster image restored to 6 bits for each color.
The second device 8b restores the raster image of 4 bits for each color to 6 bits for each color in the rear stage 5b of the image processing unit, and the second device 8c converts the raster image for each color of 3 bits for each color in the rear stage 5c of the image processing unit. Other than restoring to 6 bits, it is the same as the second device 8a.

The operation of the image transmission apparatus according to the present embodiment will be described. Here, a case where the raster image 1 is transmitted to the second device 8a will be described as an example. The first stage 4 of the image processing unit processes the 6-bit raster image 1 for each color to generate a 5-bit, 4-bit, and 3-bit raster image for each color. The bit plane reduction number control unit 50 controls the selector 51 to cause the demultiplexer 52 to input a raster image corresponding to the receiving apparatus, that is, a raster image of 5 bits for each color. At this time, the bit plane reduction number control unit 50 sends the control signal to the selector 51 as “a”. Since the control signal output from the bit plane reduction number control unit 50 is “a”, the raster image input to the demultiplexer 52 is output to the transmission path to the second device 8 a.
In the second device 8a, the raster image received from the first device 7 is processed in the latter stage 5 of the image processing unit to return it to a raster image of 6-bit gradation for each color and displayed on the image display unit 3a.

  As described above, the image transmission apparatus according to the present embodiment can select how much the number of bit planes of the raster image is to be reduced according to the reception-side apparatus. Therefore, since the raster image having the number of bit planes corresponding to the bus width of the transmission path to the receiving apparatus and the capabilities of the image processing unit rear stages 5a to 5c can be transmitted, the efficiency of the transmission capacity can be improved. .

<Fifteenth embodiment>
Since the present invention aims to reduce the chip area and power consumption, the image processing unit does not require complicated processing and has a simple configuration. Therefore, the present invention can be mounted on a driver or controller chip of a display device having a built-in memory to obtain the above effect. Further, the present invention can be applied to a polysilicon circuit on which these driver and controller are mounted on a glass substrate. Is also applicable.

  FIG. 34 shows a liquid crystal display device in which an image processing unit and a drive circuit unit are formed using a polysilicon thin film transistor circuit on a glass substrate according to the fifteenth embodiment of the present invention. The input signal is 6 bits for each color of RGB, the memory is 4 bits for each color of RGB, and the output is 6 bits for each color of RGB. An external raster image 1 is displayed on the liquid crystal display unit 10. The liquid crystal display unit 10 includes pixels 31 and thin film transistors 32 arranged in a matrix, and a plurality of data lines 33 and a plurality of gate lines 34 arranged in a lattice pattern with respect to the set of the pixels 31 and the thin film transistors 32. Are connected one by one. Each pixel 31 is written with a signal on the data line 33 connected to the thin film transistor 32 when the thin film transistor 32 is turned on by a signal from the gate line 34.

  The raster image 1 is sent to the image processing unit front stage 4 and the data register 23. The raster image input to the first stage 4 of the image processing unit is subjected to the image processing as described in the twelfth embodiment of the present invention, and is stored in the memory 2 having a total of 12 bits in RGB. Then, data is read from the memory 2 as necessary, and image processing is performed in the latter stage 5 of the image processing unit. The output of the image processing unit rear stage 5 is sent to the selector 13B. Here, the processing in the image processing unit front stage 4, the memory 2, and the image processing unit rear stage 5 is based on the method described up to the twelfth embodiment of the present invention. Therefore, the XY coordinates of the pixels when writing to or reading from the memory 2 are required as control signals input to the image processing unit front stage 4 and the image processing unit back stage 5. In addition, the control signal which can derive | lead-out the XY coordinate of a pixel instead of the XY coordinate of a pixel, for example, VSync, HSync, CLK may be sufficient. The memory 2 is controlled by the memory control unit 26 to switch between reading and writing and to control data input / output addresses. At least the XY coordinates of the pixels are input to the memory control unit 26 as in the case of the image processing unit front stage 4 and the image processing unit back stage 5.

  FIG. 35 is a circuit diagram showing the configuration of the shift register 21A and the data register 22 in the liquid crystal display device. The raster image input to the data register 22 is sequentially stored with 6-bit data based on an output signal from an S / R (shift register) 21A, and is latched by a latch 23. The output from the latch 23 is sent to the selector 13B.

FIG. 36 is a circuit diagram showing a configuration of the selector 13B in the liquid crystal display device.
The selector 13B sends to the DAC 24 based on the control data from the memory use switching control unit 6 depending on whether to display the image stored in the memory 2 from the rear stage 5 of the image processing unit or to display the image from the outside as it is. Select data. The DAC 24 converts each color 6-bit digital signal from the selector 13B into an analog signal, and the data line selector 25 outputs the analog signal to a desired data line.

  The output from the data line selector 25 is sent to the liquid crystal display unit 10 and is written into the pixel 31 via the thin film transistor 32 in the row of the gate line 34 selected by the shift register 21B.

  In such a configuration, in the fifteenth embodiment of the present invention, it is possible to obtain a liquid crystal display device in which the image processing circuit shown in the twelfth embodiment of the present invention is built on a glass substrate. The image processing unit front stage 4 and the image processing unit rear stage 5 can each be configured with a small number of transistors.

  FIG. 37 shows an example of the logic configuration of the image processing unit pre-stage 4 and the image processing unit post-stage 5 that accumulate 6-bit signals in a 4-bit memory and develop them into 6 bits. In FIG. 37, it consists only of 2 input, 3 input NAND, and an inverter. Therefore, it can be seen that the area of the image processing circuit is sufficiently smaller than the memory area, and the area of the circuit portion can be reduced.

  Each of the above-described embodiments is an example of a preferred embodiment of the present invention, and various modifications can be made without departing from the spirit of the present invention.

  For example, in each of the above embodiments, as the image processing method, multi-value dither processing using a two-dimensional dither matrix and bit addition based on the two-dimensional dither matrix are performed. The present invention is not limited, and any image processing that does not show the false color, false contour, and graininess can be applied.

  In each of the above embodiments, when reducing the number of bit planes of the raster image, multi-level dither processing is performed using a two-dimensional dither matrix, and when increasing the number of bit planes, multi-level dither processing is used. Bits are added based on the two-dimensional dither matrix, but the reverse image when the number of bit planes decreases and increases, such as multi-level dither processing using random dither instead of the two-dimensional dither matrix Other image processing methods that perform processing may be applied.

Furthermore, in the second embodiment, the configuration in the case where image processing is performed by software processing has been described. However, in the image processing apparatus and the image transmission apparatus according to other embodiments, image processing is performed as in the second embodiment. Can be configured to be performed by software processing.
Thus, the present invention can be variously modified.

It is a flowchart which shows the flow of a process of the image processing method which is the 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the image processing apparatus which is the 2nd Embodiment of this invention. It is a top view which shows the production | generation method of the output signal of the threshold value generation part of FIG. It is a schematic diagram which shows the process of the image process part front part of FIG. FIG. 3 is a circuit diagram showing an internal configuration of a bit addition unit in FIG. 2. It is a list which shows the input signal and output signal in the 2nd Embodiment of this invention. It is a block diagram which shows the other structure of the image process part front part of FIG. It is a block diagram which shows the other structure of the image processing apparatus which is the 2nd Embodiment of this invention. It is a flowchart which shows the image processing method by an image processing part front part. It is a flowchart which shows the image processing method by an image processing part back | latter stage. It is a block diagram which shows the structure of the image processing apparatus which is the 3rd Embodiment of this invention. It is a block diagram which shows the other structure of the image processing apparatus which is the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 4th Embodiment of this invention. It is a circuit diagram which shows the internal structure of the bit addition part of FIG. It is a list which shows the input signal and output signal in the 4th Embodiment of this invention. It is a figure which shows the change of the gradation based on the kind of input signal by the gradation control part of FIG. It is a block diagram which shows the structure of the image processing apparatus which is the 5th Embodiment of this invention. It is a list which shows the input signal and output signal of B component in the 5th Embodiment of this invention. FIG. 16 is a block diagram illustrating a detailed configuration of a front stage of the image processing unit and a rear stage of the image processing unit in FIG. 15. FIG. 16 is a list showing input / output signal values in the threshold value generator of FIG. 15. FIG. It is a block diagram which shows the other structure of the image processing apparatus which is the 5th Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 6th Embodiment of this invention. FIG. 21 is a state transition diagram of the 2-bit counter of FIG. 20. FIG. 21 is a table showing input / output signal values of the carry generation unit of FIG. 20. FIG. It is a list which shows the input signal and output signal in the 6th Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 7th Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 8th Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 9th Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 10th Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 11th Embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus which is the 12th Embodiment of this invention. It is a block diagram which shows schematic structure of the image transmission apparatus which is the 13th Embodiment of this invention. It is a block diagram which shows schematic structure of the image transmission apparatus which is the 14th Embodiment of this invention. It is a block diagram which shows the structure of a liquid crystal display device. FIG. 35 is a block diagram illustrating configurations of a shift register and a data register in FIG. 34. It is a circuit diagram which shows the internal structure of the selector of FIG. FIG. 35 is a logic configuration diagram of an image processing unit upstream and an image processing unit downstream in the liquid crystal display device of FIG. It is a block diagram which shows the conventional image processing apparatus. It is a figure which shows the problem at the time of applying the invention of Japanese Patent Publication No. 2-8493 to image processing.

Explanation of symbols

1 Raster image 1A Raster image (image)
1B raster image (character information)
2 Display image memory 3, 3A Image display unit 4 Image processing unit upstream 4A Compression processing unit 5 Image processing unit downstream 5A Decompression processing unit 6 Memory use switching control unit 7 Raster image transmission side (first device)
8 Raster image receiving side (second device)
9 Subsequent stage of FRC image processing unit 10 Liquid crystal display unit 11, 11A, 11B Threshold generation unit 12 Comparator 13, 13A, 13B, 13C, 13D, 51 Selector 14, 14A Bit addition unit 15, 52 Demultiplexer 16 Input / output switching Control unit 17 Adder 18 Quantizer 19 Counter 20 Carry generation unit 21A, 21B Shift register 22 Data register 23 Latch 24 D / A converter 25 Data line selector 26 Memory control unit 27 Memory input signal switching control unit 28 Image composition unit 29 Control signal 31 Pixel 32 Thin film transistor 33 Data line 34 Gate line 50 Bit plane reduction control unit

Claims (17)

After reducing the number of bit planes of the first raster image that is the original image, the number of bit planes of the raster image having the reduced number of bit planes is increased to be less than or equal to the number of bit planes of the original image, and the second raster image An image processing device for generating
First image processing means for performing multi-value dither processing using a two-dimensional dither matrix when reducing the number of bit planes of the first raster image;
Second image processing means for performing bit addition processing based on the two-dimensional dither matrix used by the first image processing means when increasing the number of bit planes of the raster image in which the number of bit planes has decreased;
Selecting means for selecting and outputting either the first raster image or the second raster image, and the selecting means selects the second raster image when the original image is a still image. And the first raster image is selected when the original image is a moving image. After reducing the number of bit planes of the first raster image that is the original image, the number of bit planes of the raster image having the reduced number of bit planes is increased to be less than or equal to the number of bit planes of the original image, and the second raster image An image processing device for generating
First image processing means for performing multi-value dither processing using a two-dimensional dither matrix when reducing the number of bit planes of the first raster image;
When increasing the number of bit planes of the raster image in which the number of bit planes has decreased, bit addition processing is performed based on the two-dimensional dither matrix used by the first image processing means, and the signal value of the original image Second image processing means for adding an offset value so that a difference between the average value of all the dither values of the raster image having the increased number of bit planes is minimized,
An image processing apparatus comprising: selection means for selecting and outputting either the first raster image or the second raster image.   The first raster image is an RGB color image in which each color of the RGB signal has the same number of bit planes, and the amount of decrease in the number of bit planes is largest for the B signal and smallest for the G signal. The image processing apparatus according to claim 1 or 2. An image processing apparatus that compresses and decompresses data of a first raster image that is an original image to generate a second raster image,
First image processing means for compressing the first raster image;
Second image processing means for decompressing the data compressed by the first image compression means to generate the second raster image;
Selecting means for selecting and outputting either the first raster image or the second raster image, and the selecting means selects the second raster image when the original image is a still image. And the first raster image is selected when the original image is a moving image. Storing means for storing raster image data obtained by the first image processing means;
5. The image according to claim 1, wherein the second image processing unit reads the data of the compressed raster image stored in the storage unit and performs the image processing. 6. Processing equipment.   The first and second image processing means perform image processing so that the maximum value and the minimum value of element components of a raster image do not change before and after the image processing. The image processing apparatus according to claim 5.   The image processing apparatus according to claim 1, wherein the second image processing unit is formed on the same substrate as a drive circuit of the display device.   The image processing apparatus according to claim 1, wherein the first image processing unit is formed on the same substrate as a drive circuit of the display device. An image processing method for generating a second raster image by reducing the number of bit planes of the first raster image that is the original image and then increasing the number of bit planes of the raster image to be less than or equal to the number of bit planes of the original image Because
A selection step of selecting which of the first and second raster images to output;
A first image processing step of performing multi-value dither processing using a two-dimensional dither matrix when reducing the number of bit planes of the first raster image;
A second image that performs bit addition processing based on the two-dimensional dither matrix used in the first image processing step when increasing the number of bit planes of the raster image processed in the first image processing step. Processing steps;
An output step of outputting one of the first raster image and the second raster image selected in the selection step;
In the selecting step, a second raster image is selected when the original image is a still image, and a first raster image is selected when the original image is a moving image. . After reducing the number of bit planes of the first raster image that is the original image, the number of bit planes of the raster image having the reduced number of bit planes is increased to be less than or equal to the number of bit planes of the original image, and the second raster image An image processing method for generating
A selection step of selecting which of the first and second raster images to output;
A first image processing step of performing multi-value dither processing using a two-dimensional dither matrix when reducing the number of bit planes of the first raster image;
When the number of bit planes of the raster image processed in the first image processing step is increased, bit addition processing is performed based on the two-dimensional dither matrix used in the first image processing step, and the original image A second image processing step of adding an offset value so as to minimize a difference between the signal value of the image data and the average value of all the dither values of the raster image having the increased number of bit planes;
An image processing method comprising: an output step of outputting one of the first raster image and the second raster image selected in the selection step. The first raster image is an RGB color image in which each color of the RGB signal has the same number of bit planes,
11. The image processing method according to claim 9, wherein the amount of reduction in the number of bit planes is the largest for the B signal and the smallest for the G signal. An image processing method for compressing data of a first raster image that is an original image and then decompressing the compressed raster image data to generate a second raster image,
A selection step of selecting which of the first and second raster images to output;
A first image processing step of compressing the first raster image;
A second image processing step of decompressing the data compressed in the first image processing step to generate the second raster image;
An output step of outputting one of the first and second raster images selected in the selection step;
In the selecting step, a second raster image is selected when the original image is a still image, and a first raster image is selected when the original image is a moving image. . A storage step of storing the raster image data obtained by the first image processing step in the storage unit after the first image processing step;
13. The image processing method according to claim 9, wherein in the second image processing step, raster image data stored in the storage means is read and image processing is performed.   If the storage capacity of the storage means is smaller than the raster image data obtained in the first image processing step before the storage step, the raster image data obtained in the first image processing step The image processing method according to claim 13, further comprising a step of compressing the image to a storage capacity of the storage unit or less.   10. The selecting step, wherein the second raster image is selected when the original image is a still image, and the first raster image is selected when the original image is a moving image. The image processing method according to claim 14.   After the selection step, when the first raster image is selected in the selection step, a processing stop step for stopping the image processing by the first image processing step and the second image processing step. The image processing method according to claim 9, further comprising:   The image processing is performed so that maximum values and minimum values of element components of the first raster image and the second raster image coincide with each other in the first and second image processing steps. The image processing method according to any one of 9 to 16.

Images