JP2010141775A - Display device driving circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by increasing the compression rate when a display image shows no large deterioration of image quality even if the compression rate is increased, and to ensure enough image quality after data expansion by decreasing the compression rate when the display image shows large image deterioration when increasing the compression rate. <P>SOLUTION: The display device driving circuit (101) includes a display data compression circuit (109), a recording circuit (110), a display data expansion circuit (111) and output circuits (112 and 113). The display device driving circuit is also provided with a compression rate setting circuit (107), and the display data compression circuit includes a function to compress display data according to the compression rate set by the compression rate setting circuit. Thus, when a display image shows no large deterioration even if the compression rate is increased, the compression rate is increased to reduce consumption power. In addition, when the display image shows large deterioration when increasing the compression rate, the compression rate is decreased to ensure enough image quality after data expansion. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display data compression processing technique, and more particularly to a technique effective when applied to a display device driving circuit and a display device.

  In recent years, in mobile devices such as mobile phones, display panels have become higher definition, and the resolution of the display panel is becoming VGA and HD image quality display is becoming mainstream. When the panel has high definition, power consumption due to transfer of display data increases. Therefore, the frame memory is built in the driver, and the method of reducing the power consumption by transferring the display data only when the video changes is taken. An increase in power consumption due to reading is a problem.

  In connection with the increase in the frame memory, for example, as disclosed in Patent Document 1 and Patent Document 2, the size of the frame memory is reduced by compressing the display data and reducing the data amount in the display drive circuit. Techniques to do this have been proposed. By reducing the amount of data in the frame memory, power consumption due to reading from the frame memory can be reduced.

JP 2007-108439 A JP 2006-338028 A

  The inventors of the present invention have examined the above-described conventional techniques and found the following various problems.

  (1) The display data is stored after being compressed to the size of the frame memory prepared in the drive circuit, and is displayed on the display device after being decompressed during display. As shown in the above prior art, generally, when the compression rate is large (the size of the frame memory after compression is reduced), the image quality of the display image after data expansion is deteriorated. The relationship between the compression rate and the image quality of the display image after expansion differs depending on the display image. In general, even if the compression rate is increased for a solid image or a natural image with a gentle change, the image quality degradation is small. A user interface image having a lot of fine edges has a larger image quality degradation than the solid image even at the same compression rate. Therefore, if all images are compressed at the same compression rate, image quality degradation will be greater in user interface images with many fine edges. Further, even when displaying a solid image or a natural image with gentle changes, the power consumption reduction rate cannot be increased.

  (2) The display screen of a mobile phone or the like is displayed in finely divided areas, and there are areas where icons such as radio wave status and time are always displayed, and areas where natural images, videos, etc. are displayed. As described above, the user interface image and the natural image have different characteristics. Therefore, when the display data is compressed at the same compression rate, the image quality is deteriorated in the user interface image, and the power consumption cannot be reduced much in the natural image.

  (3) As the definition becomes higher, the power consumption related to the display data transfer between the CPU and the display device drive circuit becomes a big problem. In recent years, due to the appearance of a high-performance touch panel, a request for data transfer of touch information from the display screen to the CPU has increased, and the amount of data transferred on the bus between the CPU and the display device driving circuit has increased.

  (4) Since the characteristics of a user interface image displayed on a mobile phone or the like are different from those of a natural image, image quality degradation occurs in the user interface image when display data is compressed using the same compression algorithm.

  (5) A CPU such as a mobile phone has a huge amount of processing, and it is difficult to determine and set the compression rate for each display image.

  The object of the present invention is to reduce the power consumption by increasing the compression ratio in the case of a display image in which the image quality does not deteriorate even when the compression ratio is increased. Is to provide a technique capable of lowering the compression rate and ensuring sufficient image quality after data expansion.

  Another object of the present invention is a display device or display device drive circuit that displays different types of images for each region. Power consumption can be reduced by increasing the compression ratio, and increasing the compression ratio can reduce the compression ratio in the case of a display area with a large image quality deterioration, and ensure sufficient image quality after data expansion. It is to provide a display data compression / decompression technique.

  Another object of the present invention is to reduce the power consumption consumed by the bus between the CPU and the display device drive circuit, and to reduce the image data degradation even if the compression ratio is increased while reducing the ratio of display data transfer on the bus. For display images that are not large, the power consumption can be reduced by increasing the compression rate, and for display images that experience large image quality degradation when the compression rate is increased, the compression rate is lowered to ensure sufficient image quality after data expansion. It is to provide technology that makes it possible.

  Another object of the present invention is to compress display data using a different algorithm for each region in a display device or a display device driving circuit that displays different types of images for each region. It is an object of the present invention to provide a display data compression / decompression technique capable of ensuring sufficient image quality.

  Another object of the present invention is to automatically determine a display image in which display quality is not greatly deteriorated even if the compression rate is increased and a display image in which image quality is greatly deteriorated when the compression rate is increased in the display device or the display device drive circuit, It is to provide a technique capable of changing the compression rate for each display image.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  In order to achieve the above object, the display device driving circuit is provided with a compression rate setting circuit that enables the setting of the compression rate of display data, and the display data compression circuit is provided with a compression rate set in the compression rate setting circuit. A function for compressing display data is provided.

  In order to achieve the above object, a display area setting circuit for setting the position of the display area and a compression ratio setting circuit for each display area are provided so that the display area can be divided into a plurality of areas and the compression ratio can be set for each display area. Is.

  In order to achieve the above object, a compression method setting circuit capable of setting a compression method corresponding to the display area is provided, and the display is performed by switching the compression method according to the set value of the compression method setting circuit and the display position of the display data. Compress data.

  In order to achieve the above object, the display device driving circuit has a step of performing quantization with at least a quantization coefficient in the compression step, and setting of the compression ratio setting circuit according to the magnitude of the quantization coefficient. A circuit whose value can be updated is provided.

  In order to achieve the above object, the CPU is provided with a compression rate setting circuit capable of setting the compression rate of the display data, and the display data compression circuit compresses the display data according to the compression rate set in the compression rate setting circuit. The display data compressed by the display data compression circuit is transferred to the display data expansion circuit via the recording circuit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, in the case of a display image in which the image quality does not deteriorate greatly even if the compression rate is increased, the power consumption can be reduced by increasing the compression rate. In the case of a display image in which the image quality is greatly degraded by increasing the compression rate, the compression rate is increased. It is possible to provide a technique that can reduce the image quality and ensure sufficient image quality after data expansion.

  When different types of images are displayed in each area, if the display area is a display image that does not deteriorate image quality even when the compression ratio is increased, the power consumption can be reduced by increasing the compression ratio. When the display area of a display image with a large image quality degradation is increased, the compression rate is lowered, and a display data compression / expansion technique that makes it possible to ensure a sufficient image quality after data expansion can be provided.

  In the case of a display image that reduces the power consumption consumed by the bus and reduces the rate required to transfer the display data on the bus, and the image quality does not deteriorate significantly even if the compression rate is increased, the power consumption can be increased by increasing the compression rate. In the case of a display image in which the image quality is greatly deteriorated when the compression rate is increased, the compression rate can be lowered, and a technique capable of ensuring sufficient image quality after data expansion can be provided.

  In display devices and display device drive circuits that display different types of images for each region, display data is compressed using a different algorithm for each region to ensure sufficient image quality after data expansion. It is possible to provide a display data compression / decompression technique that enables this.

  In a display device or display device drive circuit, a display image whose image quality does not deteriorate greatly even when the compression rate is increased and a display image whose image quality is greatly deteriorated when the compression rate is increased are automatically identified, and the compression rate is changed for each display image. Possible technology can be provided.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A display device driving circuit (101) according to a typical embodiment of the present invention is a display data compression circuit (109) capable of reducing the amount of display data by compressing image display data. A recording circuit (110) capable of storing display data compressed by the display data compression circuit, a display data decompression circuit (111) for decompressing display data read from the recording circuit, and the display data decompression And an output circuit (112, 113) capable of outputting the display data expanded by the circuit to the display unit. The display device driving circuit includes a compression rate setting circuit (107) that enables the compression rate of the display data to be set. The display data compression circuit displays the display according to the compression rate set in the compression rate setting circuit. Includes the ability to compress data.

  According to the above configuration, in the case of a display image in which the image quality does not deteriorate significantly even when the compression rate is increased, the power consumption can be reduced by increasing the compression rate. In this case, the compression rate can be lowered to ensure sufficient image quality after data expansion.

  [2] In the above [1], the display device driving circuit includes a display area setting circuit (107) capable of setting a plurality of display areas. The compression rate setting circuit includes a function capable of setting a compression rate corresponding to the display area. The display data compression circuit includes a function of compressing the display data by switching a compression rate according to a set value of the display area setting circuit and a display position of the display data. As a result, in a display device or a display device drive circuit that displays different types of images for each region, the compression rate is increased in the case of a display image display region where image quality degradation does not increase even when the compression rate is increased. Thus, the power consumption can be reduced, and when the compression ratio is increased, the display area of the display image having a large image quality deterioration can be reduced to ensure a sufficient image quality after data expansion.

  [3] In the above [2], the display device driving circuit includes a compression method setting circuit (1001) capable of setting a compression method corresponding to the display area. The display data compression circuit compresses the display data by switching the compression method according to the set value of the compression method setting circuit and the display position of the display data. This reduces the power consumed by the bus, lowers the rate required for the display data transfer on the bus, and increases the compression rate for display images that do not experience significant image quality degradation even when the compression rate is increased. Thus, the power consumption can be reduced, and when the compression rate is increased, the display rate of a display image with a large deterioration in image quality can be reduced, and sufficient image quality after data expansion can be ensured.

  [4] In the above [1], the display device driving circuit includes a step of performing quantization with at least a quantization coefficient in a compression step, and setting of the compression ratio setting circuit according to a magnitude of the quantization coefficient. A circuit (1305) capable of updating the value is included. As a result, in display devices and display device drive circuits that display different types of images for each region, display data is compressed using a different algorithm for each region, thereby ensuring sufficient image quality after data expansion. can do.

  [5] The display device (100) includes a display device drive circuit (101) and a display unit (105). The display device driving circuit (101) includes a CPU (102) including a display data compression circuit (901) capable of reducing the data amount of the display data by compressing image display data, and a compressed display. A recording circuit (110) capable of storing data, a display data expansion circuit (111) for expanding display data read from the recording circuit, and an output capable of outputting display data expanded by the display data expansion circuit Circuit (112, 113). The CPU (102) includes a compression rate setting circuit (902) capable of setting the compression rate of the display data. The display data compression circuit includes a function of compressing the display data in accordance with a compression rate set in the compression rate setting circuit. The display data compressed by the display data compression circuit is transferred to the display data expansion circuit via the recording circuit.

  According to the above configuration, in a display device or a display device driving circuit, a display image that does not deteriorate image quality even when the compression rate is increased and a display image that greatly deteriorates image quality when the compression rate is increased are automatically identified and compressed. The rate can be changed for each display image.

2. Next, the embodiment will be described in more detail.

  Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  In general, when compressing still image data, there are two typical compression methods. The first is a method using orthogonal transform and entropy coding, in which compression is performed according to the blocks shown in FIG. The other is a method called BTC (Block Truncation Coding). Each is briefly described below.

  First, a method using the orthogonal transform and entropy coding shown in FIG. 2 will be described. In FIG. 2, reference numeral 201 denotes a block that performs color space conversion. In general, a display device driving circuit such as a liquid crystal driver receives a display image in RGB format from a CPU. Since the RGB hue is a format with many overlaps between colors, a color space with little overlap between parameters is generally used during compression processing. For example, various color spaces for compression such as YUV, YCbCr, YCoCg have been proposed. The type of color space to be compressed does not affect this patent, and any type may be used. The color space conversion circuit 201 converts RGB data into color space data for compression.

  Reference numeral 202 denotes an orthogonal transformation circuit. In the orthogonal transformation circuit, the display image is divided into blocks of 4 pixels × 4 pixels, 8 pixels × 8 pixels, 16 pixels × 16 pixels, etc., and the color data arranged in the space is converted by performing an operation with the orthogonal transformation matrix. Divide into low and high frequency components. Data compression is performed by utilizing the fact that the high frequency component generally has a small value. Examples of the orthogonal transform include Hadamard transform, DCT used in MPEG, JPEG, and Wavelet used in JPEG2000. In addition, the size of the orthogonal matrix of the orthogonal transformation is various, such as 4 × 4, 8 × 8, and 16 × 16. The types of these orthogonal transforms do not affect the present patent, and anything may be used.

  Reference numeral 203 denotes a quantization circuit. The value is reduced by dividing the value obtained by the orthogonal transformation by a constant. This constant is called a quantization coefficient.

  Reference numeral 204 denotes an entropy encoding circuit. Entropy coding is a coding method in which codes having different code lengths are assigned according to the appearance probability of numerical values. In general, the high frequency component has a very high probability of taking a small value such as 0, 1, etc., so entropy coding is performed, and 0 having the highest probability of appearance is assigned to a 1-bit code to reduce the amount of data. Perform compression. Examples of entropy codes include Huffman codes and Exp-Golomb codes, but the types of these entropy codes do not affect the present invention and any may be used.

  Reference numeral 205 denotes a memory write control block. In this block, data compression is performed by recording a variable-length code in a memory.

  Next, BTC will be described with reference to FIGS. Also in BTC, a display image is blocked in a size of 4 × 4, 8 × 8, etc., and compressed. First, as shown in FIG. 11, the display image is blocked by the blocking circuit 1101. For example, it is assumed that the block is formed into a block of 4 pixels × 4 pixels. For example, it is assumed that the value of R is 1201 in RGB signals in a certain block. The representative value extraction circuit 1102 extracts a representative value. Various extraction methods have been proposed as representative value extraction methods. For example, the average value of the entire block is used as a threshold value, and the average value of values larger than the threshold value and the average value of values smaller than the threshold value are extracted as representative values. There is a way. In this way, the representative value 1202 and the representative value 1203 are extracted. For example, the representative values in this case are 16 and 227. The pixel assignment circuit 1103 assigns the R value of each pixel to 0 or 1, as indicated by 1204, using the overall average value as a threshold value. The G and B data are similarly converted. For example, when each pixel value of R is expressed by 8 bits, by performing such conversion, 8 bits × 2 = 16 bits for two representative values and 16 bits for allocation of each pixel, and 32 after compression It can be expressed in bits. Since it was 8 bits × 16 = 128 bits before compression, it is compressed to ¼. At the time of expansion, the value of 0 or 1 of each pixel is replaced with a representative value as indicated by 1205. By doing so, compression is performed in BTC. By increasing the number of representative values, the image quality after decompression is improved, but the compression rate is lowered.

  There are two such methods for general still image compression algorithms. In general, a compression method that combines orthogonal transform and entropy code is suitable for a display image that has few edges and the display image changes gently. BTC is suitable for images with a small number of colors.

<Embodiment 1>
Next, the first embodiment will be described in detail. FIG. 1 is a block diagram of a display device according to Embodiment 1 of the present invention. Reference numeral 100 denotes a display device such as a mobile phone, 101 denotes a display device driving circuit such as a liquid crystal driver, 102 denotes a CPU (central processing unit) that controls the entire display device such as a mobile phone, 103 denotes a memory that stores display data, and the like. Is an internal bus, and 105 is a display panel that is driven by the display device driving circuit 101 to perform display. The display panel may be any display panel such as a liquid crystal panel, organic EL (Electro-Luminescence) panel, PDP (Plasma Display Panel), FED (Field Emission Display), and electronic paper.

  An input / output interface circuit 106 includes a register group (not shown) for setting various modes by the CPU 102 and receives display data from the CPU 102 and the memory 103. Reference numeral 107 denotes one register in a register group provided in the input / output interface circuit, and is a compression ratio setting register for setting a display data compression ratio used in a display data compression circuit described below. Reference numeral 108 denotes an input buffer. In general, display data is transferred from the CPU in units of one line in the horizontal direction, but since orthogonal transformation is performed in units of blocks such as 4 × 4, 8 × 8, and 16 × 16, 4 × 2 rows , An input buffer for storing 8 × 2 rows or 16 × 2 rows is required. Reference numeral 109 denotes a display data compression circuit. The display data is compressed in this block, and the compressed data is written into the frame memory 110.

  A display data decompression circuit 111 decompresses the compressed display data read from the frame memory and transfers it to the output buffer 112. Normally, the data expansion unit is a block unit such as 4 × 4 pixels, 8 × 8 pixels, 16 × 16 pixels, etc., which are orthogonal transform units, so that the output buffer 112 waits to store one line. The data is output to a DA (digital / analog) converter 113 and output on the display panel 105. Here, in the case of a control device driving device for a panel that controls with an analog voltage such as a liquid crystal panel, the DA converter 113 is used. Since the DA converter 113 changes depending on the driving method of the display panel 105, it may be a block having a circuit function for converting the digital value of the display pixel into a method capable of driving the display panel. The circuit block of the DA converter 113 has other functions. Even if the circuit block is changed, the present invention is not affected at all.

  Next, the circuit configuration in the display data compression circuit 109 will be described in detail with reference to FIG. The display data compression circuit 109 in FIG. 3 is a compression method using orthogonal transformation and entropy coding. The color space transformation circuit 201, orthogonal transformation circuit 202, quantization circuit 203, entropy coding circuit 204, and memory write control circuit 205 are used. Is the same as the circuit shown in FIG. The display data compression circuit 109 has a code length predictor 301, a target code length determination circuit 302, and a quantization coefficient determination circuit 303, as compared with the compression circuit shown in FIG. The target code length determination circuit 302 is a circuit that multiplies (1-set value of the compression rate setting register 107) by the data amount before compression for one block, and calculates the code length for one block as a target. . The code length predictor 301 calculates a code length for one block after entropy coding for each quantized coefficient when the data after orthogonal transformation is divided by a plurality of predetermined quantized coefficients. It is. The quantization coefficient determination circuit 303 selects a code length corresponding to the minimum quantization coefficient from among the code lengths that do not exceed the target code length that is the output of the target code length determination circuit 302 from the output of the code length predictor 301 And a circuit for outputting the quantization coefficient. The quantization circuit 203 divides the quantization coefficient determined by the quantization coefficient determination circuit 303 and performs quantization. The quantized coefficients are generally stored in memory along with the entropy code.

  By configuring the compression circuit in this manner, display data can be compressed at the compression rate set by the compression rate setting register.

  Next, the circuit configuration in the display data decompression circuit 111 will be described in detail with reference to FIG. The memory read control unit 401 multiplies (1-set value of the compression rate setting register 107) by the data amount before compression for one block to calculate the code length for one block, and displays the data for one block. The data of the code length calculated for decoding is read out. Next, the inverse entropy encoding circuit 402 converts the entropy code into fixed-length numerical data, and the inverse quantization circuit 403 multiplies the numerical data output from the inverse entropy encoding circuit 402 by a quantization coefficient to perform inverse quantization. . The inverse orthogonal transform circuit 404 multiplies the inverse matrix of the orthogonal matrix, and the inverse color space conversion circuit 405 converts the data compression color space to the RGB color space. With such a configuration, it is possible to expand the display data compressed at the compression rate set by the compression rate setting register.

  By adopting such a configuration, in the first embodiment, data can be written into the memory at a compression rate corresponding to the compression rate set by the CPU. For example, when displaying an image having gentle characteristics, such as an image taken with a digital camera, on the display panel 105, the CPU increases the compression rate by setting the value of the compression rate setting register 107 large, and the frame memory Reduce the amount of data to be written to and reduce power consumption. In addition, when displaying a moving image such as a video camera image, the image quality degradation is not noticeable for the moving image. Therefore, by setting the compression rate setting register 107 to a large value, the compression rate is increased and data to be written to the frame memory is displayed. Reduce the amount and power consumption.

  Conversely, when displaying an image with many fine edges, such as a UI image, on the display panel 105, the value of the compression rate setting register 107 is set small, and the amount of data written to the frame memory is increased. This prevents image quality degradation and keeps the image quality after decompression above a certain level.

  This compression rate setting register need not be given numerically. For example, the compression rate is limited to a plurality of fixed values. For example, one of them may be a UI mode, the other one may be a moving image, and a natural image mode.

<Embodiment 2>
Next, the second embodiment will be described with reference to FIG. 5, FIG. 6, FIG. 7, and FIG.

  The second embodiment is greatly different from the first embodiment in that the display area is divided into a plurality of areas and the compression rate can be changed for each area.

  In general, a display screen 501 of a mobile phone or the like is divided into a natural image standby screen 503 and UI (user interface) image display areas 502 and 504 in which time, various icons and the like are arranged as shown in FIG.

  FIG. 6 is a block diagram of the display device according to the second embodiment. The display device 100 according to the second embodiment has a display area setting register 603, and a first area compression ratio setting register 601 and a second area compression ratio setting that can set the compression ratio for each area in the compression ratio setting register 107. Having the register 602 is different from the block diagram of the display device 100 of Embodiment 1. The display area setting register 603 includes a first area upper left X coordinate setting register 604, a first area upper left Y coordinate setting register 605, a first area lower right X coordinate setting register 606, and a first area lower right Y coordinate setting register 607. The first area and the other display area (second area) can be set.

  FIG. 7 is a detailed block diagram of the data compression circuit of the second embodiment. Reference numerals 701 and 702 denote counters, which respectively indicate the X coordinate and Y coordinate of the display position of the display data currently being compressed. The counters 701 and 702 are reset by a frame start signal generated by the timing generation circuit 608, and the counter 701 is counted up by the size of the block in the X direction every time one block is compressed. Each time the processing for one line is completed, the counter 702 is incremented by the size in the Y direction. Reference numeral 703 denotes a comparator, the count value of 701 is equal to or higher than the first area upper left X coordinate setting register 604, the first area lower right X coordinate setting register 606 is equal to or lower, and the count value of 702 is equal to the first area upper left Y coordinate setting register. In the case of 605 or more and the first area lower right Y coordinate setting register 607, a first area signal indicating that the area is the first area is output, and a second area signal is output otherwise. When the output of the comparator 703 is the first region signal, the selector 704 outputs the value of the first region compression ratio setting register 601 to the target code length determination circuit 302, and the output of the comparator 703 is the second region signal. Outputs the value of the second area compression rate setting register 602 to the target code length determination circuit 302.

  FIG. 8 is a detailed block diagram of the data decompression circuit according to the third embodiment. Reference numerals 801 and 802 are counters, and 803 is a comparator. The count value of 801 is equal to or higher than the first area upper left X coordinate setting register 604, the first area lower right X coordinate setting register 606 is lower, and the count value of 802 is In the case of the first area upper left Y coordinate setting register 605 or more and the first area lower right Y coordinate setting register 607, the first area signal indicating the first area is output, and otherwise the second area signal is output. Is output. The selector 804 outputs the value of the first area compression ratio setting register 601 to the memory read control circuit 401 when the output of the comparator 803 is the first area signal, and when the output of the comparator 803 is the second area signal. The value of the second area compression rate setting register 602 is output to the memory read control circuit 401. As a result, even if the compression rate changes in the middle of the frame, the amount of data corresponding to the compression rate can be read and can be correctly decompressed.

  In FIG. 5, the area 503 is the first area, the upper left coordinates and the lower right coordinates of the area 503 are set in the display area setting register 603, and the first area compression rate setting register 601 is a natural image and is relatively high. By setting a compression rate and setting a relatively low compression rate in the second region compression rate setting register 602 because it is a UI image, it is possible to maintain an image quality after decompression above a certain level in all regions, Further, since the compression rate can be increased for the region 503, power consumption can be reduced.

<Embodiment 3>
Next, a third embodiment will be described with reference to FIG.

  The third embodiment is greatly different from the first and second embodiments in that a display data compression circuit 901 is provided in the CPU 102.

  The display data compression circuit 901 is functionally the same circuit as the display data compression circuit 107 of the first embodiment. The display image is compressed according to the set value of the compression rate setting register 902 in the CPU 102 and transferred to the display device drive circuit 101 via the internal bus 104. The display data may be sent directly from the CPU 102 to the display device driving circuit 101 or may be sent from the memory 103 to the display device driving circuit 101 after storing the compressed data from the CPU 102 to the memory 103. The CPU 102 sets the value set in the compression rate setting register 902 at the time of compression to the compression rate setting register 107 in the display device driving circuit 101 at the time of display. Thus, by providing a compression circuit on the CPU side and transferring compressed data, the number of switching of the internal bus can be greatly reduced, and power consumption can be reduced. In addition, since the bus use time can be shortened, there is an advantage that the surplus time can be allocated to the data tradition of other functions such as a touch panel.

<Embodiment 4>
Next, the fourth embodiment will be described with reference to FIG. 10, FIG. 13, and FIG.

  The fourth embodiment is greatly different from the first embodiment, the second embodiment, and the third embodiment in that the compression method can be switched depending on the display image, and the image after the display data is expanded. The compression ratio of the image can be automatically switched according to the degree of deterioration.

  10, reference numeral 1001 denotes a compression mode switching register in the area 2 (area 502 and area 504) shown in FIG. In an image having a large number of UI images, such as region 2, the image quality after decompression may be better in the BTC method than in a combination of orthogonal transform and entropy code, such as when the number of colors is small. By setting the BTC mode in the compression mode switching register 1001 according to the design of the display image, the BTC method can be selected as the compression method for the region 2.

  FIGS. 13 and 14 show detailed block diagrams of the display data compression circuit 109 and the display data decompression circuit 111 according to the fourth embodiment.

  In FIG. 13, reference numeral 1301 denotes a BTC compression circuit having a circuit block function shown in FIG. The orthogonal transform compression circuit 1302 is a circuit that performs compression by a combination of orthogonal transform and entropy code, and is the same circuit except that the display data compression circuit 109 of the second embodiment has an automatic compression ratio function. .

  In FIG. 13, when the region determination circuit 703 outputs the second region signal and the BTC mode is set in the compression mode switching register 1001, the AND circuit 1303 outputs the BTC mode. When the region determination circuit 703 outputs the second region signal or when the BTC mode is not set in the compression mode switching register 1001, the AND circuit 1303 enters the non-BTC mode. The selector 1304 outputs the output of the BTC compression circuit 1301 when the AND circuit 1303 is in the BTC mode. When the AND circuit 1303 is in the non-BTC mode, the output of the orthogonal transform compression circuit 1302 is output. By operating in this way, the second area can be compressed by the BTC method.

  Reference numeral 1305 denotes a quantization coefficient average value calculation circuit. In general, when a data compression method using a combination of orthogonal transform and entropy coding is used, the larger the quantization coefficient, the larger the error between the original data and the decompressed data, resulting in image quality degradation. It is considered that as the average value of the quantization coefficient calculated by the quantization coefficient average value calculation circuit 1305 is larger, the image quality after the expansion of the display data is deteriorated. Therefore, when the average value of the quantization coefficient calculated by the quantization coefficient average value calculation circuit 1305 is larger than a certain value, the certain value is subtracted from the setting value of the compression rate setting register 601 in the region 1 and the retransmission request status register 1002 is obtained. Display data resend request. By doing so, it is possible to reduce the compression rate by a certain amount and re-compress the display data that has been transferred again, thereby automatically maintaining a certain image quality.

  Conversely, when the average value of the quantized coefficients calculated by the quantized coefficient average value calculating circuit 1305 is smaller than a certain value, it is considered that a certain level of image quality can be maintained even after further compression. Therefore, when the average value of the quantized coefficients calculated by the quantized coefficient average value calculating circuit 1305 is smaller than a fixed value, the fixed value is added to the set value of the compression rate setting register 601 in the area 1, and the retransmission request status register 1002 Display data resend request. By doing so, the display data transferred again can be recompressed by increasing the compression rate by a certain amount, and the power consumption required for reading from the frame memory can be reduced.

  In FIG. 14, reference numeral 1401 denotes a BTC type expansion circuit, which has a function of generating expansion data 1205 from the representative values 1202 and 1203 and the pixel value 1204 shown in FIG. The orthogonal transform expansion circuit 1402 is a circuit that performs compression by a combination of orthogonal transform and entropy code, and is the same circuit as the display data expansion circuit 111 of the second embodiment.

  In general, in the case of still image display, the number of times of reading is much larger than the number of times of writing, so even if the CPU retransmits several times, the power consumption is not seriously affected. In this way, power consumption can be controlled to a minimum while automatically maintaining a constant image quality.

  In the case of a moving image, the CPU does not retransmit but sends the display data of the next frame, so that the compression changed according to the average value of the quantization coefficient calculated by the quantization coefficient average value calculation circuit 1305 of the previous frame The rate can be used as the compression rate for the next frame. Since the correlation between frames is large in moving images, the power consumption can be controlled to the minimum while automatically maintaining a constant image quality by controlling the compression rate in this way.

  Although the invention made by the inventor of the present application has been specifically described above, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention.

  The present invention can be applied to a display device and a display device driving circuit such as a liquid crystal display such as a mobile phone and a portable game machine, and an organic EL display.

It is a figure which shows the block configuration of the display apparatus in Embodiment 1 of this invention. It is a figure which shows the block configuration of a general display data compression circuit. It is a figure which shows the block configuration of the display data compression circuit in Embodiment 1 of this invention. It is a figure which shows the block configuration of the display data expansion circuit in Embodiment 1 of this invention. It is a figure which shows the display area division | segmentation image in the display apparatus in Embodiment 2 of this invention. It is a figure which shows the block configuration of the display apparatus in Embodiment 2 of this invention. It is a figure which shows the block configuration of the display data compression circuit in Embodiment 2 of this invention. It is a figure which shows the block configuration of the display data expansion circuit in Embodiment 2 of this invention. It is a figure which shows the block configuration of the display apparatus in Embodiment 3 of this invention. It is a figure which shows the block configuration of the display apparatus in Embodiment 4 of this invention. It is a figure which shows the detailed block structure of the BTC compression system circuit in Embodiment 4 of this invention. It is a figure which shows the concept of the BTC compression algorithm of the BTC compression system circuit in Embodiment 4 of this invention. It is a figure which shows the block configuration of the display data compression circuit in Embodiment 4 of this invention. It is a figure which shows the block configuration of the display data expansion circuit in Embodiment 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Display apparatus 101 Display apparatus drive circuit 102 CPU
DESCRIPTION OF SYMBOLS 103 Memory 104 Internal bus 105 Display panel 106 Input / output I / F circuit 107 Compression rate setting register 108 Input buffer 109 Display data compression circuit 110 Frame memory 111 Display data expansion circuit 112 Output buffer 113 DA converter 201 Color space conversion circuit 202 Orthogonal conversion Circuit 203 Quantization circuit 204 Entropy encoding circuit 205 Memory write control circuit 301 Code length predictor circuit 302 Target code length determination circuit 302 Quantization coefficient determination circuit 401 Memory read control circuit 402 Inverse entropy encoding circuit 403 Inverse quantization circuit 404 Inverse orthogonal transformation circuit 405 Inverse color space transformation circuit 501 Display image of display device 502 User interface image display area 503 Natural image display area 504 User interface image display area Area 601 First area compression ratio setting register 602 Second area compression ratio setting register 603 Display area setting register 604 First area upper left X coordinate setting register 605 First area upper left Y coordinate setting register 606 First area lower right X coordinate setting register 607 First area lower right Y coordinate setting register 608 Timing generation circuit 701 X coordinate counter 702 Y coordinate counter 703 Area determination circuit 704 Selector 801 X coordinate counter 802 Y coordinate counter 803 Area determination circuit 804 Selector 901 Display data compression circuit 902 Compression rate Setting register 1001 Compression mode switching register 1002 Retransmission request status register 1101 Blocking circuit 1102 Representative value extraction circuit 1103 Pixel allocation circuit 1201 R pixel values 1202 and 120 before compression 3 Representative value 1204 R pixel value compressed to 1 bit 1205 R pixel value after decompression 1301 BTC system compression circuit 1302 Orthogonal transformation compression circuit 1303 AND circuit 1304 Selector 1305 Quantization coefficient average value calculation circuit 1401 BTC system expansion circuit 1402 Orthogonal transformation expansion circuit 1403 AND circuit 1404 selector

Claims (5)

A display data compression circuit capable of reducing the data amount of the display data by compressing the display data of the image;
A recording circuit capable of storing display data compressed by the display data compression circuit;
A display data expansion circuit for expanding the display data read from the recording circuit;
An output circuit capable of outputting the display data expanded by the display data expansion circuit to a display unit, and a display device driving circuit comprising:
The display device driving circuit includes a compression rate setting circuit that enables a compression rate of the display data to be set, and the display data compression circuit compresses the display data according to a compression rate set in the compression rate setting circuit. A display device driving circuit including a function of The display device driving circuit includes a display area setting circuit capable of setting a plurality of display areas,
The compression rate setting circuit includes a function capable of setting a compression rate corresponding to the display area,
The display device driving circuit according to claim 1, wherein the display data compression circuit includes a function of compressing the display data by switching a compression rate according to a set value of the display area setting circuit and a display position of the display data. The display device driving circuit includes a compression method setting circuit capable of setting a compression method corresponding to the display area,
The display device driving circuit according to claim 2, wherein the display data compression circuit compresses the display data by switching a compression method according to a set value of the compression method setting circuit and a display position of the display data.   The display device driving circuit includes a step of performing quantization at least with a quantization coefficient in a compression step, and includes a circuit capable of updating a set value of the compression ratio setting circuit according to a magnitude of the quantization coefficient. Item 4. A display device driving circuit according to Item 1. A CPU having a display data compression circuit capable of reducing the data amount of the display data by compressing the display data of the image, a recording circuit capable of storing the compressed display data, and read from the recording circuit A display device drive circuit comprising: a display data decompression circuit for decompressing the display data; and an output circuit capable of outputting the display data decompressed by the display data decompression circuit;
A display unit capable of displaying display data output via the output unit, and a display device comprising:
The CPU includes a compression rate setting circuit capable of setting the compression rate of the display data,
The display data compression circuit includes a function of compressing the display data in accordance with a compression rate set in the compression rate setting circuit,
A display device, wherein display data compressed by the display data compression circuit is transferred to the display data expansion circuit via the recording circuit.

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