JP2000278538A - Device and method for arithmetic encoding/decoding - Google Patents

Abstract

PROBLEM TO BE SOLVED: To turn processing procedure into pipeline and to provide acceleration by selecting any one of read three pieces of probability estimation information, establishing an updating condition, performing addition of a generation probability and fit shift processing operation of an object pixel on the basis of a specified operation result and the shit number of bits, and outputting encoded data. SOLUTION: Since an updated party of an index is defined in two ways by a probability estimation table of reading processing in an arithmetic encoder which performs formation of pipeline, the probability estimation table is changed so that three pieces of information, that is, information on the index and two pieces of information when updating is performed, can be read out of the same index, and three pieces of information, probability estimation information 1, 2 and 3, is enabled to be read from the probability estimation table by the reading processing. Thus, when an operation is performed to β by processing regarding continuing two pixels α and 5, selection of the probability estimation information is enabled by the processing result about α.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an arithmetic encoding / decoding apparatus and method for performing compression / expansion in encoding / decoding of image data.

[0002]

2. Description of the Related Art In recent years, digital copiers, facsimile machines, printers, and the like tend to have higher resolution and higher speed, and a system for storing a large amount of image data and processing at high speed is indispensable. . In such a system, an apparatus for encoding / decoding image data is employed. Among them, a JBIG arithmetic encoding / decoding apparatus has been receiving attention.

[0003] JBIG is the name of the joint research organization of the new binary image coding system of ISO and ITU-T, Joint Bi
-level Image coding experts Group is an acronym for JBIG, which is a binary image compression / decompression method recommended as an international standard by this work group.
It is the most efficient compression method among international standards. JB
The basic system of the IG is a typical prediction process of comparing pixel values of successive horizontal lines in image data, as shown in FIG. It includes a model template process for extracting peripheral pixel values, and an arithmetic encoding process for outputting code data using the target pixel value and the peripheral pixel values.

Among these, the arithmetic coding process has a function of predicting a target pixel from peripheral pixel values, and has a high compression ratio. However, since each pixel is processed sequentially, a high speed operation is required. Hindered. FIG. 2 shows a configuration of a conventional arithmetic coding processing device. Arithmetic coding is generally performed using the following (1) to
It is executed according to the processing procedure of (6). The numbers of the processing procedures correspond to the numbers shown in FIG.

In the arithmetic coding process, A [16 bits] and C [32 bits] are used to hold the value being calculated.
Are used. (1) Target pixel value [1 bit] and peripheral pixel value [10 bi]
t]. (2) Based on the peripheral pixel values, read the predicted value [1 bit] of the target pixel and the index [7 bit] of the probability estimation information from the state transition memory.

(3) The probability estimation information is read from the probability estimation table based on the probability estimation information index. The probability estimation information includes the occurrence probability [15 bits] of the pixel value having a low occurrence probability, and the update index [7] when the prediction value and the target pixel are the same.
bit], an update index [7 bit] when the predicted value differs from the target pixel, and a flag [1 bit] for changing the predicted value.

(4) An operation is performed using the target pixel value, predicted value, probability estimation information, register A and register C.
That is, 16-bit subtraction, 32-bit addition, 16b
It compares it, performs bit shift processing, and updates registers A and C. (5) Based on the result of (4), the predicted value and the probability estimation information index of (2) are updated. The information to be updated is included in the probability information of (3).

(6) Code data is output. FIG. 3 shows a configuration of a conventional arithmetic decoding processing device. FIG.
The conventional arithmetic decoding is generally executed in the following processing procedure. (1) to (6) shown in FIG.
Indicates processing units of the following processing procedures (1) to (6). In the arithmetic decoding process, A [16 bit], C _H [16 bit], C
Three registers of _L [16 bits] are used. In the arithmetic decoding process, two registers C _H and C _L are required because the upper 16 bits of the value of the register C are treated as C _H and the lower 16 bits are treated as C _L for convenience of calculation.

(1) Code data and peripheral pixel value [1bi
t]. (2) Based on the peripheral pixel values, read the predicted value [1 bit] of the target pixel and the index [7 bit] of the probability estimation information from the state transition memory. (3) Read the probability estimation information from the probability estimation table based on the probability estimation information index. The read probability estimation information has the same contents as at the time of encoding.

[0010] (4) the code data, the predicted value, probability estimation information, registers A, the register C _H, is calculated by using the register C _L. That is, subtraction of 16 bits, comparison of 16 bits, bit shift processing, and updating of registers A, C _H , and C _L are performed. (5) The predicted value and the probability estimation information index of (2) are updated based on the result of (4). The information to be updated is included in the probability information of (3).

(6) A pixel value [1 bit] is output.

[0012]

SUMMARY OF THE INVENTION The above-mentioned conventional JBI
It is said that it is difficult for the arithmetic coding unit and the arithmetic decoding unit of G to perform high-speed processing by simple pipelining. The main reason is that the predicted value in the processing procedure (5),
This is because if the update processing is not completed to update the probability estimation information index, the information determined in the processing of the processing procedure (2) cannot be read out, and the pipeline, which is a general technique for speeding up, cannot be performed.

Further, the processing procedure (2) is performed by any method.
Even when (5) can be pipelined, the processing time of the processing unit in the processing procedure (4) is long, and to further increase the speed, it is necessary to pipeline the inside of the processing unit. In this case, in the case of the arithmetic coding unit, the operations of the registers A and C are almost independent, and the operation of the register A and the operation of the register C can be relatively easily pipelined. in parts, the register a, a register C _H, the information of the register C _L is required at the same time, pipelined is difficult.

[0014] The present invention solves such a problem and provides a JB.
An object of the present invention is to provide a configuration in which the above-described processing procedures (2) to (5) are pipelined and a pipelined method in order to speed up the arithmetic coding / decoding device in the IG. Another object of the present invention is to provide a configuration in which an arithmetic unit for performing the above-described processing procedure (4) is pipelined, and a method for the pipeline.

[0015]

According to the first aspect of the present invention,
An arithmetic coding device for JBIG processing, wherein, when a target pixel value and a peripheral pixel value are input, a prediction value and a probability estimation information index of the target pixel from a state transition memory based on the input peripheral pixel values. Means for reading the
A probability estimation table in which three pieces of probability estimation information, that is, probability estimation information before update (1) and two pieces of probability estimation information (2) and (3) when updated, are stored; Is given, three pieces of probability estimation information (1), (2), and (3) are obtained from the table.
Means for subtracting the occurrence probability of the target pixel and performing a bit shift processing operation, and selecting any one of the read three pieces of probability estimation information (1), (2), and (3). Means for determining an update condition, and means for performing an addition of a probability of occurrence of a target pixel and a bit shift processing operation based on the operation result and the number of bit shifts, and outputting encoded data. It is assumed that.

According to a second aspect of the present invention, there is provided an arithmetic decoding apparatus for JBIG processing, wherein when code data of a target pixel and peripheral pixel values are input, a state is determined based on the input peripheral pixel values. Means for reading the predicted value and the probability estimation information index of the target pixel from the transition memory, three probability estimation information (1) before update, and two probability estimation information (2) and (3) when updated Means for reading out three pieces of probability estimation information (1), (2), and (3) from the table in response to being provided with the probability estimation information index, the probability estimation table having estimation information stored therein; , The three pieces of probability estimation information (1),
Means for selecting any one of (2) and (3) and subtracting the current occurrence probability of the target pixel and performing a bit shift processing operation, and based on the calculation result and the number of bit shifts, Means for performing the addition of the occurrence probability of the target pixel and performing the bit shift processing operation, and outputting the encoded data as pixel data.

According to a third aspect of the present invention, there is provided an arithmetic coding / decoding apparatus including the arithmetic coding apparatus according to the first aspect and the arithmetic decoding apparatus according to the second aspect. According to a fourth aspect of the present invention, the step 0 for reading the predicted value and the probability estimation information index of the target pixel from the state transition memory based on the input peripheral pixel value, and the probability estimation information before updating (1) are updated. From the probability estimation table in which the two pieces of probability estimation information (2) and (3) in the case where are stored, based on the probability estimation information index given by the process of step 0,
Step 1 for reading the three pieces of probability estimation information (1), (2), and (3), and subtraction and bit shift processing of the occurrence probability of the target pixel, and the read three pieces of probability estimation information (1) , (2), and (3) are selected, and the update condition is determined. Based on the subtraction result of step 2 and the number of bit shifts, addition of the occurrence probability of the target pixel and bit Performing a shift processing operation and outputting encoded data; and
3 is an arithmetic coding processing method characterized by being pipelined so as to sequentially perform serial operation based on an operation clock.

According to a fifth aspect of the present invention, there is provided a step 0 for reading a predicted value and a probability estimation information index of a target pixel from a state transition memory based on an inputted peripheral pixel value.
From the probability estimation table in which the probability estimation information before update (1) and the two pieces of probability estimation information (2) and (3) when updated are stored, the probability estimation information given by the process of step 0 Step 1 for reading out the three pieces of probability estimation information (1), (2), and (3) based on the index, and three pieces of probability estimation information read out based on the calculation result performed on the previous target pixel (1), (2),
Step 2 of selecting one of (3) and subtracting the occurrence probability of the current target pixel and performing a bit shift process;
A step of adding the occurrence probability of the current target pixel and performing a bit shift operation on the basis of the subtraction result of step 2 and the number of bit shifts to output encoded data as pixel data; An arithmetic decoding method is characterized in that steps 0 to 3 are pipelined so as to sequentially perform a serial operation based on an operation clock.

According to each of the above-described configurations, since the processing can be executed independently in steps 0 to 3, the four stages of steps 0 to 3 can be pipelined. As a result, the processing speed can be increased.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing a configuration of a pipelined arithmetic coding device according to an embodiment of the present invention. In the prior art, as described with reference to FIG.
In (5), high-speed processing cannot be realized by simple pipelining. This means that, for two consecutive pixels α and β, if all the surrounding pixels have the same value, the predicted value of the process (2) and the probability estimation information index for β until the process (5) is completed for α. Cannot be determined.

However, looking at β, the actually necessary information is the predicted value and the probability estimation information used in the process (4), and the information of the processes (2) and (3) has not been determined for β. However, if the probability estimation information determined from the predicted value and the probability estimation information index updated in the process (5) of α can be obtained by the process (4) of β, the pipeline can be realized.

Therefore, in this embodiment, attention is paid to the fact that the update destination of the index is limited to two types by the probability estimation table of the process (3). The probability estimation table has been changed so that a total of three pieces of information can be read from one index. More specifically, S in FIG.
In AGE1, in the process of reading from the probability estimation table, probability estimation information 1, probability estimation information 2, probability estimation information 3
Three types of information can be read.

As a result, when the operation is performed on the β in the process (4), the probability estimation information can be selected from the result of the process (4) on the α (see the shaded portion in FIG. 4). Next, a description will be given of a pipeline of the operation unit that performs the above process (4). FIG. 5 shows an operation flow of the conventional arithmetic coding device. FIG. 6 shows a calculation flow of the arithmetic coding device according to this embodiment.

As shown in FIG. 5, in the operation flow of the conventional arithmetic coding device, the value of the register C is not involved in the condition comparison. Therefore, the operation of the register A and the operation of the register C can be separated as in the operation flow shown in FIG.
At that time, when the register C is normalized, the shift number of A at the time of the normalization of the register A is required, the subtraction result of the register A and the occurrence probability when updating the register C, and the necessary flag when updating the register A are required. Become.

Taking this into consideration, the STAGE of FIG.
As shown by 2 and 3, the operation unit is pipelined. In other words, focusing on the fact that all the conditions necessary for updating are prepared by 16-bit subtraction and 16-bit comparison, the subtraction and comparison and 32-bit addition are pipelined to shorten the critical path. .

As a result, the configuration of the arithmetic coding circuit is S
It is pipelined so as to include four stages TAG0 to TAG3. FIG. 7 is a block diagram showing a configuration of a pipelined arithmetic decoding device according to an embodiment of the present invention. The arithmetic decoding device in FIG. 7 also has STAGEs 0 to 3 as in the arithmetic coding device shown in FIG.
A pipeline including three stages has been realized.

Next, the operation unit (S) in the device shown in FIG.
TAG2, 3) will be described in detail. FIG. 8 is a flowchart of the arithmetic unit of the arithmetic decoding device when the pipeline is not performed, and FIG. 9 is a flowchart illustrating the arithmetic unit of the arithmetic decoding device when the pipeline is performed.

As shown in FIG. 8, in the operation unit flow, there is a comparison condition of C _H <A involving both the values of the register A and the register C _H (step in the second stage). Thus, the register A in one cycle, the calculation of C _H, not complete the normalization can not perform the following operations. That is, the register A, the calculation of the C _H is unable pipeline.

[0029] Therefore, in this embodiment adopts a technique that can determine without using the value of register C _H made the condition comparison interfere with pipelined directly. This technique will be described below. FIG. 10 shows a change example of each value at the time of calculation. As shown in FIG. 10, the change of the register C _H at the time of the calculation is limited only at the time of normalization, as shown in FIG.
→ There are two ways: (5).

First, the state changes from (2) to (3) in FIG.
Think about the case. In FIG. 11, the upper part of the interval
5 shows a conventional condition determination method when selected. In FIG.
As shown, in the conventional condition determination, the selected interface
Bal (shaded area) and C_H0-(A₀-LSZ₀) Is choice
Interval size (LSZ ₀) Is 8000H
Shift both values to the left until₁, C_H1Normalized to
And then compare the conditions.

On the other hand, in this embodiment, as shown in FIG. 12, the above-described normalization is not performed, and LSZ ₁ is shifted rightward by the number to be originally normalized, so that it can be compared with A ₀ and C _H0. performing alignment shift (with respect to the condition comparison, a, but using the normalized values of C _H, a, performs conventional normalization with respect to updating of the C _H). The formula LSZ ₁ ′ shown in FIG.
= LSZ ₁ >> ACT indicates that the register A is shifted rightward by the shift number ACT at the time of normalization.

The comparison formula does not use C _H as a reference, but LSZ (LS
Z is an estimate of the normal probability of LPS. LPS is based on the symbol that appears less frequently among the symbols to be coded, and A ₀ −C _H0 > LSZ ₁ ′ (based on CH, the right shift of LSZ is The calculation of A ₀ −LSZ ₁ ′ cannot be executed unless it is terminated.) If the comparison formula A ₀ −C _H0 > LSZ ₁ ′ is used, A and C _H one cycle before are used. Therefore, even if the update of C _H is delayed by one cycle due to the pipeline, the operation can be performed without any problem.

However, in this method, information to be compared is lost by shifting the LSZ to the right. Information to be added from the C _L Normalization also in the value of the C _H is missing. Due to the lack of such information, the comparison formula A ₀ −C _H0 > LSZ ₁ ′ alone cannot substitute for C _H <A in FIG.

Therefore, in order to make up for this lack of information,
The compared information is further compared. C _HMissing information
Is the comparison formula A₀-C_H0> LSZ₁’, A₀Difference from
Since the information is divided, to secure the difference, the comparison formula
A₀-C_H0-1> LSZ₁’. FIG.
Show the condition judgment method and conditional expression for the part where information is missing
I have.

Referring to FIG. 13, a method of comparing missing information when ATC = 3 will be described. The missing information is LSZ ₁ [2: 0] and C _L [15: 1, respectively.
3] (the notation of X [a: b] indicates the value of bits a to b of X). The value of C _L [15:13] is A
Since the difference is calculated from the value secured from ₀ , NOT (C
_L [15:13]) + 1B, and the comparison expression finally becomes N
_{OT (C L [15:13]>} = LSZ 1 [2: 0]) become (is NOT an inverted sign).

This comparison equation is: A ₀ −C _H0 −1> LS
Since it is independent of Z ₁ ′, processing can be performed in parallel. By using these comparison expressions as in the flow of the operation unit in FIG. 9, the operations of the registers A and C can be separated, and the pipeline can be realized. Also in the case of the normalization of (4) → (5) in FIG. 10, the parallel processing operation can be performed by almost the same method.

More specifically, FIG. 14 shows a conventional condition determination method when the lower side of the interval is selected, and FIG. 15 shows the condition determination in this embodiment when the lower side of the interval is selected. This shows the method. The description of FIG. 14 is substantially the same as the description of FIG. 11, and thus description thereof will be omitted.

In FIG. 15, A ₀ -LSZ _{0 is used} as a comparison equation.
Performing a calculation using the -C _H0 -1> LSZ ₁ '. The other processing for condition determination is the same as the method described with reference to FIG. In order to realize the above-described manner as a hardware configuration, a circuit portion 10 indicated by hatching shown in FIG. 7 is added.

In the circuit portion 10 of FIG. 7, the "interval maximum value" is replaced by (2) → (3) or (4) →
The value of A, A-LSZ depending on the case (5) is held. The present invention is not limited to the embodiments described above, and various modifications can be made within the scope of the claims.

[0040]

In the arithmetic coding device and / or the arithmetic decoding device, data can be processed at a high speed because the pipeline can be formed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic system configuration of JBIG.

FIG. 2 is a block diagram illustrating a configuration of an arithmetic coding device that does not perform pipelining.

FIG. 3 is a block diagram illustrating a configuration of an arithmetic decoding device that does not perform pipelining.

FIG. 4 is a block diagram showing a configuration of a pipelined arithmetic coding device according to an embodiment of the present invention;

FIG. 5 is a flowchart of an operation unit of the arithmetic coding device that does not perform pipelining.

FIG. 6 is a flowchart of an operation unit of the arithmetic coding device that has been pipelined according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a pipelined arithmetic decoding device according to an embodiment of the present invention.

FIG. 8 is a flowchart of the operation unit of the arithmetic decoding device that does not perform pipeline processing.

FIG. 9 is a flowchart of an operation unit of the arithmetic decoding device that has performed pipeline processing according to an embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of a change in each value during an operation in arithmetic decoding.

FIG. 11 is a diagram for explaining a method of determining conditions according to a conventional method when an upper side of an interval is selected.

FIG. 12 is a diagram for explaining how to determine conditions in one embodiment of the present invention when the upper side of the interval is selected.

FIG. 13 is a diagram showing a condition determination method and a conditional expression for a portion where information is missing according to an embodiment of the present invention.

FIG. 14 is a diagram for explaining a conventional method of determining conditions when the lower side of an interval is selected.

FIG. 15 is a diagram illustrating a method of determining a condition according to an embodiment of the present invention when the lower side of the interval is selected.

Claims (5)

[Claims] An arithmetic coding device for JBIG processing, comprising: when a target pixel value and a peripheral pixel value are input, a prediction value of the target pixel from a state transition memory based on the input peripheral pixel value; Means for reading the probability estimation information index and the probability estimation information, and the probability estimation information in which three probability estimation information (2) and (3) are stored. A table, and in response to the probability estimation information index being given, three probability estimation information (1), (2), and (3) from the table.
And means for subtracting the occurrence probability of the target pixel and performing a bit shift operation, and selecting any one of the three pieces of read probability estimation information (1), (2), and (3). Means for determining an update condition, and means for performing an addition of a probability of occurrence of a target pixel and a bit shift processing operation based on the operation result and the number of bit shifts, and outputting encoded data. Arithmetic coding apparatus for JBIG. 2. An arithmetic decoding apparatus for JBIG processing, comprising: when code data and a peripheral pixel value of a target pixel are input, a target pixel of the target pixel is read from a state transition memory based on the input peripheral pixel value. Means for reading the predicted value and the probability estimation information index, and three probability estimation information, that is, the probability estimation information before update (1) and two pieces of probability estimation information (2) and (3) when updated are stored. A probability estimating table, and in response to the probability estimating information index being given, three probability estimating information (1), (2), and (3) from the table.
Means for reading the three pieces of probability estimation information (1), (2), and (3) read out based on the result of the previous operation performed on the target pixel.
Means for selecting any one of the following, and performing a subtraction of the current probability of occurrence of the target pixel and a bit shift processing operation; and adding the probability of occurrence of the current target pixel based on the calculation result and the number of bit shifts. And a means for performing a bit shift operation and outputting encoded data as pixel data, and outputting the encoded data as pixel data. 3. The arithmetic coding device according to claim 1, wherein
Arithmetic coding / decoding device provided with the arithmetic decoding device of (1). 4. A step 0 for reading a predicted value and a probability estimation information index of a target pixel from a state transition memory based on an input peripheral pixel value, the probability estimation information before updating (1), From the probability estimation table in which the two pieces of probability estimation information (2) and (3) are stored, based on the probability estimation information index given by the process of step 0, the above three pieces of probability estimation information (1) and (2) , (3) reading step 1
And subtraction of the occurrence probability of the target pixel and bit shift processing, and the read three pieces of probability estimation information (1),
(2) selecting one of (2) and (3) to determine the update condition; and adding the occurrence probability of the target pixel and bit shifting based on the subtraction result of step 2 and the number of bit shifts. Performing a processing operation and outputting encoded data, wherein steps 0 to 3 are pipelined so that serial operations are sequentially performed based on an operation clock. Method. 5. A step 0 for reading a predicted value and a probability estimation information index of a target pixel from a state transition memory based on an input peripheral pixel value, the probability estimation information before update (1), From the probability estimation table in which the two pieces of probability estimation information (2) and (3) are stored, based on the probability estimation information index given by the process of step 0, the above three pieces of probability estimation information (1) and (2) , (3) reading step 1
And three pieces of probability estimation information (1), (2), and (3) read out based on the result of the calculation performed on the previous target pixel.
Step 2 in which one of the following is selected and the current occurrence probability of the target pixel is subtracted and the bit shift process is performed. Based on the subtraction result in Step 2 and the number of bit shifts, the current occurrence probability of the target pixel is selected. And a bit shift processing operation to output encoded data as pixel data and output the pixel data. Steps 0 to 3 are pipelined so that serial operations are sequentially performed based on an operation clock. An arithmetic decoding method comprising: