JP2003198858A - Encoder and decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an encoder capable of implementing highly efficient encoding at a high-speed and producing encoding data capable of being managed as a single encoding data by suppressing the amount of encoding data. <P>SOLUTION: The encoder is provided with two encoding sections 31-A, B for implementing prediction encoding each comprising a prediction section 4, a probability estimation table 6, and an arithmetic encoding section 9, which respectively encode different pixels at an interval of one pixel in parallel. A context generating section 2 is provided in common to each encoding section 31 to generate a context used for prediction from consecutive image data. FIFO memories 32-A, B corresponding to encoded data 10-A, B respectively store the data encoded by the encoding sections 31-A, B by using the context. A composite section 36 controls the FIFO memories 32-A, B to alternately read and output the encoded data basically in the unit of the amount of a prescribed data to obtain composite encoded data 37. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device for image data using a predictive coding system and a decoding device for decoding the coded data.

[0002]

2. Description of the Related Art As one of binary image coding techniques, there is a predictive coding method in which the state of a pixel of interest is predicted from surrounding pixels and the predicted result is coded. In predictive coding, surrounding pixels that are considered to have a correlation with the pixel of interest are used for prediction as Markov information sources.

As a prediction method, a method of directly determining a prediction value and a method of indirectly determining a prediction value are known. As a method for directly determining the predicted value, for example, Japanese Patent Application Laid-Open No. 5-31637.
As disclosed in Japanese Unexamined Patent Publication (Kokai) No. 0, there is a method of adaptively switching a predictor having a high hit rate from a plurality of predictors, finally selecting one predictor, and using it for predicting an original image. . Further, as a method of indirectly determining the predicted value, for example,
There is a method in which information such as a predicted value is stored in a memory, information in the memory is read from peripheral pixel values and used for prediction.

The prediction method disclosed in Japanese Examined Patent Publication No. 6-95645 is a prediction method that indirectly determines a prediction value using a memory of the latter type. Prediction error data is generated using the prediction value output in the up method. But,
The position of all predicted pixels is not fixed, but only one pixel is variable, and the predicted position is changed according to the predictive hit ratio. ITU-TT. 82, T-85
JBIG (Joint Bi-level)
Image coding expert Grou
The prediction method used in p) is the above-mentioned Japanese Patent Publication No. 6-956.
The prediction method is disclosed in Japanese Patent Publication No. 45-45, and a learning method in which information in the prediction table is updated according to the coding state is adopted. Prediction error data, which is the result of predicting the pixel of interest by the above-described prediction method, is used for encoding.

In JBIG, arithmetic coding is adopted as a coding unit for coding prediction error data. In arithmetic coding, for example, as disclosed in Japanese Examined Patent Publication No. 17295/1989, the region on the number line is divided according to the occurrence probability of 1 and 0 of the input symbol, and the region is divided by the value of the input symbol. Select. At this time, the symbol (predominant symbol) that matches the prediction is set to MPS (More Probe).
and a non-matching symbol (recessive symbol) with LPS (Less Probable S).
symbol). The estimated probability of occurrence of MPS and LPS is changed according to the predictive predictive value and the like. JBIG
In the above, the symbol appearance probability estimator has a probability value (= region width LSZ) at the time of LPS occurrence, and a learning function for updating the probability estimate value in accordance with the symbol appearance process. The learning function of probability estimation works in conjunction with the learning function of the prediction value described above. This division selection processing is performed for each output sequence of the information source, and the output sequence is represented by the binary decimal display of one point in the area obtained by the division at the final stage.

FIG. 10 is a conceptual diagram of arithmetic coding. The hatched areas are the effective areas after the symbol coding is completed. In the initial state, the effective area is [0, 1)
It is a section, and a region width LSZ (0) at the time of LPS occurrence is set. 1-LSZ (0) is the region width when MPS occurs. Here, the MPS is when the symbol is “0”,
When it is "1", it is set as LPS. In FIG. 10, the probability values are shown in binary numbers.

In FIG. 10, since the first input symbol is "0", the effective area is shown in FIG.
In 0 (A), it is a hatched area. Then, a new area width LSZ (1) that divides the effective area into areas when LPS occurs and when MPS occurs is set. When the next symbol is "1", the occurrence of LPS causes
The hatched area in (B) is the effective area. Similarly, when the third symbol is “0”, the hatched area in FIG. 10C is the effective area, and when the fourth symbol is “1”, the area shown in FIG.
The hatched area at 0 (D) is the effective area.

The output code is represented by C. The code for the input symbol string “0101” is shown in FIG.
It may be one point in the effective area in (D). Here, the basis of the effective area, that is, the smallest value C (3) of the effective area is represented as a code and output.

In arithmetic coding, in the process of coding,
Since one point in the effective area is used as a code, if the area is made large, the effective digits decrease and the code amount decreases. In other words, by reducing the value of LSZ as much as possible when MPS occurs and increasing the value of LSZ as much as possible when LPS occurs, it is possible to secure a large effective area and reduce the code amount.

FIG. 11 is a schematic diagram of a predictive coding system adopted in JBIG. In the figure, 1 is image data, 2
Is a context generation unit, 3 is a context, 4 is a prediction unit, 5 is a state, 6 is a probability estimation table, and 7 is an LSZ.
And SW, 8 is a prediction value, 9 is an arithmetic coding unit, 10 is code data, 11 is rewriting data, and 12 is a rewriting signal.

The image data 1 is input to the arithmetic coding unit 9 for coding and also to the context generation unit 2. In the context generation unit 2, in order to perform prediction of the pixel of interest, peripheral pixel is used to create a prediction model template. FIG. 12 is an explanatory diagram of an example of a template used in JBIG. When P is the target pixel, a template using the reference pixels X _{9 to} X ₀ shown in FIG. 12 is generated. This reference pixel X _{9 to} X
A value of ₀ becomes a 10-fold Markov information source of 2 ¹⁰ states (context), which is directly input to the prediction unit 4 as context 3 and used for prediction.

The predictor 4 has a reference pixel X₉~ X₀To the value of
The corresponding predicted value 8 and the probability estimation table 6 are referred to.
The prediction table that is paired with state 5 for
There is. Reference pixel X₉~ X₀Context 3 which is the value of
It is directly input as an address in the prediction table and predicted
Any of the 1024 entries in the table is selected
It Prediction table selected by context 3
Predictive value 8 and state 5 from the
The value 8 is input to the arithmetic coding unit 9 and the state 5 is confirmed.
Input into the rate estimation table 6. FIG. 13 shows the prediction unit 4.
It is explanatory drawing of an example of the prediction table memorized. Figure 1
The prediction table shown in 3 corresponds to the address
Value and state are stored as a pair. In addition,
Res is shown in binary, but this is the context
Reference pixel X input as text 3₉~ X₀That of
It corresponds to each pixel value. For example, the reference pixel
X ₀Value of "1" and other reference pixels are "0"
For example, the address "00000001" is referenced and the
The measured value "1" and the state "2" are obtained.

Corresponding to the state 5, the probability estimation table 6 has a region width LSZ at the time of LPS occurrence, a next state value NLPS at the time of LPS occurrence and a next state value NMPS at the time of MPS occurrence, and SW, which is a flag indicating whether to rewrite the predicted value when normalization occurs, is stored. The LSZ and SW7 corresponding to the input state 5 are output to the arithmetic encoding unit 9 and the NM
The PS and NLPS are sent to the prediction unit 4 as a part of the rewrite data 11. FIG. 14 is an explanatory diagram of an example of the probability estimation table 6. In FIG. 14, LSZ, NMPS, NLPS, and SW are stored as a pair corresponding to the number of state 5. For example, when the state is “2”, LSZ is “0x1114”, NLPS is “16”, NMP.
“3” is obtained as S and “0” is obtained as SW. Here, the numerical value starting with "0x" is a hexadecimal number.

The arithmetic coding unit 9 compares the predicted value 8 input from the prediction unit 4 with the image data 1, and if they match, the symbol to be coded is "0", that is, the MPS has occurred. If they do not match, it is assumed that the symbol to be encoded is "1", that is, LPS has occurred. Then, using the LSZ input from the probability estimation table 6, FIG.
The coded data 10 is output by performing the arithmetic coding as outlined in 0. When an LPS occurs, a new prediction value obtained by inverting the prediction value is rewritten only when the SW input from the probability estimation table 6 is capable of rewriting the prediction value (for example, when SW is “1”). As a part of the data 11, the rewriting signal 12 is sent together with sending to the prediction unit 4 to rewrite the predicted value of the prediction table stored in the prediction unit 4.

In JBIG, the arithmetic coding unit 9 adjusts the effective area to be always 0.5 or more and less than 1 so as not to increase the effective digits of the effective area.
This process is called normalization. The value of LSZ is always 0.5
The probability estimation table is configured so that the value is less than. As a result, when LPS occurs, the effective area becomes less than 0.5, and the normalization always occurs. Furthermore, even when MPS occurs, the new effective area is LSZ from the current effective area.
May be less than 0.5 because it is calculated by subtracting
There are cases where normalization occurs. When this normalization occurs, the rewrite signal 12 is sent to the prediction unit 4. The prediction unit 4 writes the NMPS given from the probability estimation table 6 in the prediction table as the state of the context 3 given from the context generation unit 2 when the MPS occurs. Further, when LPS occurs, the NLPS given from the probability estimation table 6 is written in the prediction table as the state of the context 3. After the prediction table is updated in this way, the process for the next image data 1 is started.

The learning type prediction / probability estimation method in which the above-mentioned prediction unit 4 and probability estimation table 6 are sequentially rewritten will be further described using a specific example. FIG. 15 is an explanatory diagram of a specific example of input image data. Figure 15
Then, the image data 1 of the template portion shown in FIG.
Shows only. As shown in FIG. 15, consider a case where the pixel of interest P is 1 when the contexts X _{9 to} X ₀ are “0000000011”. The prediction table and the probability estimation table 6 of the prediction unit 4 are shown in FIGS.
It is assumed that the contents shown in 4 are set.

First, the context "00000001"
1 ”is input to the prediction unit 4 as the context 3. At this time, the address “00000” in the prediction table of the prediction unit 4
As shown in FIG. 13, the predicted value "0" is set to "00011".
And the state value “80” are stored. The state value “80” read from the prediction table is input to the probability estimation table 6. Next, the state number “80” in the probability estimation table 6 is referred to. Since the content shown in FIG. 14 is set in the probability estimation table 6, the LSZ value “0x5832” corresponding to the state number “80” is read out and output to the arithmetic encoding unit 9.

At this time, the value of the pixel of interest P is "1", but the predicted value read from the prediction table of the prediction unit 4 is "0", so it means that LPS has occurred. When LPS occurs, the area corresponding to the LSZ value read from the probability estimation table 6 basically becomes the next effective area. Since LSZ is less than 0.5, 0.5
The normalization is performed so as to be less than 1 and the NLPS value “80” of the state number “80” is overwritten as the state value of the address “0000000011” in the prediction table of the prediction unit 4. Further, since the SW of the state number “80” of the probability estimation table 6 is “1”, the predicted value is inverted to “1” and is overwritten as the predicted value of the address “0000000011” in the prediction table of the prediction unit 4. It FIG. 16 is an explanatory diagram of a specific example of the prediction unit table after rewriting. In this way, as shown in FIG. 16, the prediction value and the state value of the address “0000000011” of the prediction unit are rewritten. Prediction for the next image data 1 is performed using the rewritten prediction unit. When the same context is input next, the predicted value is 1.

In this example, LPS has occurred, but if MPS has occurred, the prediction unit 4 will be used when normalization is performed.
Rewrite the state value of the prediction table of NMPS to “81”. When the same context 3 is input next time after rewriting, the state value is “81”, and L at this time is
From FIG. 14, SZ is “0x4d1c”. This value is
It is smaller than LSZ “0x5832” when the state value is “80”, that is, it means that the probability of occurrence of LPS is small. This is because the prediction at the time of the same context last time was correct, so when the same context is input next time, the area width at the time of occurrence of MPS is expanded, and the effective area can be widened when the prediction is correct again. It is possible to increase the final effective area and reduce the code amount.

As described above, the predictor is sequentially rewritten according to the probability estimation table to improve the predictive predictive value, increase the number of MPS occurrences, and control the area width at the time of MPS / LPS occurrences to perform coding. Improves efficiency.

The processing at the time of decoding is also carried out while performing area division, as in the case of encoding. The difference from encoding is that the prediction value and the pixel of interest are compared during encoding, and the LP
While the S / MPS area is calculated while being calculated, at the time of decoding, which area of the LPS / MPS the code is included in is calculated, and then the pixel of interest is selected from the surrounding decoded reference pixels. Inverse prediction is required.

FIG. 17 is a schematic diagram of the predictive decoding system adopted in JBIG. In the figure, parts similar to those in FIG. 11 are assigned the same reference numerals and explanations thereof are omitted. Reference numeral 21 is an arithmetic decoding unit, 22 is an inverse prediction unit, 23 is an inverse prediction value, and 24 is rewrite data. The context generation unit 2 and the inverse prediction unit 22 operate exactly the same as the context generation unit 2 and the prediction unit 4 at the time of encoding. The inverse prediction unit 22 is the same as the prediction unit 4 at the time of encoding. Naturally, the same probability estimation table 6 as that at the time of encoding must be used.

First, as in the case of encoding, the context is generated by the value of the reference pixel around the pixel of interest of the decoded image data 1, and the inverse prediction unit 22 and the probability estimation table 6 are generated.
Then, the LSZ and the inverse prediction value 23 are output to the arithmetic decoding unit 21.

Next, the coded data 10 is transferred to the arithmetic decoding unit 21.
Inverse prediction value 2 after valid area comparison is performed in
3 is used to output the image data 1. FIG. 18 is an explanatory diagram of the basic operation of the arithmetic decoding unit. First, subtract the LSZ width input from the probability estimation table from the current effective area,
(Effective area-LSZ) is obtained. The MPS area and the LPS area are divided at this value. The next input code C is
It is compared whether or not it is larger than the value of (effective area-LSZ) obtained earlier. That is, it is determined that C> effective area-LSZ. By this comparison determination, it is possible to determine whether the pixel of interest is LPS or MPS, and therefore the level of the pixel of interest is obtained from the input inverse prediction value. That is, MP
If S, the value of the pixel of interest is an inverse prediction value, and if LPS, the inverse prediction value may be inverted to obtain the value of the pixel of interest. The pixel of interest can be basically decoded by the above processing.

However, in order to decode the next pixel, it is necessary to further determine a new effective area, a code-effective area subtraction process, and the like. For example, in the example shown in FIG. 18, since the code data C exists in the LPS area, the LPS area is set as a new effective area, a new LSZ is set, and the above-described processing is repeated. In addition, the prediction value and the state value of the prediction table stored in the prediction unit 4 are rewritten in the same manner as at the time of encoding.

As described above, in JBIG, the learning type prediction method in which rewritable memory is used as the probability estimation table is used for updating, and the arithmetic coding method is used in the entropy coding section. Highly efficient coding of binary images and decoding of coded data can be achieved as compared to conventional run-length coding and the like.

However, in the JBIG system, while highly efficient coding is achieved, there is a problem that the processing becomes slow. The learning type prediction method using the prediction table adopted in JBIG has the advantage of improving the predictive hit ratio because it rewrites the prediction value and state to bring it closer to the optimum state, but at the same time, it takes time to access the memory. In addition, when the prediction table is rewritten, the prediction value cannot be read until after the rewriting is completed, which makes it difficult to increase the speed.

Japanese Patent Application Nos. 8-301889 and 8
No. 288731, there is a method of preliminarily reading a plurality of data from a prediction table or an inverse prediction table at the time of encoding or decoding, and selecting the data according to the encoding result or the decoding result of the current image to increase the speed. Proposed. Further, for example, Japanese Patent Laid-Open No. 8-1
As shown in Japanese Patent No. 54059, a method of speeding up arithmetic coding itself has also been proposed. However, in any case, since the prediction table may be rewritten for each pixel, it is the current situation that a speed-up means such as simultaneously processing a plurality of adjacent pixels cannot be taken.

In order to speed up the encoding process, it is generally conceivable to use a plurality of encoders for parallel processing.
That is, the input image is divided into a plurality of areas and encoded by the corresponding encoders. However, this method cannot handle the case where the input image is transferred from the scanner or the like pixel by pixel from the beginning of the page. For example, when the input image is divided into two and encoded by two encoders,
Pixels in one region are continuously transferred, during which only the encoder corresponding to that one region operates, and then the code corresponding to the other region is started until the transfer of pixels in the other region starts. The vessel cannot work. Therefore, it is not possible to perform processing in parallel, even though a plurality of encoders are provided. Since the images are processed in parallel, it is conceivable that the images are once stored in the memory and then transferred, but there is a problem that the memory amount increases. Also, when outputting in real time to an output device or the like at the time of decompression, it is necessary to temporarily store in the memory.

As another method, as described in US Pat. No. 4,982,292, a method of encoding an input image every other pixel has been proposed. However, this method has a problem in that the context for realizing high-efficiency coding in JBIG is generated every other pixel, and the prediction efficiency is lowered, which affects the coding efficiency.

Further, in any of the above-described methods for increasing the speed, since the codes processed in parallel are separately output, there is a problem that the memory management for holding the codes becomes complicated.

As a method of synthesizing separately generated code data into one, as described in, for example, JP-A-6-38048, a method of inserting an identification code at the beginning of each code data There is. According to this method, the number of codes is one, but if each code data length is increased, an extra memory is required, and if the switching is finely performed, the identification code amount increases. there were.

[0033]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances and is capable of performing high-speed and highly efficient encoding or decoding and suppressing the amount of code data to obtain a single code. It is an object of the present invention to provide an encoding device that generates encoded data that can be managed as data and a decoding device that decodes the encoded data.

[0034]

In order to solve the above problems, the encoding device of the first invention (claim 1) synthesizes code data encoded by a plurality of encoding means by a synthesizing means. In doing so, the coded data output from each encoding means is sequentially output for each predetermined amount. If the coded data is not output from the coding means, the coded data cannot be sequentially output. Therefore, only in that case, the identification code is added and the coded data is output from the other coding means. As a result, the identification code is not output to the composite code data output from the synthesizing means in a normal state, and the identification code is output only in a special case where the code data is not output from the encoding means. It is possible to suppress the total data amount of the combined code data.

Further, in the decoding apparatus of the second invention (claim 2), the synthetic code data obtained by synthesizing the code data obtained by sequentially allocating the input data for each predetermined unit and encoding the divided data is divided. The data is divided by the means and distributed and input to a plurality of decoding means as coded data. When an identifier appears when dividing the synthetic code data into code data, a plurality of code data consecutive to the identifier are continuously input to the same decoding means. Since the identifier is not inserted in the input synthetic code data except when the code data is continuously input to the same decoding means, the data amount of the synthetic code data to be input can be suppressed.

[0036]

1 is a block diagram showing an embodiment of an encoding apparatus according to the present invention. In the figure, FIG.
The same reference numerals are given to the same portions as, and the description thereof will be omitted. Three
1 is an encoding unit, 32 is a FIFO memory, 33 is a memory status signal, 34 is a read signal, 35 is unit code data, 3
6 is a synthesizing unit, and 37 is synthetic code data. Note that FIG.
Shows an example in which two blocks of the encoding unit 31 are provided,
One block is an A block and the other block is a B block, and the configuration related to each block is distinguished by adding A or B after “−”.

Each coding unit 31-A, B comprises a prediction unit 4, a probability estimation table 6, and an arithmetic coding unit 9, and the context generation unit 2 is common to each coding unit 31-A, B. It is provided as a configuration. The image data 1 is input to the context generation unit 2 that is provided in common, and is also input to the arithmetic encoding unit 9 of each encoding unit 31-A, B. The contexts 3-A and B generated by the context generation unit 2 are encoded by the respective encoding units 31.
-A, B input to the prediction unit 4.

A FIFO memory 32-for temporarily storing the code data 10-A, B output from the encoding units 31-A, B corresponding to the encoding units 31-A, B, respectively.
A and B are provided. This FIFO memory 32-A, B
Is read in sequence from the previously stored code data in accordance with the read signals 34-A and B from the synthesizing unit 36, basically in units of a predetermined data amount, and the unit code data 35
It is passed to the synthesizing unit 36 as A and B. FIFO memory 32-
Each of A and B can store a plurality of units of code data, and a memory status signal 33-indicating whether it is empty or full.
Output A and B.

The synthesizing unit 36 is provided for each FIFO memory 32-.
Based on the memory status signals 33-A and B from A and B, basically, the FIFO memory 32-A and the FIFO memory 32 are
-B, the read signal 34-A or the read signal 34-B is alternately sent to read the code data to obtain the unit code data 35-A or the unit code data 35-B.
The composite code data 37 is output. FIFO memory 3
When one of 2-A or FIFO memory 32-B is empty and the other is full, the identification code of the side that has become full is inserted to continue from the full FIFO memory. The unit code data is read and output as the composite code data 37. Also, at the end of code data,
FIFO memory 32-A or FIFO memory 32-B
The remaining code data is read and output.

Next, an example of the operation of the embodiment of the encoding apparatus of the present invention will be described. FIG. 2 is an explanatory diagram of an example of image data. In FIG. 2A, (n + 1)
An original image composed of x (n + 1) pixels is shown, and the data of each pixel from the left end to the right end of each line is sequentially input from the top to the bottom in the drawing. That is, P ₀₀ ,
P ₀₁ , ..., P _0n , P ₁₀ , P ₁₁ , ..., P _1n ,
The image data 1 of each pixel is input in the order of P ₂₀ , ..., P _mn . In the configuration shown in FIG. 1, two blocks of the encoding unit are provided, but the encoding units 31-A and 31-B alternately encode the input image data 1. That is, the encoding unit 31-A, as shown in FIG.
Encoding processing is performed on the pixels P ₀₀ , P ₀₂ , ..., P ₁₀ , P ₁₂ , ... (Pixels with the second subscript being an even number). In addition, as shown in FIG. 2C, the encoding unit 31-B has pixels of P ₀₁ , P ₀₃ , ..., P ₁₁ , P ₁₃ , ... (Pixels of which the second subscript is an odd number). Is controlled so as to perform the encoding process for.

The context generation unit 2 generates the context 3 from the input image data 1 according to the template as shown in FIG. 12, for example. For example, when the image data 1 of P ₂₂ is input, the context is generated by 10 pixels excluding P ₂₂ shown in FIG. Next P
_When the image data 1 of ₂₃ is input, the context is generated by 10 pixels except P ₂₃ shown in FIG. These contexts are uniformly generated regardless of which coding unit is used. In this way, by generating the context 3 regardless of the encoding unit, the accuracy of prediction is improved and efficient encoding is possible.

When the pixel having the second subscript with an even number is input, the encoding unit 31-A takes in the context 3-A and the image data 1-A output from the context generating unit 2. For example, when the image data of P ₂₂ is input, this is taken in as image data 1-A and
The context 3-A generated by the template shown in FIG. 2D corresponding to P ₂₂ is fetched. Similarly, when the pixel having the second subscript with an odd number is input, the encoding unit 31-B takes in the context 3-B and the image data 1-B output from the context generation unit 2. For example, when the image data of P ₂₃ is input, it is captured as the image data 1-B, and the context 3-B generated by the template shown in FIG. 2E corresponding to P ₂₃ is captured.

In each of the encoding units 31-A and B, the above-mentioned FIG.
By the same operation as in 1, the image data 1-A and B are adaptively predictively encoded according to the contexts 3-A and B, and the code data 10-A and B are output.

FIG. 3 is a timing chart showing an example of the input of an image and the operation of each coding section in the embodiment of the coding apparatus of the present invention. The image data 1 for one pixel is input together with the input image clock. Encoding unit 31-
The input image clock is set to 2 in A and the encoding unit 31-B.
The divided clocks with different phases are input. Since the image data 1 is latched at the rising edges of the respective clocks in the encoding units 31-A and B, the resulting latched image data A and B must be input to the respective encoding units every other pixel. become. In the example of FIG. 3, first, while the pixel P ₂₀ is being input, the encoding unit 31-
The clock of A rises, and P ₂₀ is taken into the encoding unit 31-A and encoded. Next, while the pixel P ₂₁ is being input, the clock of the encoding unit 31-B rises and P
₂₁ is captured by the encoding unit 31-B and encoded. P
_{While 21} is being input, the clock of the encoding unit 31-A does not rise, so P ₂₁ is not taken into the encoding unit 31-A. In this way, the image data 1 is alternately captured by the encoding unit 31-A and the encoding unit 31-B and encoded.

As shown in FIG. 3, the encoding units 31-A,
B can perform the encoding process for only two cycles of the input image clock. On the contrary, the encoding units 31-A, B
Operate in parallel, the image data 1 can be input and encoded at a speed twice as fast as the processing speed, and the overall encoding speed is doubled as compared with the case where there is only one encoding unit. At this time, since the context generation unit 2 is shared, the encoding unit 31-A and the encoding unit 31-B independently perform the encoding process, but the prediction with a high hit rate is performed. It is possible to improve the compression efficiency.

The coded data 10-A, B coded and output by the respective coding units 31-A, B are respectively FIF.
It is stored in the O memories 32-A and B. FIFO at this time
A plurality of units of code data are stored in the memories 32-A and B with a predetermined data amount as a unit. Here, as an example, it is assumed that code data is stored in word units.

FIG. 4 is a flow chart showing an example of the operation of the synthesizing section in the embodiment of the encoding apparatus of the present invention. In this flowchart, the FIFO memory 32-
A is shown as'A 'and FIFO memory 32-B is shown as'B'. The synthesizing unit 36 is basically S
The operations of 71 to S74 are repeated. That is, in S71, it is determined whether or not the FIFO memory 32-A is empty by referring to the memory status signal 33-A. If it is not empty, in S72, one word of code data (unit code data) from the FIFO memory 32-A is read. 35-A) is read out and output as composite code data 37. Next, in S73, it is determined whether or not the FIFO memory 32-B is empty by referring to the memory status signal 33-B. If not empty, the FIFO memory is used in S74.
The code data (unit code data 35-B) for one word is read from the memory 32-B and output as the composite code data 37. By repeating this, the encoding unit 3
1-A and the encoded data encoded by the encoding unit 31-B is 1
Each word is output alternately, and the encoding unit 3
This means that the code data generated in 1-A and B are combined. By performing such synthesis, the encoding unit 3
The code data generated in 1-A and B can be managed as one code data without separately managing them. Further, the identification code for identifying each code data can be eliminated as much as possible, and the increase of the data amount at the time of composition is suppressed.

In the arithmetic coding method, one code is not always output for one input of image data. For example, when the coding can be performed very efficiently, the code is not input if a large number of image data are not input. No output. Further, as described with reference to FIG. 10, since the decimal part of the base of the effective area is used as a code, a carry may occur depending on the change of the effective area in some cases. For example, when the base of the effective area is 0.0111 in binary, it may be changed to 0.10001 or the like due to division of the effective area. In such a case, the code cannot be output in consideration of the possibility that this carry will occur.

There is a case where the code data is not output in this way in one of the encoding units, and the output of the code data from the other encoding unit is accumulated in the FIFO memory. For example, when the state in which the code data is not output from the encoding unit 31-A continues and the code data from the encoding unit 31-B is accumulated in the FIFO memory 32-B, whether the encoding is completed in S75. After judging whether or not S
At 76, it is determined whether the FIFO memory 32-B is full. If it is not full, the process directly returns to S71.
This is because the format of outputting code data alternately for each word is not destroyed, if possible.
When the code data is output from 1-A, it is alternately set to 1 again.
The process of reading and outputting word by word is started.

Further, when the code data is not output from the encoder 31-A and the FIFO memory 32-B becomes full,
Since the encoding unit 31-B cannot output the encoded data, it has to stop the encoding process. To avoid this situation, the memory status signal 33-A indicates empty
If the memory status signal 33-B indicates full,
In S77, an identification code indicating that code data from the same block as the code data output immediately before is continuously output is output, and all words are read from the FIFO memory 32-B and output. And S71
Then, the process returns to and waits for the code data to be stored in the FIFO memory 32-A again.

The same applies to the case where the coded data from the coding unit 31-B continues to be output and the coded data from the coding unit 31-A is accumulated in the FIFO memory 32-A. After the unit code data 35-A for one word is read from the FIFO memory 32-A and output in S72,
In step S73, it is determined that the FIFO memory 32-B is empty. After it is determined in S78 whether the encoding process is completed, it is determined in S79 whether the FIFO memory 32-A is full. If the FIFO memory 32-A is not full, S7
3, the process waits until code data is stored in the FIFO memory 32-B. FIFO memory 32-B remains empty F
When the IFO memory 32-A becomes full, in S80, the identification code is output and the FIFO memory 3
Read and output all words from 2-A. Then, the process returns to S73 and waits again for the code data to be stored in the FIFO memory 32-B.

As described above, when the FIFO memory is full, by outputting the code data together with the identification code, the data amount of the combined code data is slightly increased, but the high-speed code can be performed without stopping the coding unit. The conversion process can be performed.

Even when the input of the image data 1 to be coded is lost and the coding process is completed, either of the FIFs
Other FIFOs with code data stored in O memory
It waits for the code data to be stored in the memory.
In order to avoid this, the end of the encoding process is determined in S75 and S78. When the end of the encoding process is determined in S75, it is determined in S71 that the FIFO memory 32-A is empty, so that data remains in the FIFO memory 32-B. In S81, after outputting the identification code, all code data in the FIFO memory 32-B is read and output. If it is determined in S78 that the encoding process has ended, it is determined in S73 that the FIFO memory 32-B is empty. Therefore, in S82, after the identification code is output, the FIFO memory 32-A is output.
Reads and outputs all the code data in. In this way, all code data can be output.

FIG. 5 is an explanatory diagram of an example of the synthetic code data. An example of the combined code data 37 output from the combining unit 36 as described above is shown in FIG. here,
“A” is the unit code data 35-A read from the FIFO memory 32-A, and “B” is the FIFO memory 32.
It is the unit code data 35-B read from -B. Basically, FIFO memory 32-A and FIFO memory 32-
Unit code data 35-A, B alternately from B every 1 word
Since the unit code data 35-A read from the FIFO memory 32-A and the unit code data 35-B read from the FIFO memory 32-B are
The words are alternated one by one. That is, the unit code data 35-A read from the FIFO memory 32-A
Are A ₀ , A ₁ , ... In turn, and the FIFO memory 32
Unit code data 35-B read from
₀ , B _1, ..., First, A ₀ , B ₀ ,
The sign of A _0, B ₁ ··· and each block is output alternately.

After the output of A _n , a period in which the coded data 10-A is not output from the encoding unit 31-A continues, and the coded data 10-B is output from the encoding unit 31-B during that period. . After outputting B _n , the FIFO memory 3
The code data is not read until the 2-B is full, and is simply stored in the FIFO memory 32-B as it is. This state continues, and the FIFO memory 32
When -B is full, the identification code is output, and all code data in the FIFO memory 32-B is read and output. The capacity of the FIFO memory 32 is 16 words here. As shown in FIG. 5, B _{n + 1} to B _{n + 16} are output following the identification code.

In this example, thereafter, the coded data is output from the coding unit 31-A, and read and output are alternately performed again with A _{n + 1} , B _{n + 17} , .... Of course, after that, there is no output of code data from the encoding unit 31-A, and if the FIFO memory 32-B becomes full again, all the code data in the FIFO memory 32-B is output together with the identification code. The same applies when the code data is not output from the encoding unit 31-B and the code data is accumulated in the FIFO memory 32-A. In this way
It is possible to combine the code data separately encoded by the encoding unit 31-A and the encoding unit 31-B into one, and output the combined code data 37 in which the increase in the data amount is suppressed.

The above-mentioned identification code may be any code as long as it is different from a normal code. For example, a comment marker such as FF04 (hexadecimal) defined by the JBIG standard may be used.

FIG. 6 is a block diagram showing an embodiment of the decoding apparatus of the present invention. 17, those parts that are the same as those corresponding parts in FIG. 17 are designated by the same reference numerals, and a description thereof will be omitted. 41 is a decoding unit, 42 is a FIFO memory, 43 is a memory status signal,
44 is a write signal, 45 is unit code data, 46 is a division unit, and 47 is composite code data. Note that FIG. 6 shows an example in which two blocks of the decoding unit 41 are provided, one of which is A
Blocks and the other block are B blocks, and configurations related to each block are distinguished by adding A or B after “−”.

The dividing section 46 divides the combined code data 47 into unit code data 45-A and B, and controls the FIFO memories 42-A and B with reference to the memory status signals 43-A and B. Unit code data 45-A,
B is written in the FIFO memories 42-A and B, respectively.
The dividing unit 46 performs an operation that is completely opposite to that of the combining unit 36 in the above-described encoding device. That is, basically, the synthetic code data 47 is divided into a predetermined amount of data and written alternately into the FIFO memory 42-A or the FIFO memory 42-B. When the identification code is detected, the unit code data of a predetermined data amount is continuously written in one of the FIFO memories.

The FIFO memories 42-A and B are provided in the preceding stages corresponding to the decoding units 41-A and B, respectively.
The unit code data 45-A, B having a predetermined data amount is stored according to the write signals 44-A, B. Decoding unit 41-
A and B read the code data 10-A and B from the corresponding FIFO memories 42-A and B and decode them.

The decoding units 41-A and 41-B are arithmetic decoding units 2 excluding the context generation unit 2 in the configuration shown in FIG.
1, a probability estimation table 6, and an inverse prediction unit 22. The context generation unit 2 is provided commonly to the two decoding units 41-A and 41-B. The image data 1 is alternately output from the decoding units 41-A and B. Output image data 1
Is input to the context generation unit 2 and generates a context 3 according to a template as shown in FIG. 12, for example. Context 3 generated by context generator 2
Are alternately input to the decoding unit 41-A or the decoding unit 41-B.

Next, an example of the operation of the embodiment of the decoding apparatus of the present invention will be described. For example, the composite code data 47 as shown in FIG. 5 is input to the dividing unit 46. The dividing unit 46 basically divides the combined code data 47 into units of a predetermined data amount, for example, one word unit, and divides the divided unit code data 45-A and B into the write signal 44-.
A and B are written alternately into the FIFO memories 42-A and B. When writing, the memory status signal 43-
By referring to A and B, it is confirmed that the FIFO memory on the writing side is not full.

For example, in the synthetic code data 47 shown in FIG. 5, the first unit word code data A ₀ is written in the FIFO memory 42-A, and the next unit word data unit B ₀ is written in the FIFO memory 42-B. Write. Similarly, A ₁ , ..., _An are stored in the FIFO memory 42-A and B 1,
₁ , ..., B _n are sequentially written into the FIFO memory 42-B. Referring to the memory status signals 43-A and B, if either of the FIFO memories 42-A and B is full, the writing is temporarily stopped at that point.

When the identification code is detected, a predetermined number of unit code data following it are written in one of the FIFO memories. In the case of the synthetic code data 47 shown in FIG. 5, since the writing is performed in the FIFO memory 42-B before the identification code, the unit code data of 16 words following the identification code is sequentially written in the FIFO memory 42-B. Go on.
Also in this case, referring to the memory status signal 43-B, the FIFO
When the memory 42-B is full, control is performed to suspend writing.

The operation in each of the decoding units 41-A, B is the same as that in FIG. 17 described above, and the contexts 3-A, B generated by the context generating unit 2 are used to output from the FIFO memories 42-A, B. Read code data 10-A, B
Is decoded and output as image data 1-A, B. At this time, the decrypting units 41-A and 41-B
The context output from is alternately fetched according to the pixel position to be decoded and decoded. For example, when the image shown in FIG. 2A is restored, the decoding unit 41-A that decodes the code data obtained by encoding the pixels shown in FIG. 2B has an image of pixels in which the second subscript is an even number. Take in context 3-A when decrypting the data. Similarly, a decoding unit 41 that decodes coded data obtained by coding the pixels illustrated in FIG.
-B captures the context 3-B when decoding the image data of the pixel whose second subscript is an odd number.

FIG. 7 is a timing chart showing an example of the relationship between the operation of the decoding section and the output of image data in the embodiment of the decoding apparatus of the present invention. Decoding unit 41-
Clocks having different phases are given to A and B, and decoding is performed according to the clocks. By the decoding process, the image data that is the decoding result is determined at a certain point. At this time, the decoding unit 41-A and the decoding unit 41-B
Perform decoding processing independently of each other, and it is possible to perform decoding at a speed twice that in the case where there is one decoding unit.

Since the decoding unit 41-A and the decoding unit 41-B operate in accordance with clocks having different phases, FIG.
As shown in, the timing at which the decoding result is determined is different.
This is output alternately by the output image clock having a half cycle of the clock given to the decoding units 41-A and 41-B. As a result, the decoding result of the decoding unit 41-A that decodes the pixel illustrated in FIG. 2B and the decoding result of the decoding unit 41-B that decodes the pixel illustrated in FIG. 2C alternate. 2 is selected, the image data shown in FIG. 2A is sequentially output.

In this way, the decoding units 41-A,
The image data in which the decoding result of B is alternately selected is also input to the context generation unit 2. As a result, in the context generation unit 2, as in the case of encoding, the context generation unit 2 shown in FIG.
It is possible to generate a context with reference to consecutive pixels as shown in FIG.

However, in the context generation unit 2, there is a problem that the current pixel cannot be decoded because the context of the current pixel cannot be generated unless the decoding of the previous pixel is completed. That is, if the decoding process is delayed by one decoding unit, the other decoding process cannot be started, and the processing speed is reduced. In order to avoid this, for example, as disclosed in Japanese Patent Application No. 8-288731 mentioned above, inverse prediction is performed according to all possible values of the previous pixel at the time of decoding to generate a plurality of inverse prediction data.
Then, a method has been proposed in which any of the inverse prediction data is selected when the value of the previous pixel is determined to speed up the decoding process, and this technique can be used in the present invention.

In the decoding apparatus of the present invention shown in FIG. 6, the decoding units 41-A and 41-B decode every other pixel. Therefore, for example, when the current pixel is decoded by the decoding unit 41-A, the pixel immediately before being decoded by the decoding unit 41-A, that is, the pixel two pixels before in the original image and the other decoding unit 41. -The pixel being decoded in B, that is, the pixel one pixel before in the original image is used for the context. Although the value of the pixel decoded immediately before by the decoding unit 41-A is fixed, if the inverse prediction table in the inverse prediction unit 22 is rewritten, the inverse prediction cannot be performed until the rewriting is completed. In addition, the decoding unit 41
Regarding the pixel to be decoded in -B, the value may not be fixed because it is processed in parallel. for that reason,
When decoding the current pixel, the previous pixel and
For a pixel before the pixel, a plurality of inverse prediction values corresponding to all possible combinations of values are obtained. Then, when the value of the pixel decoded immediately before by the decoding unit 41-A and the value of the pixel currently decoded by the decoding unit 41-B are determined, a plurality of inverse prediction values are calculated from the values of these pixels. Choose the correct one from the.

A configuration for realizing such an operation is shown below. FIG. 8 is a block diagram showing another example of the decoding unit in the embodiment of the decoding apparatus of the present invention. In the figure, 51 to 54 are inverse prediction tables, 55 is a write controller, 56 is a write signal, 57 is a write address, and 58 is a write address.
Is a selection unit, 59 is image data from another decoding unit, and 60 is previous image data. Here, only the configuration of one decoding unit is shown. The configuration shown in FIG. 8 is applied to the decoding units 41-A and 41-B in FIG.

In this configuration, for example, a context consisting of eight image data of X _{9 to} X ₂ excluding X ₁ and X ₀ of the template shown in FIG. 12 is used. Inverse prediction table 5
Each of 1 to 54 is a table having a configuration as shown in FIG. 13, for example, and is stored in a storage device such as a RAM. The addresses of the reverse prediction tables 51 to 54 are as shown in FIG.
Unlike the one shown in FIG. 3, it is composed of 8 bits.
The inverse prediction table 51 stores the inverse prediction value and the state when the pixels of X ₁ and X ₀ are assumed to be 0 and 0. Similarly, the reverse prediction tables 52 to 54 respectively store the reverse prediction values and the states when the pixels of X ₁ and X ₀ are assumed to be ₀ , ₁ , ₁ , ₀ , ₁ , ₁ , respectively. Four inverse prediction tables 51 to 51 depending on an 8-bit context
The inverse predicted value and the state are read from 54 and input to the selection unit 58.

The selecting unit 58 fetches the image data 1 output from the arithmetic decoding unit 21 as the previous image data 60 and the image data 59 from the other decoding unit, and based on these, the inverse prediction table 51. 54 to 54, select any one of the inverse prediction value and the state, and set the state in the probability estimation table 6 to the inverse prediction value 23.
Is output to the arithmetic decoding unit 21. For example, the previous image data 6
When 0 is 0 and the image data 59 from the other decoding unit is 0, the output of the inverse prediction table 51 is selected. Similarly,
When the previous image data 60 and the image data 59 from the other decoding unit are 0 and 1, the output of the inverse prediction table 52 is selected,
In the case of 1, 0, the output of the inverse prediction table 53 is selected,
In the case of 1, 1, the output of the inverse prediction table 54 is selected.

The write control unit 55 uses the inverse prediction table 5
Context X used in 1 to 54 ₉~ X₂Write
Output to the reverse prediction tables 51 to 54 as addresses
And in response to the rewriting instruction of the rewriting signal 12.
Image data 1 output from the arithmetic decoding unit 21
And write from the value of the image data 59 from the other decoding unit.
Select any of the inverse prediction tables 51 to 54 to be performed
The write signal 56 to the selected inverse prediction table.
It Each of the inverse prediction tables 51 to 54 has a probability estimation table.
Rule 6 output NMPS or NLPS and arithmetic
The new inverse prediction value output from the decoding unit 21 is the rewriting data.
Since it is given as the data 24, the write control unit 55
In the inverse prediction table to which the write signal 56 is sent from
Similarly, the write controller sent from the write controller 55
The rewrite data 24 is written in the dress.

FIG. 9 shows an embodiment of the decoding apparatus of the present invention.
An example of the operation of another example of the decoding unit in the state
FIG. In Figure 9, in Figure 2
P _{twenty four}Decoding of the pixel at the position is performed by the decoding unit 41-A.
An example is shown. In the decryption unit 41-A, P_{twenty four}In the position of
Just before decoding the pixel, P_{twenty two}Decode the pixel at the position.
The write control unit 55 uses P_{twenty two}The pixel at the position of
Context X ' ₉~ X '₂Holding

While the pixel at the position of P ₂₂ is being decoded, the contexts X _{9 to} X _{2 in} which the pixel at the position of P ₂₄ is the target pixel are input to the inverse prediction tables 51 to 54 as addresses. From the reverse prediction tables 51 to 54, X ₁ and X ₀ are 0, respectively.
Four kinds of inverse prediction values and states of 0, 01, 10, and 11 are read and input to the selection unit 58.

On the other hand, in the decoding section 41-B, P_{twenty three}of
The pixel at the position is decoded by P in the decoding unit 41-A._{twenty two}of
The decoding is started by a half cycle after the pixel at the position is decoded. Eventually
P in the encoding unit 41-A_{twenty two}The pixel at the position is decoded
Image data is output, and this is the previous image data 60.
It is input to the selection unit 58. After that, the decryption unit 41-B
P in_{twenty three}The pixel at the position is decoded and the image data is output
The selection unit 5 outputs the image data 59 from the other decoding unit.
8 is input. X at this point₁, X₀Value of 00,0
Since it is decided whether it is 1, 10, or 11,
The selection unit 58 outputs one of the inverse prediction tables 51 to 54.
Select (inverse prediction value, state) and select P _{twenty four}Pixel at position
Inverse predictor for decoding
It is passed to the encoding unit 21 and the probability estimation table 6. By this
P in the next cycle_{twenty four}Start decoding pixel at position
You can

When the inverse prediction table is rewritten by the decoding of P ₂₂ , the write control unit 55
Outputs the contexts X ′ _{9 to} X ′ _{2 in} which the held pixel at the position of P ₂₂ is the target pixel as the write address 57 to the prediction tables 51 to 54. Also, the image data 1 at the position of P ₂₂ output from the arithmetic decoding unit 21,
The inverse prediction table to be rewritten is specified from the image data 59 from the other decoding unit, which is the image data at the position of P ₂₃ output from the decoding unit 41-B, and the write signal 56 is sent to the inverse prediction table. . Inverse prediction table 51-
54 includes a probability estimation table 6 and an arithmetic decoding unit 21.
Since the rewrite data 24 regarding the image data at the position of P ₂₂ is input, the inverse prediction table to which the write signal 56 is given from the write control unit 55 rewrites the data of the write address 57 to the rewrite data 24. In the next decoding of the pixel at the position of P ₂₆ , four types of inverse prediction values and states will be output using the rewritten inverse prediction table.

Of course, the image data 1 at the positions of P ₂₂ and P ₂₄ output from the decoding unit 41-A is the decoding unit 41-
It is sent to B and used as the image data 59 from the other decoding unit, and the decoding is carried out by the same processing.

In this way, the inverse prediction table can be read even before the inverse prediction table is rewritten.
The processing of the arithmetic decoding unit 21 and the reading of the inverse prediction tables 51 to 54 can be executed in parallel, and the decoding processing can be speeded up.

The inverse prediction tables 51 to 54 are configured as two inverse prediction tables based on only the value of the previous pixel for the image data 59 from the other decoding unit, and the arithmetic decoding unit 21 outputs the image data 1. Then, the contexts X _{9 to} X ₁ may be used. Alternatively, a three-port memory may be used to configure two or one memories.

Here, an example has been shown in which the decoding apparatus performs prefetching of the inverse prediction table as shown in FIG. 8 to increase the speed. For example, as described in Japanese Patent Application No. 8-301889 mentioned above, the code If the encoding device is configured to perform pre-reading of the prediction table, the encoding device can perform the encoding process without causing a delay due to the writing of the prediction table, and the encoding can be performed at high speed.

An example of the encoding device and the decoding device for arranging a plurality of encoding units or decoding units according to the present invention and performing parallel processing has been described above. The invention is not limited to these examples. For example, the encoding unit and the decoding unit may be configured in a larger number than two blocks and further parallelized. Further, the unit of the data amount of the code data to be synthesized by the synthesizing unit 36 may be other than one word, and the synthesizing can be performed sequentially with an arbitrary data amount as a unit. Further, the number of units of code data from the specific coding unit following the identification code can be set arbitrarily. These need only be settable with the decoding device, and the dividing unit 46 may divide the combined code data according to the same rules as at the time of encoding.

Further, the FIFO memory 32 and the FIFO memory
The capacity of the memory 42 is not limited to 16 words and may be any capacity. Of course, the FIFO memory 32 and FI
The FO memories 42 may have different capacities, and the synthesizing unit 36 and the dividing unit 46 may perform FI according to the format of the synthetic code data.
The FO memory 32 and the FIFO memory 42 may be controlled.

Furthermore, the present invention is not limited to combining the code data of the predictive coding method with the combined code data, and may be configured to also combine the code data of different coding methods. is there.

As described above, according to the present invention, since the speed can be increased even in the encoding method such as JBIG which is difficult to increase in speed, the JBIG can be applied to a system such as a printer or a copying machine which requires high speed real time processing. It is possible to compress data by applying a high-efficiency encoding method such as.

[0087]

As is apparent from the above description, according to the encoding device of the first aspect of the present invention, the code data processed in parallel can be efficiently combined into one code. While suppressing the increase in the amount of data in
The management of code data can be simplified.

According to the decoding device of the second invention,
It is possible to obtain a decoding device in which the coded data efficiently combined is distributed and input to the plurality of decoding means by the dividing means, and parallel processing can be performed by the plurality of decoding means.

In addition, since the predictive coding can be performed in parallel by a plurality of coding means, the coding can be performed at high speed. At this time, since a large image memory is not required in the previous stage and the context can be generated in the same manner as when using a single encoding unit, it is possible to perform encoding without impairing the encoding efficiency. Further, similar to this encoding device, a large image memory is not required in the preceding stage, and the decoding processing can be performed in parallel by a plurality of decoding means, so that high-speed real-time decoding can be performed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of an encoding device of the present invention.

FIG. 2 is an explanatory diagram of an example of image data.

FIG. 3 is a timing chart showing an example of image input and an operation of each encoding unit in the embodiment of the encoding device of the present invention.

FIG. 4 is a flowchart showing an example of the operation of a synthesizing unit in the embodiment of the encoding device of the present invention.

FIG. 5 is an explanatory diagram of an example of composite code data.

FIG. 6 is a block diagram showing an embodiment of a decoding device of the present invention.

FIG. 7 is a timing chart showing an example of the relationship between the operation of the decoding unit and the output of image data in the embodiment of the decoding apparatus of the present invention.

FIG. 8 is a block diagram showing another example of the decoding unit in the embodiment of the decoding apparatus of the present invention.

FIG. 9 is a timing chart for explaining an example of the operation of another example of the decoding unit in the embodiment of the decoding apparatus of the present invention.

FIG. 10 is a conceptual diagram of arithmetic coding.

FIG. 11 is a schematic diagram of a predictive coding system adopted in JBIG.

FIG. 12 is an explanatory diagram of an example of a template used in JBIG.

FIG. 13 is an explanatory diagram of an example of a prediction table stored in the prediction unit 4.

FIG. 14 is an explanatory diagram of an example of a probability estimation table 6.

FIG. 15 is an explanatory diagram of a specific example of input image data.

FIG. 16 is an explanatory diagram of a specific example of a prediction unit table after rewriting.

FIG. 17 is a schematic diagram of a predictive decoding system adopted in JBIG.

FIG. 18 is an explanatory diagram of a basic operation of the arithmetic decoding unit.

[Description of Codes] 1 ... Image data, 2 ... Context generation unit, 3 ... Context, 4 ... Prediction unit, 5 ... State, 6 ... Probability estimation table, 7 ... LSZ and SW, 8 ... Predicted value, 9 ... Arithmetic code Coder, 10 ... Code data, 11 ... Rewrite data, 1
2 ... Rewriting signal, 21 ... Arithmetic decoding part, 22 ... Inverse prediction part, 23 ... Inverse prediction value, 24 ... Rewriting data, 31 ... Encoding part, 32 ... FIFO memory, 33 ... Memory status signal, 34 ... Read signal , 35 ... Unit code data, 36 ...
Compositing unit, 37 ... Combined code data, 41 ... Decoding unit, 42
... FIFO memory, 43 ... Memory status signal, 44 ... Write signal, 45 ... Unit code data, 46 ... Dividing unit, 47 ...
Composite code data 51 to 54 ... Inverse prediction table, 55 ...
Write control unit, 56 ... Write signal, 57 ... Write address, 58 ... Selection unit, 59 ... Image data from other decoding unit, 60 ... Previous image data.

Claims (2)

[Claims] 1. A plurality of encoding means for encoding input data sequentially distributed in units of a predetermined unit, and code data generated by the plurality of encoding means in a predetermined order.
When there is empty code data to be output in one encoding means, the combining means outputs the above-mentioned code data output from another encoding means together with the identifier. An encoding device characterized by the above. 2. A decoding device for decoding synthetic code data obtained by sequentially synthesizing code data obtained by sequentially allocating and coding coded input data for each predetermined unit in a predetermined order. And a dividing unit that divides the input composite code data into the code data and distributes and inputs the code data to the plurality of decoding units, and the dividing unit is provided when an identifier appears in the composite code data. ,
A decoding device, characterized in that a plurality of the coded data consecutive to the identifier are continuously inputted to the same decoding means.