JP3251447B2 - Encoding device and method, and decoding device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus and method for encoding or decoding an image for each pixel , and a decoding apparatus and method.

[0002]

2. Description of the Related Art An outline of an encoding apparatus using general predictive encoding will be described with reference to FIG.

In FIG. 1, reference numeral 501 denotes an image memory, which is a memory for storing an image to be encoded.
Reference numeral 502 denotes a prediction reference pixel synchronization generation unit for supplying a prediction reference pixel group to a prediction state memory, which will be described later, and includes a line memory for several lines, a latch for delaying several pixels, and the like.

FIG. 8 shows a prediction reference pixel group (template).
It is a figure showing the example of. In the figure, the * part is the pixel of interest for encoding (Target Pixel), and the hatched parts 1 to
Reference numeral 12 denotes a prediction reference pixel, and in this example, a template is configured using 12 pixels of 4 lines including the own line. This example is merely an example, and does not refer to the number / position of reference pixels in this case.

Returning to FIG. 5, reference numeral 503 denotes a prediction state memory which receives a prediction reference pixel as an address input and outputs a prediction symbol and a prediction state. Reference numeral 504 denotes an exclusive OR (EOR) gate circuit, which determines whether the pixel of interest to be coded and the predicted symbol match or not. Reference numeral 505 denotes an encoding circuit which inputs a prediction state from the prediction state memory 503 and a match / mismatch from the exclusive OR gate circuit 504 and performs an encoding operation, and has an arithmetic unit 506 and an update logic 507 (predict state update unit) inside ). 508 is an encoding circuit 505
This is a buffer memory for storing codes output from.

The encoding operation will be described below with reference to FIGS.

First, the data flow until immediately before the encoding apparatus is renormalized will be described with reference to FIG. 6, focusing on the operation of the prediction state memory. In the figure, 601 to 608
Are equivalent to 501 to 508 shown in FIG. The portion shown by the dotted line is a non-operation portion. Predicted state memory 603
Uses the prediction reference pixel group (template) output from the prediction reference pixel synchronization generation unit 602 as an address input, and outputs a prediction state and a prediction symbol. Therefore, the port of the prediction state storage memory 603 is an output. The prediction state is input to the calculation unit 606, and the prediction symbol is EOR
The data is input to the gate 604, and the comparison with the prediction reference pixel is performed for the match / mismatch.

Next, a data flow in the case where re-normalization occurs during the encoding process will be described with reference to FIG.
5, reference numerals 701 to 708 denote 501 to 5 shown in FIG.
08. The portion shown by the dotted line is a non-operation portion.

When a re-normalization instruction is output after the above-described processing of the arithmetic unit 706, the update logic of 707 operates, the port of the prediction state memory 703 becomes an input, and a new prediction state / prediction symbol is output. Is written. The address at this time is the same as at the time of reading. As described above, when renormalization occurs, reading and writing of the prediction state memory 703 are performed twice for the same address.

[0010]

However, the general configuration as shown in FIG. 5 has the following problems.

1. Since the reading and / or writing operation of the prediction state memory is performed in the encoding process for each pixel, the encoding speed is limited by the access speed of the memory.

2. Since the above-described read / write operation is always performed on the same address in the prediction state memory, it must be completed before processing of the next pixel to be coded, which hinders speeding up.

3. Since the input / output of the memory data bus is switched, the control is complicated.

FIG. 5 shows the encoding.
A similar problem occurs in the decoding process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides an encoding apparatus and method, and a decoding apparatus and method which have a simple configuration and can improve the speed of encoding and decoding processing. The purpose is to provide. Specifically, on
Using the prediction state memory as described above, the image is
In the case of encoding, the reference
Focusing on the value of the illuminated pixel, each time
When the value of changes frequently, the prediction
Providing a configuration that allows access to memory
Aim.

[0016]

To achieve the above object, the present invention provides an encoding apparatus for encoding an image on a pixel-by-pixel basis.
And has a predetermined relative positional relationship with the pixel of interest for encoding.
A plurality of surrounding pixels are used as a reference pixel group, and the value of the reference pixel group
A prediction state memory that outputs a prediction value / prediction state for the encoded pixel of interest,
Encoding means for encoding using the predicted value / predicted state, and after the encoding , the predicted value / predicted value in the predicted state memory
A updating means for updating the estimated status, the estimated status main
The memory is a predetermined number of pixels at a specific position in the reference pixel group.
Consists of multiple memory banks classified according to the value of
Of the reference pixel group in the first target pixel of interest.
The value of a given number of pixels at a fixed position, followed by the
Of a reference pixel group in a second coded target pixel
When the value of the predetermined number of pixels at the position is different, and
When the encoding result of the encoding target pixel of 1 is updated
The updating means adds the first encoding target pixel to the
Value of a predetermined number of pixels at a specific position in the reference pixel group
The predicted value / predicted state in the first memory bank determined accordingly
Update, and in parallel with the update, the encoding means
Of the pixel of interest to be encoded as the second pixel of interest to be encoded
Value of a predetermined number of pixels at a specific position in the reference pixel group
The predicted value / predicted state in the second memory bank determined accordingly
It is characterized by using and encoding .

According to another aspect of the present invention, there is provided an encoding method for encoding an image on a pixel-by-pixel basis.
A plurality of pixels having a predetermined relative positional relationship with the pixel of interest
The surrounding pixels are used as a reference pixel group, and according to the value of the reference pixel group,
A prediction state memory for outputting a prediction value / prediction state for the encoded pixel of interest;
An encoding step of encoding using a prediction state, and an updating step of updating a prediction value / prediction state in the prediction state memory after the encoding, wherein the prediction state memory is
According to the value of a predetermined number of pixels at a specific position of the reference pixel group
It is composed of a plurality of classified memory banks,
At a specific position of the reference pixel group in the pixel of interest
A predetermined number of pixel values and a second code to be encoded next
At the specific position of the reference pixel group in the pixel of interest
If the value of the fixed number of pixels is different and the first encoding
When the coding result of the eye pixel is updated, the updating is performed.
In the new process, the first encoding target pixel
According to the value of a predetermined number of pixels at a specific position of the reference pixel group
Update the predicted value / predicted state in the determined first memory bank
In parallel with the updating, the encoding step
2 is the pixel of interest to be encoded,
Of the predetermined number of pixels at a specific position of the reference pixel group in
Value / predicted state in the second memory bank determined according to
The encoding is characterized by using

[0018] In order to achieve the above object, the present invention is, marks
A decoding apparatus for decoding a signal image for each pixel , comprising a plurality of peripheral pixels having a predetermined relative positional relationship with a pixel of interest to be decoded.
The pixels are referred to as a reference pixel group, and the pixels are determined according to the value of the reference pixel group.
Output the predicted value / predicted state for the pixel of interest
A predicted state memory, the forecast value and the decoding target pixel
Decoding means for decoding using a prediction state ;
After, a updating means for updating the forecast value and the predicted state of the prediction state memory, said predicted-state memory, the ginseng
The distribution is performed according to the value of a predetermined number of pixels at a specific position of the illumination pixel group.
A first decryption system comprising a plurality of memory banks
At the specific position of the reference pixel group in the pixel of interest
A fixed number of pixel values, followed by a second decoding to be decoded
A predetermined position at a specific position of the reference pixel group in the target pixel
Pixel values are different from each other and the first decoding
If the decoding result of the pixel is updated, the updating is performed.
The means is a reference pixel in the first decoding target pixel.
The third pixel determined according to the value of a predetermined number of pixels at a specific position in the group
Update the predicted value / predicted state in one memory bank,
In parallel with the second decoding,
An elephant pixel as a reference pixel in the second decoding target pixel
The third pixel determined according to the value of a predetermined number of pixels at a specific position in the group
Characterized <br/> Rukoto be decoded using the prediction value and prediction state within 2 memory banks.

According to another aspect of the present invention, there is provided a decoding method for decoding a code image for each pixel.
Te, a plurality in the decoding target pixel and predetermined relative positional relationship
Surrounding pixels of the reference pixel group, and according to the value of the reference pixel group
A prediction state memory for outputting a prediction value / prediction state for the decoded pixel of interest;
A decoding step of decoding using the measured value / prediction state, and after the decoding, having an update step of updating the prediction value / prediction state in the prediction state memory , wherein the prediction state memory is
According to the value of a predetermined number of pixels at a specific position of the reference pixel group.
And a plurality of memory banks classified in the same manner.
At the specific position of the reference pixel group in the pixel of interest
The value of a given number of pixels and the second
At the specific position of the reference pixel group in the decoding target pixel
Is different from the value of a predetermined number of pixels, and the first decoding
When the decoding result of the pixel of interest is updated,
In the updating step, the first decoding target pixel is
Corresponding to the value of a predetermined number of pixels at a specific position of the reference pixel group
Update the predicted value and predicted state in the first memory bank
New and in parallel with the update,
The second decoding target pixel is set to the second decoding target image.
Of a predetermined number of pixels at a specific position of the reference pixel group
Predicted value / predicted value in second memory bank determined according to value
The decoding is performed using the state .

[0020]

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the encoding apparatus according to the first embodiment. In the figure, 101,
102, 104 to 108 are 501, 50 shown in FIG.
2,504 to 508, respectively.

Reference numeral 103 denotes a prediction state memory, which is divided into four banks in this example, and has the same capacity as the prediction state memory 503 in FIG. 1
Reference numeral 09 denotes a 2-bit data latch for delaying an arbitrary 2 bits of the template by one pixel.
Reference numeral 110 denotes a comparator, which compares the currently used template (109 output) with the next template of the encoding target pixel (109 input) for 2 bits. The output of the comparator 110 is input to the prediction state update unit (update logic) 107. 111 is 2 bits
Is a 2to4 decoder for decoding. Reference numeral 112 denotes a multiplexer for switching the address for the prediction state memory 103 before / after the latch.

FIG. 2 is a diagram showing memory access timing when the output of the comparator 110 matches / mismatches. The output of the comparator 110 matches (two consecutive
When the prediction state memory 103 has the same bank for one encoded pixel of interest, the read / write operation must be performed on the same bank, so that the normal operation is performed (P
HASE1,2). At this time, the read / write operation is sequentially performed only on one predetermined bank of the prediction state memory 103. When the output of the comparator 110 does not match, writing to the predicted state memory 103 (predicted state update) and reading of the predicted state for the next pixel (a different bank from the update) can be performed simultaneously. Yes (PHA
SE4,5).

FIG. 2 shows an example of an encoding procedure.
Each PHASE is the minimum processing unit.
Further, the encoding target pixels are five pixels X1 to X5, and the upper two bits of the template are used for banking. First, an update occurs in PHASE1,
Also, the bank of the template with the next pixel is the same (0X0
96: upper two bits: 0 → bank 1), a normal read / write operation is performed, and the process of X1 ends in two cycles including PHASE2.

PHASE 3 is a case where the update process is not performed in the process of X 2, and only reading from the bank 1 (reading of the predicted state) is performed. Also, the template of the next pixel X3 (0X222: upper 2 bits: 2
→ Since the bank is different from that of the bank 2), it is possible to read simultaneously.

In PHASE 4, writing to bank 2 and reading of the next pixel X4 from bank 3 are performed simultaneously. Similarly, in PHASE 5, writing to bank 3 and reading from bank 4 can be performed simultaneously.

As described above, according to the first embodiment, since reading / writing to different banks can be performed at the same timing, it is possible to speed up the encoding process.

In the first embodiment, four banks are used for convenience.
However, the present invention is not limited to this, and if it is 1 or more, the effect is exhibited, and by further subdividing,
Needless to say, the effect is higher.

<Modification of First Embodiment> FIG. 3 is a block diagram showing a configuration of a modification of the first embodiment.

In this modification, a dual port memory is used as the prediction state memory 303. 309 is 12
Bit (all bits) data latch, 31
0 also uses a 12-bit comparator. Reference numeral 311 denotes an address selector which determines the address of each port of the dual port memory from the current processing pixel address (302 output) or 1
Select whether it is before the pixel (309 output). The dual-port memory is a simultaneous access unless the addresses of the two ports are the same.

Therefore, in this modification, the comparator 3
By comparing all bits of the template with 10, it is possible to increase the speed without dividing the bank of the predicted state memory.

<Second Embodiment> FIG. 4 is a block diagram showing a configuration of a decoding apparatus according to a second embodiment. In the figure, reference numeral 405 denotes a decoding circuit, which is composed of an operation unit 406 and an update logic 407.
Then, the code is sequentially read from the code buffer 408 to perform the decoding process. The decoded pixels are written to the image memory 401 and, at the same time, are also input to the prediction reference pixel synchronization generation unit 402 and are used again as a part of the template in the subsequent decoding processing. Other parts are the same as those of the encoding device.

FIG. 9 is a diagram showing the operation at the time of calculation in decoding. In the figure, reference numeral 908 denotes a code buffer memory, which performs decoding processing from the code data read therefrom, the output of the prediction state memory 903, and the template output 902 to generate decoded pixels. The decoded pixel is written into the image memory 901 and is also input to the template generation unit 902 to be reused in the decoding process for the next pixel and thereafter.

FIG. 10 is a diagram showing the operation when the update process is performed after the decoded pixel is output. When an update instruction is issued from the decoder, a write operation is performed from the update unit 1007 to the prediction state memory 1003. At this time, as shown in FIG. 2, it is clear that writing / reading can be performed at the same time when the bank for writing and the reading bank for the next pixel are different even during decoding.

As described above, according to the second embodiment, it is possible to speed up the decoding process.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device.

It is needless to say that the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0039]

As described above, according to the present invention,
With a simple configuration, it is possible to improve the speed of the encoding and decoding processes. Specifically, a prediction reference pixel is added.
State input that outputs the predicted value / predicted state
When encoding an image pixel by pixel using memory
The value of the reference pixel around the pixel to be coded (in the embodiment,
Represents 12 pixels = 12 bits forming the template.
2 pixels = 2 bits), and code each pixel
Each time these values change frequently,
For two consecutively input pixels of interest
Predicted state method used for outputting and updating predicted values / predicted states
Efficient by making the memory (each memory bank) different
Can access the prediction state memory.

[0040]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encoding device according to a first embodiment.

FIG. 2 is a diagram showing access timings of a prediction state memory shown in FIG.

FIG. 3 is a block diagram showing a configuration according to a modification of the first embodiment.

FIG. 4 is a block diagram illustrating a configuration of a decoding device according to a second embodiment.

FIG. 5 is a block diagram illustrating a configuration of a general encoding device.

FIG. 6 is a diagram for explaining an operation at the time of encoding operation.

FIG. 7 is a diagram for explaining an operation at the time of updating a predicted state.

FIG. 8 is a diagram illustrating an example of a template.

FIG. 9 is a diagram illustrating an operation at the time of calculation in decoding.

FIG. 10 is a diagram illustrating an operation when an update process is performed after a decoded pixel is output.

[Explanation of symbols]

 Reference Signs List 101 Image memory 102 Prediction reference pixel synchronization generation unit 103 Prediction state memory of 4-bank configuration 104 Exclusive OR gate circuit 105 Encoding circuit 106 Operation unit 107 Prediction state update unit 108 Code buffer memory 109 2-bit data latch 110 2-bit comparator 111 2to4 decoder 112 Multiplexer 301 Image memory 302 Prediction reference pixel synchronization generation unit 303 Dual port memory 304 Exclusive OR gate circuit 305 Encoding circuit 306 Operation unit 307 Prediction state update unit 308 Code buffer memory 309 12-bit data latch 310 12-bit Comparator 311 Multiplexer 401 Image memory 402 Prediction reference pixel synchronization generation unit 403 Prediction state memory 405 having four banks Decoding circuit 406 Operation unit 40 Prediction state update unit 408 Code buffer memory 409 2-bit data latch 410 2-bit comparator 411 2to4 decoder 412 Multiplexer 501 Image memory 502 Prediction reference pixel synchronization generation unit 503 Prediction state memory 504 Exclusive OR gate circuit 505 Encoding circuit 506 Operation unit 507 Prediction state update unit 508 Code buffer memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/41-1/419 H03M 7/40

Claims (6)

(57) [Claims] An encoding apparatus for encoding an image for each pixel.
And a plurality of channels having a predetermined relative positional relationship with the pixel of interest for encoding.
The surrounding pixels are used as a reference pixel group, and according to the value of the reference pixel group,
A prediction state memory that outputs a prediction value / prediction state for the encoded pixel of interest; an encoding unit that encodes the encoded pixel of interest using the prediction value / prediction state ; after, a updating means for updating the forecast value and the predicted state of the prediction state memory, said predicted-state memory is a specific position near the reference pixel group
A plurality of memories classified according to the value of a predetermined number of pixels
Consists of a bank, a particular position of the reference pixel group in the first encoding aimed object pixel
And the value of a predetermined number of pixels
Specific position of the reference pixel group in the encoding target pixel of No. 2
Is different from the value of a predetermined number of pixels in
When the encoding result of the encoding target pixel is updated
The updating means stores the first encoded pixel of interest
Corresponding to the value of a predetermined number of pixels at a specific position of the reference pixel group
Update the predicted value and predicted state in the first memory bank
New and in parallel with the update, the encoding means
The encoding target pixel is set to the second encoding target pixel.
Corresponding to the value of a predetermined number of pixels at a specific position of the reference pixel group
Using the predicted value / predicted state in the second memory bank
Encoding apparatus characterized by encoding are. 2. Reference in a first encoding target pixel
The value of a predetermined number of pixels at a specific position in the pixel group, followed by the value
Reference image at the second encoding target pixel to be encoded
If the value of the predetermined number of pixels at the specific position of the prime group is the same,
In addition, the encoding result of the first encoding target pixel is updated.
If the first encoding target pair is
A predetermined number of images at specific positions of the reference pixel group
Prediction value and prediction value in the first memory bank determined according to the prime value
Update the measurement state, and after the update, the encoding means
2 is the pixel of interest to be encoded,
Of the predetermined number of pixels at a specific position of the reference pixel group in
Value / predicted state in the second memory bank determined according to
2. The encoding apparatus according to claim 1, wherein encoding is performed by using the following. 3. The plurality of memory banks includes four memory banks.
A memory bank, wherein the value of the predetermined number of pixels is
1 bit for each of two pixels at a specific position in the reference pixel group
2. The encoding device according to claim 1, wherein the value is a value consisting of: 4. An encoding method for encoding an image for each pixel.
And a plurality of channels having a predetermined relative positional relationship with the pixel of interest for encoding.
The surrounding pixels are used as a reference pixel group, and according to the value of the reference pixel group,
Outputting a predicted value / predicted state for the encoded pixel of interest
That the predicted state memory, a sign-step of marks <br/>-coding using the prediction value and prediction state the sign-reduction target pixel, after the encoding, the predicted value of said predicted-state memory - and a updating step of updating the predicted state, the prediction state memory, a specific position near the reference pixel group
A plurality of memories classified according to the value of a predetermined number of pixels
Consists of a bank, a particular position of the reference pixel group in the first encoding aimed object pixel
And the value of a predetermined number of pixels
Specific position of the reference pixel group in the encoding target pixel of No. 2
Is different from the value of a predetermined number of pixels in
When the encoding result of the encoding target pixel is updated
Is the first encoding target image in the updating step.
Of a predetermined number of pixels at a specific position of the reference pixel group
Predicted value / predicted state in first memory bank determined according to value
State, and in parallel with the update,
The target pixel of the second encoding target by the second encoding target
A predetermined number of pixels at a specific position of the reference pixel group in the target pixel
The predicted value in the second memory bank determined according to the pixel value;
Coding method characterized by coding using prediction state
Law . 5. A decoding device for decoding a code image for each pixel.
A plurality of channels having a predetermined relative positional relationship with a pixel of interest to be decoded.
The surrounding pixels are used as a reference pixel group, and according to the value of the reference pixel group,
Outputting a predicted value / predicted state for the decoded pixel of interest
And a prediction state memory for decoding the pixel of interest using the prediction value / prediction state.
Decoding means for No. of, after the decoding, the prediction value and prediction of the prediction state memory
Updating means for updating a state, wherein the predicted state memory is located at a specific position of the reference pixel group.
A plurality of memories classified according to the value of a predetermined number of pixels
Consists of a bank, a particular position of the reference pixel group in the first decoded interest pixel
Value of a predetermined number of pixels in the
Specific position of reference pixel group in decoding target pixel 2
Is different from the value of a predetermined number of pixels in
When the decoding result of the pixel of interest is updated
The updating means adds the first decoding target pixel to the
Corresponding to the value of a predetermined number of pixels at a specific position of the reference pixel group
Update the predicted value and predicted state in the first memory bank
New and in parallel with the update, the decryption means
The decoding target pixel is set as the second decoding target pixel.
Corresponding to the value of a predetermined number of pixels at a specific position of the reference pixel group
Using the predicted value / predicted state in the second memory bank
There decrypted device, characterized in that it decrypt it. 6. A decoding device for decoding a code image for each pixel.
A plurality of channels having a predetermined relative positional relationship with a decoding target pixel.
The surrounding pixels are used as a reference pixel group, and according to the value of the reference pixel group,
Outputting a predicted value / predicted state for the decoded pixel of interest
And a prediction state memory for decoding the pixel of interest using the prediction value / prediction state.
A decoding step of decoding, and after the decoding, a prediction value / prediction in the prediction state memory.
Updating a state, wherein the predicted state memory is located at a specific position of the reference pixel group.
A plurality of memories classified according to the value of a predetermined number of pixels
Consists of a bank, a particular position of the reference pixel group in the first decoded interest pixel
Value of a predetermined number of pixels in the
Specific position of reference pixel group in decoding target pixel 2
Is different from the value of a predetermined number of pixels in
When the decoding result of the pixel of interest is updated
Is the first decoding target image in the updating step.
Of a predetermined number of pixels at a specific position of the reference pixel group
Predicted value / predicted state in first memory bank determined according to value
State, and in parallel with the update,
The second decoding target pixel by the second decoding
A predetermined number of pixels at a specific position of the reference pixel group in the target pixel
The predicted value in the second memory bank determined according to the pixel value;
Decrypt method characterized by decrypt using the predicted state.