JP3227237B2 - Encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus for sequentially encoding each line of a binary image.
The present invention relates to a method of encoding using a relationship between pixels on a line to be encoded and pixels on a previous line.

[0002]

2. Description of the Related Art Conventionally, ISO / IEC (Committ)
e Draft 11544), a plurality of means for increasing the coding efficiency are sequentially executed for each image data in order, and then the prediction coding is performed by a configuration as shown in FIG. Processing is in progress.

[0003] ISO / IEC (Committe Dr)
TP for minimum resolution described in aft 11544
(Typical Prediction) will be described as an example. If the image of the line currently being encoded is the same as the entire line immediately above it, the TP for the lowest resolution encodes a flag H indicating whether or not the prediction is successful, Data is excluded from encoding. On the other hand, if the currently coded image of the line is different even by one pixel from the line immediately above, it is determined that the prediction is incorrect, and a flag indicating whether or not a hit has been obtained is coded, and the image data is coded. I do.

[0004] A conventional configuration for realizing the above processing will be described with reference to FIG. In the figure, reference numeral 100 denotes an image data storage memory, the output of which is input to a block for performing TP processing of 501, the output of which is input to a prediction flag storage memory of 502, and the output of which is output to a prediction encoder of 503. Is input and a code output o is output.

[0005] Binary image data 500 to be encoded is stored at 500. Reference numeral 501 reads out image data in pairs of two lines from 500, and if the predictions match, writes a flag indicating whether or not the prediction matches the prediction flag storage memory 502.

The prediction encoder 503 reads out the image data from 500 and the prediction flag from 502, and if the prediction matches, encodes only the prediction flag and excludes the line from the encoding target. If the predictions do not match, the prediction flag is encoded, and the pixels of the line are sequentially encoded, thereby outputting a code output o.

The above description has been made with reference to the TP as an example. However, a code output can be obtained by the same processing even in a configuration having another means for increasing the prediction efficiency and a means for performing resolution conversion.

[0008]

However, in the conventional example, the processing for increasing the coding efficiency based on whether or not the prediction matches as described above imposes a restriction on the operation time of the encoder. It was difficult to encode.

The present invention has been made in view of the above problems, and provides a main part of an apparatus configuration capable of executing coding in real time, including processing for increasing the coding efficiency. The purpose is to:

[0010]

In order to achieve the above object, an encoding apparatus according to the present invention is an encoding apparatus for sequentially encoding each line of a binary image. Means (e.g., corresponding to terminal a in this embodiment)
A first delay unit for delaying the binary image data input by the input unit by one line (corresponding to a line delay 2); and a binary image data obtained by the first delay unit for another one line. Second delay means for delaying (also corresponding to line delay 1), and n input from the input means
Using the binary image data of the line and the binary image data of the (n-1) th line obtained by the first delay means, the binary image data of the (n) th line is converted to the binary data of the (n-1) th line. Predictability determining means for determining whether or not prediction is possible from image data and outputting the determination result (similarly equivalent to TP4), and determination result delay means for delaying the determination result by two lines (also a two-line delay 5). Equivalent), and if the determination result of the n-th binary image data obtained by the determination result delay means is predictable with respect to the n-th binary image data obtained by the second delay means, Encoding means (corresponding to the encoder 3) for performing encoding if the determination result is prediction failure or not.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following embodiments of the present invention improve the coding efficiency by providing means for inputting a plurality of image data delayed one line at a time in the sub-scanning direction and means for delaying in the main scanning direction. This means that the encoder can be operated in parallel with the means for increasing the resolution or the means for performing the resolution conversion, thereby enabling real-time synchronous encoding.

(Embodiment 1) FIG. 1 is a drawing that best illustrates the features of the present invention, in which a is a terminal for inputting binary image data, and 1 and 2 delay data for one line in the sub-scanning direction. 6, 7, 8 are means for delaying image data in the main scanning direction, and 4 is TP (Typical P).
5 is a block for delaying the output of 4 by two lines in the sub-scanning direction.
Is an encoder that performs encoding based on the outputs of 1 and 5.

Hereinafter, the operation of FIG. 1 will be described in detail. In the description of this embodiment, the delay amounts in the main scanning direction of 6, 7, and 8 are set to 0.
And

The binary image data is input to a block for performing a TP process of 4 and a line delay of 2. It is assumed that the image data currently input to a is the data of the (n-1) th line. Next, when the image data of the nth line starts to be input to a, the output of the second line delay becomes the image data of the (n-1) th line delayed by one line. T of 4
The block performing the processing of P determines whether or not the image data of the nth line is predictable using the image data of the nth line and the (n−1) th line, and the determination result Fn
Is output.

The image data input to a further advances,
When the image data of the (n + 2) th line starts to be input to a, the image data of the (n + 1) th line starts to be output from 2 and the image data of the nth line starts to be output from 1. Prior to encoding the image of the n-th line, the encoder of No. 3
Since the content of the output Fn of 4 delayed by the delay means of 5 can be determined, the image data of the n-th line is coded sequentially in the case of prediction “no”, and n in the case of prediction “OK”. The image data of the line is not encoded.

If the above processing is performed on all the lines at the same time, the means for improving the coding efficiency and the encoder can be operated simultaneously, so that real-time synchronous coding can be performed.

(Embodiment 2) FIG. 2 is a block diagram of a second embodiment, in which a is a terminal for inputting binary image data, and 1, 2, and 10 are one line in the sub-scanning direction. Means for delaying minute data, 6 to 9 means for delaying image data in the main scanning direction, 4 is a block for performing TP, and 5 is means for delaying the output of 4 by two lines in the sub-scanning direction. And 11 is a unit for generating a reference pixel used as a prediction model of the third encoder.

The operation of FIG. 2 will be described below. In the description of the present embodiment, the delay amount in the main scanning direction of 7 and 8 is set to 0,
The total delay amount in the main scanning direction of 6 and 9 is determined by the number of pixels required to form 11 reference pixels and the operation timing of the encoder of 3, respectively. Is output to 11. Reference numeral 11 outputs a reference pixel for improving the coding efficiency of 2.

The TP block 4 and the encoder 3 operate in parallel according to the same procedure as in the first embodiment. The difference from the first embodiment is that when encoding the image data of the n-th line, the reference pixel can be generated in synchronization with the encoding operation.

(Embodiment 3) FIG. 3 is a block diagram of a third embodiment, in which a is a terminal for inputting binary image data, and b is a terminal corresponding to a binary image input from a. Terminals for inputting the reduced image data.
4 means for delaying one line of data in the sub-scanning direction of each image; 6 to 9, 12 and 13 means for delaying image data in the main scanning direction of each image; Is a means for generating a reference pixel 11 to be used as a prediction model for the three encoders.

The operation of FIG. 3 will be described below. The difference from the embodiment shown in FIG. 2 is that the means for improving the coding efficiency of 15 is operated using the binary image data to be coded and its reduced image, and also the reference pixels of 11 are coded. The simultaneous generation is performed using the binary image and its reduced image.

(Embodiment 4) FIG. 4 shows a configuration diagram of a fourth embodiment. In the figure, reference numeral 16 denotes means for generating reduced image data using the image data to be encoded and the already reduced image data. With this configuration, a reference image can be generated and encoded while generating reduced image data.

(Embodiment 5) FIG. 5 shows a configuration diagram of a fifth embodiment. In the figure, C is a terminal for outputting decoded image data, d is a terminal for inputting code data, 10 is means for delaying one line of data in the sub-scanning direction, 6, 9
Is a unit for delaying data in the main scanning direction, and 11 is a unit for generating a reference pixel used as a prediction model of 17 decoders.

The operation of FIG. 5 will be described below. The delay amounts 6 and 9 in the main scanning direction are assumed to have delay amounts sufficient for processing in steps 11 and 17, respectively. The code data read at d is decoded at 17 and output to C. The decoded image data is delayed by 6, 9, 10 and 11
, A reference pixel is generated, input to 17, and thereafter, the process is repeated to perform decoding.

With the above configuration, real-time synchronous decoding can be performed.

(Embodiment 6) FIG. 6 shows a sixth embodiment.
In the figure, _{100 to} 103 have a resolution of _RD > _RD-1.
>...> R ₁ > R ₀ is binary image data, and 1
04 to 107 are encoding circuits according to the configuration of the present invention;
C _D -C ₀ is the sign data of each hierarchy.

In order to simplify the description of the present configuration, a system for generating and encoding reference pixels while generating reduced images will be described. Reference numerals 104 to 106 include the same configuration as in FIG. 4, and reference numeral 107 denotes the configuration in FIG. 2 except for TP which is a means for increasing the coding efficiency.

The operation of FIG. 6 will be described below. 104
As an input the 100 image data, and outputs the reduced image 101, and outputs a code C _D. 105 is
The image data generated in step 100 is input, a reduced image is output, and the code _CD-1 is output. Below 106
The operation is repeated until the operation is completed. 107 as input image generated at 106, and outputs a code C _0.

With this configuration, all hierarchical image data can be generated in real time and synchronously encoded.

In addition, encoding can be performed without providing a storage device for storing 100 to 103 image data.

In the case of further decoding, it is needless to say that synchronous decoding can be performed with the same configuration.

(Embodiment 7) FIG. 7 shows a seventh embodiment.
In the figure, reference numerals 200 to 203 denote binary image data having at least one or a plurality of hierarchies, and 200 to 203 constitute multivalued image data represented by a color image or the like. Is a coding circuit including the configuration of FIG. 6, and CP _{, D to} CP _{, 0} are code outputs of each bit plane.

The encoding circuits 204 to 207 can synchronously encode the image of each bit plane in real time, so that the multi-valued image can be synchronously encoded in real time by operating 204 to 207 in parallel. Can be.

Further, needless to say, with this configuration, a multi-level image can be synchronously decoded in real time.

(Embodiment 8) FIG. 8 shows an eighth embodiment.
In the figure, reference numerals 300 and 303 denote image data storage means, reference numeral 302 denotes an encoding circuit constituted by the present invention, and reference numeral 301 denotes a means for storing code data.

The operation of the figure will be described below. For simplicity, it is assumed that 302 includes the encoding circuit shown in the configuration of FIG.

At step 302, binary image data to be encoded is read out from the memory 300 at a time, and the processing circuit shown in FIG.
A reduced image is generated and written into the image data storage unit 303. At the same time, a reference pixel required for encoding is generated, encoded, and written to the code data storage unit 301. The code data written in 301 is moved to another storage device or transferred to a decoding device by the host system. In this process, even if data processing such as adding a header for identifying data to the code data is added, it is needless to say that the processing is the same. When the encoding of the 300 image data is completed, the encoding is performed on the image data stored in 303 as the encoding target. The reduced image is stored in the storage unit 303, and the code data is stored in 301. By repeating this process, hierarchical encoding can be performed in real time and synchronously. Since the input binary image 302 is capable of synchronously encoding an input binary image in real time, it is possible to encode an image having the highest resolution without using a storage device. For example, a binary image read by a scanner or the like, or a binary image or the like generated by a computer or the like can be directly input from e and can be coded. If the processing is to reduce the resolution to half, 303
Is 1/4 the size of the original image,
300 is only 1/16.

(Embodiment 9) FIG. 9 shows a ninth embodiment.
In the figure, reference numerals 405 and 406 denote multiplexers,
Reference numerals 0 to 404 represent ANDs, and reference numeral 407 represents a Reset circuit. The same processing as in the configuration of FIG. 4 is performed, but the operation is performed in consideration of the following points. ISO / IEC (Committe
As described in Draft 11544), there is no actual image data at the boundary of the image data, so a dummy image must be inserted according to the boundary rule.

For the sake of simplicity, the ISO / I
A description will be given in accordance with the boundary rule described in EC (Committe Draft 11544), and it is assumed that the binary image data is composed of white and black, and white is a logical value “0” and black is a logical value “1”. .

The boundary rules are as follows. -Assume that there is a white (0) border on the left and right of the actual image. Pixel references in the stripe below the currently processed pixel shall be such that the lower side of the image is expanded as necessary down by repeating the pixels in the last line of the currently processed stripe. .

Based on the above assumptions, the operation of FIG. 9 will be described below. FIG. 10 is a timing chart showing the flow of the processing in FIG. At the start of encoding, Repeat
1, Repeat 2 selects the L side of the multiplexers 405 and 406. For simplicity of explanation, the number of lines on the high resolution side is 6, and the images of the respective lines are H1 to H6.

During the period when Repeat 1 is at “Low level”, high-resolution image data from a is input to 403,
Since i is a signal that becomes “Low level” at both ends of the actual image, the eight outputs are as shown in FIG. 10, which is equivalent to an image with white borders on the left and right, and after passing through eight delays. Used to generate reduced image data. h is
Since H1 is "Low level" until it is read from a, 7 outputs are always white while 8 outputs are H1.
It becomes “0”. Similarly, since g and f are respectively “Low level” for 2 lines and 3 lines from the beginning, outputs 8, 7, 6 and 9 are as shown in FIG.

In the figure, the encoder 3 operates for the first time when the 6 outputs are at H1, and at that time the 9 outputs are always white, so it is assumed that there is a white border right above the actual image. Processing can be performed. Repeat1 becomes "High level" after H6 is input from a. Since reference numeral 405 selects the H side, as shown in FIG.
6 is patroled. By this operation, the image of the last line can be enlarged downward, so that even if the actual image ends, the processing can be performed as if there is data below. Also, in the encoding process of the next stripe, when referring to the last line of the stripe immediately above, h,
If g and h are the same reset signals as i in FIG. 10, the processing can be performed with reference to the last line H6 of the previous stripe.

Next, the processing on the low resolution side will be described. For the sake of simplicity, a case where one low-resolution pixel is generated for a total of four pixels on the high-resolution side, in the main scanning direction 2, in the sub-scanning direction 2, and so on.

As shown in FIG. 10, when the seven outputs become H1 and the eight outputs become H2, a low resolution image L1 is generated. In the processing of the next line, L2 cannot be generated yet, so that Repeat2 becomes “High level” and 40
6 selects the H side, goes around L1 again, and 12 outputs
0. When L2 starts to be output from b, Repeat2 becomes "Low level" and 406 becomes L level.
Choose the side. Thereafter, the same operation is repeated to terminate the generation of the reduced image of L3.
The h level becomes "constant", and the circuit goes around L3. The reset in the main scanning direction is as shown by j, and the 12 outputs are eventually shown in FIG.
0.

In the above description, the image data is circulated by 405 and 406. The image data to be circulated is obtained from another output, or a plurality of multiplexing multiplexers are combined, and for example, the last two lines are repeated. It is the same invention even if it patrols.

The invention is the same even if the means 400 to 404 for generating a white image by reset operation are realized by another logic means.

[0048]

As described above, according to the present invention,
By using the configuration for the main part of the encoding device,
The image of each line can be encoded in real time, including the process of increasing the encoding efficiency based on the match / mismatch (predictability) of the preceding and succeeding lines.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a seventh embodiment of the present invention.

FIG. 8 is a diagram showing an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a ninth embodiment of the present invention.

FIG. 10 is a diagram showing a tenth embodiment of the present invention.

FIG. 11 shows a conventional example.

[Explanation of symbols]

 1, 2 line delay 3 encoder 4 TP processing unit 5 2 line delay 6, 7, 8 delay

Claims (1)

(57) [Claims] An encoding apparatus for sequentially encoding each line of a binary image, comprising: input means for inputting binary image data; and delaying the binary image data input by the input means by one line. A first delay unit, a second delay unit that further delays the binary image data obtained by the first delay unit by one line, an n-th line of binary image data input from the input unit, The second of the (n-1) th line obtained by the first delay means
A prediction possibility determining unit that determines whether the binary image data of the nth line is predictable from the binary image data of the (n-1) th line using the value image data, and outputs the determination result; A determination result delay unit for delaying the determination result by two lines; and an n-th binary image obtained by the determination result delay unit with respect to the n-th binary image data obtained by the second delay unit. An encoding apparatus comprising: an encoding unit that does not perform encoding if the determination result on data is predictable, and performs encoding if the determination result is unpredictable.