JPH0757079A - Dotting processing circuit of image processor - Google Patents

Abstract

PURPOSE:To easily enable the high speed of a series of processings of the reading of multilevel image data, the reading of a binary dot pattern and the writing of binary image data by providing a dot pattern storage part where the binary dot pattern is preliminarily stored. CONSTITUTION:A dotting processing circuit 13 is composed of a multilevel image reading circuit 14, a dot pattern reading circuit 15, a dot pattern ROM 16, a binary image writing circuit 17 and a MPX(multiplexer) 18. According to the value shown preliminarily by multilevel image data by the ROM 16, a binary dot pattern is made into a table and is stored. When this ROM 16 receives the reading address T-ADR from the circuit 15, the ROM 16 reads the binary dot pattern T-DAT of the table corresponding to the address, and the pattern is transmitted to the circuit 17. Thus, because the reading of the binary dot pattern and the writing of binary image data are made to perform a pipeline operation, the necessity of the access to an image memory 12 is eliminated for the pattern reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus using a computer, and more particularly to a halftone dot processing circuit for converting a multivalued image into a binary image.

[0002]

2. Description of the Related Art An image processing apparatus including a conventional halftone dot processing circuit is constructed as shown in FIG.

In FIG. 2, a CPU 1 comprises a microcomputer and controls a halftone dot processing circuit 3. The image memory 2 stores multi-valued image data for which halftone processing is performed, binary image data obtained as a result of halftone processing, and a binary halftone dot pattern. CPU 1 and image memory 2
And the halftoning processing circuit 3 are both address signal lines AD
R, a data signal line DAT, and a control signal line CNT are connected by a bus.

The halftone dot processing circuit 3 comprises a multivalued image reading circuit 4, a halftone dot pattern reading circuit 5, a binary image writing circuit 7 and an MPX (multiplexer) 8.

The multivalued image reading circuit 4 sequentially generates a read address R-ADR of arbitrary multivalued image data stored in the image memory 2 and a read control signal R-CNT. The read address R-ADR and the read control signal R-CNT are sent to the image memory 2 via the MPX8 and the bus.
Is supplied to.

At this time, the image memory 2 is brought into a read state by the read control signal R-CNT, and multivalued image data is read based on the read address R-ADR. The read multi-valued image data R-DAT is MP-processed via the bus.
It is sent to X8.

The halftone dot pattern reading circuit 5 is the image memory 2
The multi-valued image data R-DAT read from the MPX8
Input by switching operation of multi-valued image data R-DAT
The read address T-ADR of the binary halftone dot pattern stored in the image memory 2 and the read control signal T-CNT corresponding to the value indicated by are sequentially generated.

At this time, the image memory 2 is brought into a read state by the read control signal T-CNT, and the binary halftone dot pattern is read based on the read address T-ADR. The read binary halftone dot pattern T-DAT is sent to the MPX 8 via the bus.

The binary image writing circuit 7 converts the binary halftone dot pattern T-DAT read from the image memory 2 into MPX8.
Via a write address W-ADR and a write control signal W-CN for writing binary image data in the image memory 2 while replacing the binary image data W-DAT.
T is sequentially generated.

The replaced binary image data W-
DAT is a write address W-ADR and a write control signal W.
Image memory 2 via MPX8 and bus with CNT
Is supplied to. The image memory 2 has a write control signal W-CN.
The write state is set by T, and the write address W-AD
The secondary image data W-DAT is written based on R.

The MPX 8 sequentially switches access to the image memory 2 of the multivalued image reading circuit 4, the halftone dot pattern reading circuit 5 and the binary image writing circuit 7 based on a switching control command from the CPU 1.

Here, the binary halftone dot pattern stored in the image memory 2 uses a matrix-like pattern in order to express the gradation that the multivalued image data can have.

That is, in the halftone dot processing circuit 3 in the image processing apparatus, the multivalued image reading circuit 4, the halftone dot pattern reading circuit 5, and the binary image writing circuit 7 are sequentially stored in the image memory 2 by switching the MPX 8. By accessing, halftone processing is performed.

However, in the conventional halftone dot processing circuit as described above, the multi-valued image data is read, the binary halftone dot pattern is read, and the binary image data is written in order. There is a limit to improvement.

[0015]

As described above, in the halftone dot processing circuit of the conventional image processing apparatus, the multivalued image data reading, the binary halftone dot pattern reading, and the binary image data writing are performed. Since the processes are performed in order, the image memory must be accessed each time, and there is a limit to the improvement in processing speed.

The present invention has been made to solve the above problems, and facilitates speeding up a series of processes of reading multivalued image data, reading a binary halftone dot pattern, and writing binary image data. An object of the present invention is to provide a halftone dot processing circuit of an image processing apparatus to be realized.

[0017]

In order to achieve the above object, the present invention replaces arbitrary multi-valued image data stored in an image memory with binary image data based on a corresponding binary halftone dot pattern. In a halftone dot processing circuit of an image processing device for re-storing in an image memory, a halftone dot pattern storage unit in which a binary halftone dot pattern is stored in advance and an arbitrary multivalued image data stored in the image memory are read out. A multivalued image reading circuit, a halftone dot pattern reading circuit for reading a binary halftone dot pattern corresponding to the multivalued image data read by the multivalued image reading circuit from a halftone dot pattern storage unit, and this halftone dot pattern. A binary image writing circuit that replaces the halftone dot pattern read by the reading circuit with binary image data and writes the binary image data to the image memory, and an image memory of the multivalued image reading circuit and the binary image writing circuit. Characterized by being adapted to and a signal switching circuit for switching control access to Li.

Further, the halftone dot pattern storage unit is characterized in that the binary halftone dot pattern corresponding to the multivalued image data is stored in a table.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIG.

FIG. 1 is a block diagram showing the arrangement of an image processing apparatus including a halftone dot processing circuit according to an embodiment of the present invention.

In FIG. 1, a CPU 11 is composed of a microcomputer and controls a halftone dot processing circuit 13.
The image memory 12 includes multi-valued image data for performing halftone dot processing,
Binary image data obtained as a result of the halftone processing is stored. The CPU 1, the image memory 2 and the halftone dot processing circuit 3 are all connected by a bus composed of an address signal line ADR, a data signal line DAT and a control signal line CNT.

The halftone dot processing circuit 13 includes a multi-valued image reading circuit 4, a halftone dot pattern reading circuit 15, a halftone dot pattern ROM 16, a binary image writing circuit 17, and an MPX.
18 and.

The multi-valued image reading circuit 14 includes the image memory 1
The read address R-ADR of the arbitrary multi-valued image data stored in 2 and the read control signal R-CNT are sequentially generated. The read address R-ADR and the read control signal R-CNT are supplied to the image memory 12 via the MPX 18 and the bus.

At this time, the image memory 12 is brought into a read state by the read control signal R-CNT, and multivalued image data is read out based on the read address R-ADR. The read multi-valued image data R-DAT is transferred to M via the bus.
It is sent to the PX 18.

The halftone dot pattern reading circuit 15 MP-converts the multivalued image data R-DAT read from the image memory 12.
Input by switching operation of X8, multi-valued image data RD
Read address T-AD of the binary halftone dot pattern stored in the halftone dot pattern ROM 16 according to the value indicated by AT
R is sequentially generated.

The halftone dot pattern ROM 16 preliminarily stores a table of binary halftone dot patterns corresponding to the values indicated by the multivalued image data. Upon receiving the read address T-ADR from the halftone dot pattern reading circuit 15, the ROM 16 reads and outputs the binary halftone dot pattern T-DAT of the table corresponding to the address. This binary halftone dot pattern T-DAT is directly sent to the binary image writing circuit 17.

Here, the binary halftone dot pattern stored in the halftone dot pattern ROM 16 uses a matrix pattern in order to express the gradation that the multivalued image data can have.

The binary image writing circuit 17 is a binary halftone dot pattern T-DA read from the halftone dot pattern ROM 16.
T is input to replace the binary image data W-DAT, and a write address W-ADR for writing the binary image data in the image memory 2 and a write control signal W-CNT are sequentially generated.

The replaced binary image data W-
DAT is a write address W-ADR and a write control signal W.
-It is supplied to the image memory 12 via the MPX 18 and the bus together with CNT. The image memory 12 has a write control signal W
-Writing state by CNT, write address W
Write the secondary image data W-DAT based on ADR.

The MPX 18 sequentially switches access to the image memory 12 of the multi-valued image reading circuit 14 and the binary image writing circuit 17 based on a switching control command from the CPU 11.

In the above configuration, the operation of the halftone dot processing circuit 13 will be mainly described below. It is assumed that the image memory 12 previously stores multi-valued image data to be subjected to the halftone dot processing.

First, from the CPU 11 to the halftone dot processing circuit 13
When a start command is given to the multivalued image reading circuit 14,
Is a read address R-ADR and a read control signal R- of arbitrary multi-valued image data stored in the image memory 12.
CNT is generated and sent to the MPX 18.

The MPX 18 has a read address R-ADR.
To the address signal line ADR and read control signal RC
NT is output to the control signal line CNT, the image memory 12 connected to the bus is accessed, and multi-valued image data is read from the image memory 12. The multi-valued image data read from the image memory 12 is the data signal line DA
It is input to the MPX 18 through T. In MPX18, multi-valued image data R-DAT from the data signal line DAT
Is taken in and output to the halftone dot pattern reading circuit 15.

Then, the halftone dot pattern reading circuit 15 generates the read address T-ADR of the halftone dot pattern ROM 16 according to the value indicated by the multivalued image data R-DAT, and outputs it to the halftone dot pattern ROM 16. Halftone dot pattern ROM1
6 reads the binary halftone dot pattern T-DAT corresponding to the input read address T-ADR and directly outputs it to the binary image writing circuit 17.

The binary image writing circuit 17 includes the image memory 1
Binary image data write address W-AD to be output to
R and the write control signal W-CNT are sequentially generated, and the binary halftone dot pattern T- input from the halftone dot pattern ROM 16 is generated.
MPX by replacing DAT with binary image data W-DAT
Output to 18.

At this time, in the MPX 18, the image memory 1
2 write address W-ADR to address signal line A
The write control signal W-CNT is supplied to the control signal line C
The binary image data W-DAT is output to NT on the data signal line DAT, and the binary image data is written in the image memory 2.

By performing the above series of processing, the halftone dot processing can be performed on all the multivalued image data.

Therefore, the halftone dot processing circuit having the above-mentioned configuration stores the binary halftone dot pattern, which has been stored in the conventional image memory, in the ROM 16 in the halftone dot processing circuit 13, and the halftone dot pattern reading circuit 15 The binary halftone dot pattern is directly read from the ROM 16, and the read pattern is directly sent to the binary image writing circuit 17, so that the binary halftone dot pattern is read and the binary image data is written in a pipeline. Since it is operated, there is no need to access the image memory 12 for pattern reading, and the processing speed can be greatly improved.

In the above embodiment, the multivalued image reading circuit 14 and the image memory 12 of the binary image writing circuit 17 are used.
If there is a conflict in access to the multi-valued image data, the multi-valued image data is read with priority.

In the above embodiment, the halftone dot pattern reading circuit 15, the halftone dot pattern ROM 16 and the binary image writing circuit 17 are operated independently.

It is needless to say that the present invention is not limited to the above-described embodiments, and that various modifications may be made without departing from the scope of the present invention.

[0042]

As described above, according to the present invention, the number of times of access to the image memory can be controlled by a series of processes of reading multi-valued image data, reading a binary halftone dot pattern, and writing binary image data. It is possible to provide the halftone dot processing circuit of the image processing apparatus which can reduce the number of processing and easily realize the high speed processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image processing apparatus including a halftone dot processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image processing apparatus including a conventional halftone dot processing circuit.

[Explanation of symbols]

 1 CPU (microcomputer) 2 Image memory 3 Halftone image processing circuit 4 Multi-valued image reading circuit 5 Halftone pattern reading circuit 7 Binary image writing circuit 8 MPX 11 CPU (microcomputer) 12 Image memory 13 Halftone processing circuit 14 Multi-valued image reading circuit 15 Halftone pattern reading circuit 16 Halftone pattern ROM 17 Binary image writing circuit 18 MPX

Claims (2)

[Claims] 1. A halftoning process of an image processing apparatus for replacing arbitrary multi-valued image data stored in an image memory with binary image data based on a corresponding binary halftone dot pattern and storing the binary image data again in the image memory. In the circuit, a halftone dot pattern storage unit in which the binary halftone dot pattern is stored in advance, a multivalued image reading circuit for reading arbitrary multivalued image data stored in the image memory, and this multivalued image reading A halftone dot pattern reading circuit for reading a binary halftone dot pattern corresponding to the multivalued image data read by the circuit from the halftone dot pattern storage unit, and a halftone dot pattern read by the halftone dot pattern reading circuit. A binary image writing circuit that replaces binary image data and writes the binary image data in the image memory; access to the image memory by the multi-valued image reading circuit and the binary image writing circuit Halftone processing circuit of the image processing apparatus and a signal switching circuit for switching control. 2. The network of the image processing apparatus according to claim 1, wherein the halftone dot pattern storage unit stores a binary halftone dot pattern corresponding to the multi-valued image data in a tabular form. Pointing processing circuit.