JPH11328006A - Address control circuit for memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an address control circuit which has a small circuit scale and is easy in operation control by providing an address control part which generates and outputs address bits assigned to every group and another address control part which generates and outputs address bits assigned to every sector in groups. SOLUTION: A storage part 110 is used by dividing a storage area into three groups 1 to 3. A 1st address control part 121 generates and outputs address bits assigned for every groups. A 2nd address control part 122 generates and outputs address bits assigned to every sectors in the groups 1 to 3. Thus, even when the storage area is divided into >=2 groups 1 to 3 and used, the address control can be performed and simplified by the two address control parts 121 and 122. Further, since no selector is needed, the circuit scale can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address control circuit used for a memory device such as a dual port memory.

[0002]

2. Description of the Related Art A memory device of a type in which a storage area is divided into a plurality of groups and used is known.
As such a memory device, for example, there is a dual port memory or the like.

FIG. 3 is a block diagram schematically showing a configuration example of a conventional memory device.

As shown in FIG. 3, a storage area 310 is used by dividing a storage area into three groups 1, 2, and 3. Each of the groups 1 to 3 includes, for example, 256 sectors.

[0005] The address control unit 321 generates an address AD for writing and reading to / from the group 1 of the storage unit 310. Similarly, the address control unit 322 generates an address AD for performing writing / reading on the group 2, and the address control unit 323 generates an address AD for performing writing / reading on the group 3.

[0006] The selector 324 includes an address control unit 321.
323 to select one of the addresses AD output,
The data is sent to the storage unit 310 via the address bus 360.

The read / write control unit 330 reads / writes
A write signal R / W is generated and sent to the storage unit 310 via the signal line 370.

[0008] When the signal R / W is "read", the data processing section 340 inputs the data D output from the storage section 310 from the data bus 380 and performs a predetermined arithmetic processing.
On the other hand, when the signal R / W is “write”, the data bus 3
The write data is supplied to the storage unit 310 via 80.

[0009] The chip selector 350 sends a chip select signal CS to the storage section 310 via a signal line 390.

According to the memory device as shown in FIG.
Separate address control units 32 for groups 1, 2 and 3
Since 1 to 323 are provided, for example, a process of performing reading from a sector belonging to group 1 and reading from a sector belonging to group 2 and then performing writing to a sector belonging to group 3 is repeatedly executed. In such a case, the processing speed can be increased.

[0011]

However, the memory device as shown in FIG. 3 requires the same number of address control units as the number of groups in the storage unit 310 and the number of selectors 324. However, there is a disadvantage that the size of the image becomes large.

Also, when the number of bits of an address increases with an increase in the storage capacity of the storage unit 310 (that is, when the number of signal lines of the address bus increases), each of the address control units 321 to 323 and the selector 324 can be used. Circuit scale increases.

Further, the above-described processing of performing reading from a sector belonging to group 1 and reading from a sector belonging to group 2 and then performing writing to a sector belonging to group 3 is repeatedly executed. In the case, each of the address control units 321 to 323 and the selector 3
There is also a disadvantage that the operation control of the H.24 becomes very complicated.

For these reasons, the circuit scale is small,
In addition, an address control circuit that is simple in operation control has been desired.

[0015]

SUMMARY OF THE INVENTION The present invention relates to an address control circuit for a memory device which divides a storage area into a plurality of groups each consisting of a plurality of sectors and uses them.

A first address control unit for generating and outputting address bits assigned to each group, and a second address control unit for generating and outputting address bits assigned to each sector in the group And

According to such a configuration, even when the storage area is divided into three or more groups and used, the address control can be performed by the two address control units, and no selector is required. Thus, the circuit scale can be reduced.

Since the generation of the address bits allocated to each group and the generation of the address bits allocated to each sector are performed separately, the address control can be simplified.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement of each component are only schematically shown to an extent that the present invention can be understood, and numerical conditions described below are merely examples. Please understand that.

FIG. 1 is a block diagram schematically showing a configuration of a memory device equipped with an address control circuit according to this embodiment.

As shown in FIG. 1, the storage unit 110 is used by dividing a storage area into three groups 1, 2, and 3. In this embodiment, each of the groups 1 to 3 has 256 sectors (not shown).

In this embodiment, the address of each sector belonging to group 1 is 000h to 0FFh,
The address of each sector belonging to group 3 is 100h-1FFh, and the address of each sector belonging to group 3 is 200h-2F.
Fh. That is, the sector whose first digit of the address is 0h belongs to group 1, the sector whose first digit of the address is 1h belongs to group 2, and the sector whose first digit of the address is 2h belongs to group 3. On the other hand, the last two digits of the address are assigned to each sector in the same group.

The first address control section 121 generates and outputs address bits (that is, the first digit of the address) assigned to each group. In this embodiment, since the use by dividing the storage area of the storage unit 110 into three groups, the address value AD ₁ of the first address control unit 121 generates may be 2 bits. Therefore, only the upper two bits of the address bus 160 (10 bits) are used for transmitting an address from the first address control unit 121 to the storage unit 110.

The second address control unit 122 generates and outputs address bits assigned to each sector in groups 1 to 3. In this embodiment, since the number of sectors in each group 1-3 is a 256 respectively, the address AD ₂ of the second address control unit 122 generates is 8 bits. Therefore, the address transmission from the second address control unit 122 to the storage unit 110 requires the address bus 1
The lower 8 bits of 60 are used. As the second address control unit 122, for example, an up counter can be used.

The read / write control unit 130 reads / writes
A write signal R / W is generated and sent to the storage unit 110 via the signal line 170.

When the signal R / W is "read", the data processing section 140 inputs the data D output from the storage section 110 from the data bus 180 and performs a predetermined arithmetic processing.
On the other hand, when the signal R / W is “write”, the data bus 1
The write data is supplied to the storage unit 110 via 80.

The chip selector 150 sends a chip select signal CS to the storage unit 110 via a signal line 190.

Next, an operation example of the memory device shown in FIG. 1 will be described with reference to FIG. The operations of the units 121, 122, 130, and 140 described below are controlled by, for example, a CPU (Central Processing Unit) not shown.

Firstly, it sets the output value AD ₁ of the first address control unit 121 to 0h, to set the output value AD ₂ of the second address control unit 122 to 00h (S20
1).

Thereafter, when the output R / W of the read / write control unit 130 is set to “read” (S202), the data D at address 000h (ie, the first data of group 1) is transferred from the storage unit 110 to the data bus 180. Is output. The data processing unit 140 inputs the data D from the data bus 180 (S203).

Next, the output value AD1 of the _first address control unit 121 is set to 1h (S204). At this time, the output value AD2 of the _second address control unit 122 remains at 00h.

Thereafter, when the output of the read / write control unit 130 is set to "read" (S205), the storage unit 11
Data D at addresses 0 to 100h (ie, the first data of group 2) is output to data bus 180. The data processing unit 140 inputs the data D from the data bus 180 (S206).

Next, the output value AD1 of the _first address control unit 121 is set to 2h (S207). At this time, the output value AD2 of the _second address control unit 122 remains at 00h. Subsequently, the data processing unit 140 outputs the write data D to the data bus 180 (S20).
8).

Thereafter, when the output of the read / write control unit 130 is set to “write” (S 209), the storage unit 11
Data D (that is, the first data of group 3) is written to address 0h 200h.

Subsequently, the output value AD _{2 of} the second address control unit 122 is compared with the value “FFh” (S 210).
Then, when these values do not match, increasing the output value AD ₁ of the first address control unit 121 and sets the 0h, an output value AD ₂ of the second address control section 122 by "1h" (S211). Here, S2
10, the output value AD of the second address control unit 122
_{Since 2} is 00h, the output value AD ₂ of the second address control unit 122 is “01h” by executing S211.
Becomes

After that, the processes after S202 are executed again. These S202~S211 the output value AD ₂ of the second address control unit 122 is a value in S210 "F
Fh ”is repeated.

In S210, the second address control unit 1
Output value AD ₂ of 22 when a FFh, a series of processing ends.

As described above, according to the memory device of this embodiment, the address control is performed by the two address control units although the storage area is divided into three groups 1 to 3 and used. Since no selector is required, the circuit scale can be reduced.

The first address control unit 121 specifies a group of storage areas, and the second address control unit 122
, The address control can be simplified, and the data can be arranged regularly so that the data can be easily handled.

Although the case where there is only one storage unit 110 has been described here, the present invention can be applied to a memory device having two or more storage units. In this case, the storage section may be switched by switching the chip select signal CS output from the chip selector 150.

[0041]

As described above in detail, according to the present invention, it is possible to provide an address control circuit having a small circuit scale and easy operation control.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of a memory device equipped with an address control circuit according to an embodiment.

FIG. 2 is a flowchart for explaining an operation of the address control circuit according to the embodiment;

FIG. 3 is a block diagram schematically showing a configuration example of a conventional memory device.

[Explanation of symbols]

 Reference Signs List 110 storage unit 121 first address control unit 122 second address control unit 130 read / write control unit 140 data processing unit 150 chip selector 160 address bus 170, 190 signal line 180 data bus

Claims (2)

[Claims] 1. An address control circuit for a memory device, which divides a storage area into a plurality of groups each including a plurality of sectors, and generates and outputs address bits assigned to each group. And a second address control unit for generating and outputting address bits assigned to each of the sectors in the group, the address control circuit for a memory device. 2. The address control circuit according to claim 1, wherein the second address control unit is an up counter or a down counter.