JPS63208956A - Picture processor - Google Patents

Abstract

PURPOSE:To process picture at a high speed by performing the parallel operations between an address calculation means for original pictures and another calculation means which calculates an address storing an arithmetic result. CONSTITUTION:A memory 100 includes an original picture area 105 where the original picture data are stored and a result area 106 where the picture processing arithmetic results are stored. The data on the area 105 are successively read out and stored in the area 106 after undergoing an arithmetic operation. An original picture reading part 110 calculates an address of the area 105 to be read out and reads out the data on the corresponding address via an address data bus 103. This read-out data is processed by a data arithmetic part 130 and sent to a result storing part 120. The part 120 calculates the address of a result area to store data and writes the address via an address data bus 103. The addresses of both parts 110 and 120 are calculated in parallel with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image processing device that speeds up image processing through parallel processing.

BACKGROUND OF THE INVENTION When an image is stored in a storage device of a computer and processed, the task of calculating the address of each pixel forming the image frequently occurs.

FIG. 6 shows the correspondence between the position of each pixel constituting an image on the two-dimensional image plane and the address on the storage device where the image is stored.

In the figure, 601 is a two-dimensional image, and 602 is a storage device.

The two-dimensional image 601 consists of N words horizontally and M rows vertically, and for the sake of simplicity, it is assumed that one word is 16 bits and one pixel is one pit. That is, the two-dimensional image 601 consists of 16XNXM binary pixels.

It is assumed that the storage address of each pixel increases from left to right and from top to bottom. That is, if the address of the word at the upper left corner is A, the address of the word next to it on the right is A+1. The address of the rightmost word in the top row is A+N-1. Also, the addresses of the word at the bottom left and the word at the bottom right are A+N (M-
1), A+MN-1.

FIG. 7 is for explaining the addresses of pixels constituting an arbitrary rectangular area in the image area as described above.

In the figure, 701 and 702 correspond to 601 and 602 in FIG. 6, respectively. If the size of the rectangular area 703 is L words and XH lines, and the address of the upper left end is B, then the address of the word at the upper right end is B+L-1, and the address of the word immediately below B is B+N.

Also, the addresses of the words at the bottom left and bottom right are B+(
H-, 1) N, B+ (H-1) N+L-1.

On the other hand, if the size of the rectangular area 705 is also L words x H lines, and the address of the upper left corner is C, then the address of the word at the upper right corner is O.
+L-1, the address of the word immediately below O is O+N. Also, the at L/S of the words at the bottom left and bottom right are O+, respectively.
()(-1)N, O+ (H-1)N+L-1.

An example of a conventional image processing apparatus that processes information of an image area to which addresses are assigned as described above is shown in FIGS. 8 and 9. In FIG. 8, 800 is an image memory;
803 is an address data bus. 805 and 806 are an original image area and a result area, respectively, and correspond to rectangular areas 703 and 705 in FIG. 7, respectively. 810
is an image processor, 811 is an address line, and 812 is a data line. In such a device, the original image area 805
Copying the image into the result area 806.

By way of example, the operation of the apparatus of FIG. 8 will now be described.

This operation can be performed by repeating the following two-step operation. That is, (first stage) the image processor 810 calculates the address of one word in the original image area 805, and stores the address in the storage device 800.
It is output via address line 811 and address data bus 803. The storage device 800 outputs the content (data) of the word at this address, and this data is sent to the image processor 81 via the address data bus 8o3° data line 812.
Transferred to 0. (Second stage) Image processor 810
is the result area 80 where the read data is to be stored.
6 is calculated, and this address is transferred together with the read data to the storage device 800. Storage device 8
00 writes this data to the specified address.

By repeating the above two steps for each address in the original image area, the contents of the original image area 805 are copied to the result area 806.

The operations in each of the above steps will be explained in more detail as the operation of the apparatus shown in FIG. FIG. 9 shows the image processor 810 of FIG.
shows the internal structure of In the figure, 914 is an address register (A
R), 919 is a data register (DR), 913, 91
5,918 is an internal data bus. 916 is a register file, and 917 is an arithmetic unit. 920 is a control unit, 9
30 is a data processing section. Registers SA and DA in register file 916 hold the addresses of corresponding words in the original image area and result area, respectively. Further, the register W holds the width of the image area, that is, the numerical value N in FIG. 7, and the register E holds the numerical value 1.

The operation of the first stage is as follows. That is, the control section 9
20, the value held in the register SA is the original image area 80.
Check whether it is the rightmost address of 5. If it is the address of the rightmost word, the contents of register W are added to the contents of register SA, otherwise the contents of register E are added to the contents of register SA, and the result is stored in register SA. In this operation, the contents of register SA are output to bus 913, the contents of either register W or register E are output to bus 918, these values are added by arithmetic unit 917, and the result is output to bus 915. via Register S
It is executed by writing to A again.

As a result of the above operations, the register SA that was specifying a word in the original image area will change the word to the right of that word, or if that word is the rightmost word, the leftmost word below the - column. I will give instructions. Thereafter, the control unit 920 transfers the contents of the register SA to the address register 914, reads the contents of the main memory, and stores the read data in the data register 919 via the data line 912. This completes the first stage operation.

The operation of the second stage is as follows. That is, the control section 92
0 performs the same operation on the contents of register DA as it did on register SA in the first stage. As a result, the word in the result area indicated by register DA is moved to the right neighbor or to the leftmost end. Next, register DA
The contents of are transferred to the address register 914 and stored in the storage section 92.
Write the contents of data register 919 to 0. Since the data register 619 stores the word of the original image area read out in the first step, the copying of the - word is now complete.

Above 1st. By repeating the second two steps, the contents of the original image area can be copied to the result area. A data processing unit 930 performs appropriate processing on the contents of the data register 919 between the first and second stage operations.
It is also possible to perform a specific image operation on the original image area and store it in the result area by inserting an operation to perform the calculation and store it in the data register 919 again.

Problems to be Solved by the Invention FIG. 10 is a timing chart of the operation of the conventional device described above. In the figure, SA is the address calculation of a word in the original image area, and RD is the time of the read operation of the word. SA and RD constitute S1, that is, the operation of the first stage described above. P corresponds to data processing, and the above-mentioned first and second
Corresponds to the middle operation (S m) of the stage. DA corresponds to the address calculation of the word in the result area, and WT corresponds to the operation of writing data to the word, and both constitute 82, that is, the second stage operation described above.

As can be seen from the above, it is necessary to execute SA, RD, DA, and WT in series in this order, and conventional image processing apparatuses have the disadvantage that processing speed cannot be improved.

In view of the problems of the prior art described above, the present invention aims to significantly shorten the overall processing time and to simplify the software.

Means for Solving the Problems The present invention provides an image storage means for storing an image, and an original image address calculation means for calculating the address of a word in an original image area that is a part of the image stored in the image storage means. and,
Result address calculation means for calculating the address of a word in a result area defined in the image storage means is provided, and the original image address calculation means and the result address calculation means operate in parallel, The content of the original image area is transferred to the result area.

According to the above configuration, the present invention reduces the processing time by simultaneously performing the address calculation and read operation of the word in the original image area, the data operation for the read word, and the address calculation and write operation of the word in the result area. The whole thing can be shortened.

! Furthermore, since the calculation of the read address of the original image area and the calculation of the write address of the result area use hardware having the same structure, the hardware becomes simple.

Embodiment FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention. In FIG. 1, 100 is a storage device;
103 is an address data bus, 105 is an original image area, 1
06 is a result area corresponding to each component 800 to 806 in FIG. 8, respectively. Reference numeral 110 denotes an original image reading unit for reading out the original image in the original image area 105 in the storage device 100;
1 is its address line, and 112 and 113 are its data lines.

120 is a result storage unit, 121 is an address line, 122°1
23 is a data line. 130 is the original image reading unit 110
This is a data calculation unit that processes data transferred between the data storage unit 120 and the result storage unit 120. In this system, the original image address calculation and the result address calculation are executed independently in the original image reading section 110 and the result storage section 120, respectively, so they can be processed simultaneously and the overall processing efficiency can be improved. can.

FIG. 2 is a block diagram showing a specific embodiment of the original image reading section 110 shown in FIG. In Figure 2, 211
．． 212. and 213 are 111 and 213 in FIG. 1, respectively.
These are address lines and data lines corresponding to 112 and 113. 214 is an address register, 215 and 216 are selectors, and 217 is an adder. A word register 218 holds a value obtained by subtracting the number of words in the width of the original image area O from the number of words in the width of the entire image space, that is, N-L+1. 219 is a data register, and 220 is a control unit.

In the configuration shown in FIG. 2, the address calculation of the word to be read out in the original image area and the readout operation are performed. That is,
Only the first stage of operation in image processor 810 of FIG. 8 is performed.

This operation looks like this: That is, first, the control unit 220 controls the selector 216 depending on whether the content of the address register 214 is the rightmost word of the original image area. If the content of the address register (AR8) 214 is the address of the rightmost word, the content of the word register (WB2) 218 is selected; otherwise, the number 1 is selected, and the adder 2
17. Therefore, the output of the adder 217 is AR8+N-L+1 in the former case, and AR8+1 in the latter case, which is stored in the address register (AR8) 214. After that, the control unit 220 issues a read command to the storage device 100, and reads the address register (AR8).
The contents of 214 are output to the address line 211. As a result, the content of the read word is transferred from the storage device 100 and sent to the data register (DBS) via the data line 212.
) 219.

FIG. 3 is a block diagram showing a specific embodiment of the result writing section 120 shown in FIG. In Figure 3, 311
-320 are the same as 211-220 in FIG. 2, respectively.

That is, in FIG. 3, 311, 312° and 31°
3 are address lines and data lines corresponding to 122, 121 and 123 in FIG. 1, respectively.

314 is an address register, 315 and 316 are selectors, and 317 is an adder. A word register 318 holds a value obtained by subtracting the number of words in the width of the original image area from the number of words in the width of the entire image space, that is, N-L±1. 3
A data register 320 19 is a control section. This third
The configuration shown performs only the address calculation of the word to be written in the result area and the write operation to that word - ie, the second stage operation in image processor 810 of FIG.

Among these operations, the address calculation operation is the same as the address calculation operation explained using FIG. However, the contents of address register (ArtD) 314 indicate one word in the result area.

After completing the address calculation, the control unit 320 outputs the contents of the address register (ARD) 314 to the address line 311, outputs the contents of the data register (DRD) 319 to the data line 313, and issues a write command to the storage device 100. emits. This completes the second stage operation.

The data calculation unit 130 in FIG. 1 corresponds to the data processing unit 930 that performs data processing that should be inserted between the first and second stage processing in the conventional example. This calculation section 13
0 performs predetermined arithmetic processing on data input from the data line 113 and outputs the result to the data line 122. For processing that merely copies the contents of the original image area 105 to the result area 106, the data lines 113 and 122 may be directly connected, and the data calculation unit 130 is not necessary.

FIG. 4 is an operation timing chart of the configuration shown in FIG. In FIG. 4, 401, 402. and 403 are the original image reading section 110 and the data calculation section 13 in FIG. 1, respectively.
0, and the result storage unit 120 is operating. S A n and RDn of 401 correspond to the read address calculation operation of the n-th word and the read operation of that word, respectively. Pn of 402 corresponds to the data processing operation of the nth word.

D A n of 403 and WTn correspond to the write address calculation of the nth word and the write operation to that word, respectively.

As is clear from FIG. 4, the original image reading section 1 in FIG.
10. Result storage unit 120. The data calculation unit 130 and the data calculation unit 130 can operate simultaneously, and the processing speed can be increased compared to the conventional example.

Incidentally, if the data calculation section 130 of FIG. 1 is not present and only the data within the area is to be copied, then Dn and DAn can be executed at the same time, and 110 and 120 can also operate at the same time.

The apparatus of FIG. 5 has separate storage devices 500. and 501 is another embodiment of the present invention. In the figure, 500 to 530 correspond to 100 to 130 in FIG. 1, respectively. In such an apparatus, the reading operation and writing operation of the storage devices 500 and 501 can be executed simultaneously, so the original image reading section 510,
The degree of freedom in parallel operation of the result storage unit 520 and data calculation unit 530 is further increased.

Effects of the Invention As described above, the present invention performs the address calculation and read operation of words in the original image area, the data operation for the read words, and the address calculation and write operation of words in the result area at the same time.
can be executed at the same time, reducing the overall processing time.

Further, the calculation of the read address of the original image area and the calculation of the write address of the result area can use hardware having the same structure, which has great effects such as simplifying the hardware.

[Brief explanation of the drawing]

FIG. 1 is a block wiring diagram of an image processing device according to an embodiment of the present invention, FIGS. 2 and 3 are block wiring diagrams of main parts of the same device, FIG. 4 is an operation timing chart of the same device, and FIG. 5 is a block diagram of an image processing device according to another embodiment of the present invention; FIGS. 6 and 7 are conceptual diagrams showing the correspondence between pixel positions and addresses in a conventional image storage device; FIG. 9 is a block diagram of a conventional image processing device, and FIG. 10 is an operation timing chart of the same device. 100...Storage device, 105...Original image area, 10
6...Result area, 110...Original image reading unit, 12
0...Result storage unit, 130...Data calculation unit. Name of agent: Patent attorney Satoshi Nakao, male and 1 other person Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (7)

[Claims] (1) an image storage means for recording an image; an original image address calculation means for calculating the address of a word in an original image area that is a part of the image stored in the image storage means; and a result address calculation means for calculating the address of a word in the result area defined in the original image area, and the original image address calculation means and the result address calculation means operate in parallel to An image processing device characterized in that the content is transferred to the result area. (2) The address calculation means calculates the address of a word in the original image area and performs a read operation on the word, and the result address calculation means calculates the address of a word in the result area and performs an operation to write data to the word. An image processing apparatus according to claim 1, characterized in that the image processing apparatus performs the following operations. (3) The result address calculation means calculates the total addresses in the result area in the same order as the order of the words in which the original address calculation means calculates the addresses. Image processing device. (4) The image processing device according to claim 1, wherein the original image area and the resultant area have the same size. (5) The image processing device according to claim 1, wherein the original image area and the resultant area are rectangular. (6) The original image address calculation means has a first register that holds an address of a word in the original image area, and a second register that holds a specific value to be added to the first register, and 2. The image processing apparatus according to claim 1, wherein the address of a word in the original image area is calculated by adding the content of the second register or 1 to the content of the first register. . (7) A patent claim characterized in that the same procedure as the calculation procedure of the address of a word in the original image area is executed in a result address calculation means for calculating the address of a word in the result area. The image processing device according to scope 1.