JPS6340972A - Memory control system - Google Patents

Abstract

PURPOSE:To execute a processing in a memory at high speed by providing a storage element having a prescribed bit array, a prescribed address converting circuit, and the rotary circuit of a bit position, designating an address non-conversion, and a non- conversion or a conversion at the time of write and at the time of read-out, respective ly, and executing a memory access in a new direction. CONSTITUTION:Numbers 0-15 are given to each bit in a logical memory space and said bits are arrayed in memory elements #0-#3, and the bit position of the element is allowed to correspond in one-to-one to the bit position of the memory space. At the time of write to a memory 10, when an address bus AD is A1=0 and A0=0, D0-D3 on a data bus DA are not rotated 20 but sent to a memory 10, and addressed to '0' address by a address converting circuit 40. When A0 and A1 are changed, said D0-D3 are rotated 20 by a prescribed bit and addressed. At the time of read-out, when the bus AD is A1=A2=0, the converting circuit 40 gives an address of '0' address to all of the memories #0-#3 and reads it out without executing a rotation 30, and thereafter, reads it out by executing an rotation 30 with a prescribed bit, when A1 and A2 are changed. According to this constitution, and access can be executed from plural directions and write and read-out can be operated two-dimensionally at high speed.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a memory control method used by a processor or the like in a computer system, and in particular, when reading and writing data to and from memory, the present invention The present invention relates to a memory control method that allows memory access in multiple directions.

(Prior Art) Conventionally, when a processor or the like reads and writes data to a memory, it can only access in one dimension with the n-bit width of the memory data bus.

Various types of data such as programs and numerical data are stored in memory, but when performing two-dimensional full processing such as character patterns, it may be necessary to process data in a dimensional direction different from the conventional access direction. be.

For example, as shown in FIG.
Full rotation of character string of nXn bits and reading,■,■
, ■ (n bits each) in order to be transferred to the output device 6Q. Conventional methods for performing this processing include a program control method and a method in which a buffer memory for data conversion is added to the memory to perform the processing in a computer-like manner. First, in order to process it under the program control of the processor, nXn
The focused data is read out, rotated and bit operations are performed to create n-bit output data. In this way, program control requires time for arithmetic processing and the like, so the following data conversion buffer memory IJ2 is often added. The function of this backup memory is to read nxn bit data from the memory, store it in the buffer memory, and then output all n bit data as shown in Figure 7 by controlling the buffer address and data bus. .

By equipping such a buffer memory.

(Problem to be solved by the invention) However, in the former program-controlled method, the above-mentioned arithmetic processing takes time, and in the latter, the data conversion buffer memory IJk is omitted. Even with the method of adding data, n times of memory reading is required to output n bits of data, so there is still a problem that the speed cannot be increased.

The entire purpose of the present invention is to enable memory access in a new access direction in addition to the normal memory access direction, and to process data in the memory at high speed.

(Means for Solving the Problems) The present invention provides a memory element having a full n AXI bit configuration (A is address capacity) and a predetermined bit arrangement, and a Book (however, 2” =
n) An address conversion circuit that receives ffi input and performs address conversion according to address conversion/non-conversion designation, and an address conversion circuit that is provided between a data line and the storage element, and one of the address lines of the storage element. The rotation circuit rotates all the bit positions of input data in a predetermined direction by a predetermined amount determined according to the address of the input data and outputs the rotated data.

When writing data to the storage element, the address conversion circuit is designated with no conversion of the address, and when reading data from the storage element, the address conversion circuit is designated with no conversion or conversion of the address. .

(Operation) Each of the n memory elements has a predetermined pit arrangement. For example, when n=2, the logical memory space for the table has the focus arrangement of table B. However, the numbers in the table have data numbers.

Table A Table B If you access the logical memory space for the table in the column direction and read the data, two bits each will be set to "1" starting from the lower bit.
The data is read as "0°", "3", °"2" and 5
If accessed in the row direction, “2” is accessed from the lower bit,
00'', pa3'', and ``1'' are read out. In the present invention, two accesses to the logical memory space in the row direction and column direction are performed by arranging data as shown in Table B.

Let us now assume that the right-hand column of Table 1 B is the memory element M1, and that all the left-hand columns are memory elements M2. Also, the addresses are sequentially O in the column direction.
The address shall be number 1. When n==2, one of the address lines (this is called ThAO) is given to the address conversion circuit.

Now, let us consider reading data when no address conversion is performed. First, when AO is at address 0, the address translation circuit gives address 0 to M1 and M2 without performing address translation. Therefore, from M11M2, “1” and “
0" is read and given to the rotation circuit.AO
When the address is 0, the rotation circuit does not rotate the data. Therefore, on the data line, “
'1''.

“0” is output. Next, when AO becomes address 1, this address is given as is to M1 and M2, and "2" M31J is read out and given to each of them by the rotating circuit. When AO is at address 1, the rotation circuit loads only one bit in the lower bit direction and outputs it. Therefore 2″.

"3" is rotated as 3 and then "2" and output on the data line.In this way, the logical memory space of Table A?
The same data is obtained on the data line as when data is read by accessing in the column direction.

On the other hand, consider reading data in the case of address translation - when AO is at address 0, the address translation circuit just gives address ``40'' to Ml.

For Ml, the address is converted and address 1 is given.

Therefore, "2" and -10" are read from M1 and M1, respectively, and are applied to the rotation circuit.

When AO is at address 0, the rotation circuit does not rotate all data. Therefore, 2" and "0" are output to the data line in order from the lower bit. Next, when AO becomes address 1, the address conversion circuit gives Ml the address 1 as is, but Ml Convert address and give address O?

Therefore, Ml.

``1'' and ``3'' are respectively read from Ml and given to the rotation circuit. When AO is at address 1, the rotation circuit rotates all the data by 1 bit in the direction of the upper bit and outputs the data. On the line, 3゛° and "1" are displayed in order from the lower bit.

is output. In this way, the same data is obtained on the data line as when data is read by accessing all rows of the logical memory space of Table 1A.

On the other hand, data is written without address conversion.
Data is always arranged as shown in Table B. In this case, the rotation circuit rotates by a predetermined amount (when AO is at address 0, it does not rotate; when AO is at address 1, it rotates by 1 bit) in the lower focus direction according to the address value of AO.

(Example) Before explaining the implementation 11 of the present invention, 1. An outline of the memory access method according to the present invention will be explained.0 Fig. 2 is a diagram for explaining the outline of the memory access method according to the present invention. be. As shown in Figures (al and bJ), there are two ways to access the memory. The access method shown in Figure (al) (hereinafter referred to as the first access method) The memory space in the row direction specified by each address in the column direction is accessed sequentially to write data on the external data bus 80 and read data to the external data bus 80. The access method shown in b) (hereinafter referred to as the second access method) accesses the terms in all rows of the memory space of the memory 70, and externally accesses the memory space in the column direction specified by each address in the row direction. Data is written on the data bus 80 and data is read from the external data bus 80.In this way, the memory access method according to the present invention enables two-way memory access, and stores two-dimensional data in the memory. High-speed processing is possible when processing with

Next, one embodiment of the present invention will be described.

FIG. 1 is a block diagram of an embodiment of the present invention. In this embodiment, the aforementioned n is 4. In the same figure, A
D is an address bus (address capacity tA) from a processor (not shown), which is 1, and from the lower bits AO, At, A2
,... are given signal names. DA is a data bus consisting of four data lines, starting with the lower bits Do, D
The signal names l, D2, and D3 are given. 10 is a memory consisting of four memory elements, #o from the lower bit element.

Element numbers #L, #2, and #3 are given.

Each memory element has an AXI pin (A is address capacity) configuration. Reference numerals 30 and 30 indicate low data provided at the connection portion between the data bus DA consisting of four data lines and the memory input/output data line 10a of each memory element #O to #3. Low data 20 is the lower 2 bits AO on address bus AD
, A1, the data on the data bus DA is rotated by an arbitrary m pinot (m=0 to n-1, n=4 in this example), and the memory input data of the memory input/output data line 10a is feed the line. raw data 30
converts the data on the memory output data line of the memory input/output data line tOa to arbitrary m bits (m
Rotate by = 0 to n-1, n = 4 in this example,
Supplied to data bus DA. 40 is an address conversion circuit which converts the upper (7) lower 2 bits of the address bus AD, AO, A
t and a signal (supplied from the processor) specifying conversion/non-conversion of addresses AO and AI, and supplies the lower two bits of the address to each memory element #0 to #3. The remaining address bits A2. A3... is directly supplied from the processor to each memory element #0 to #3. 1st
The table shows all the relationships between the inputs and outputs of the address conversion circuit 40.

Here, the bit arrangement of each memory element #0 to #3 will be explained. Figure 3 (fat) shows the bit array of the logical memory space when processing 4x4 pinto data, and Figure 3 (b) shows the memory element #0 corresponding to this logical memory space.
The bit arrangement of ~#3 is shown.

In the same figure (al), addresses 0, 1, 2, 3, etc. in the column direction are for the first access method (second access method).
In the memory addresses in Figure (a), addresses 0, 1, 2, and 3 in the row direction are used when using the second access method described above (
The memory address in FIG. 2(b)) is shown.

Further, numbers 0 to 15 in Figure 1 are numbers assigned to each bit in the logical memory space. Each bit in such a logical memory space is assigned to each memory element # as shown in FIG. 3(b).
Arranged in numbers 0 to #3 (physical arrangement). The bits of each memory element correspond L to 1 to the focus between logical memory 'J2's. For example, data "4", 15" at address 1 in the first access method.

6" and "7" are memory elements #2, #1 and #0, respectively.
, #3 is the data at address 1.

Next, the operation of this embodiment will be explained separately for the first access method and the second access method.

First, the operation in the first access method will be explained. When the first access method is fully executed, a no-conversion designation is given to the address conversion circuit 4.

And data Th to memory 0! The action of digging in is the fourth
This is done as shown in the figure. First, the lower two bits of the address on the address bus AD are AL=O.

When AO=O (FIG. 4(a)), data DO on data bus DA="3", Dl="2", 1)2. ==”
“1”.

D3="0" is supplied to memory 0 without being rotated when raw data is added. At this time, the address conversion circuit 40 converts memory elements #0 to #3 as shown in Table 1.
The address of address 0 (A1=0°AO=0) is given to all of them. Therefore, 4-bit data "3°" is supplied from the raw data addition.

“2′, uii, and “0” are memory elements #O and
It is stored in the area specified by address 0 of #l, #2, and #3. Next, the lower two bits of the address are Al=O,
When AO=1 (Fig. 4 (bl), data bus D
Data on A ``7'', ``6'', 5''.

“4&’ is raw data 20 and only 1 bit D3→D2→
It is rotated in the direction of D1→DO+D3 and output to memory elements #0 to #3. At this time, the address conversion circuit 40 converts the address 1 (
A l=0, AO=1) address is given.

Therefore, the data ``6'' output from the raw data addition
u 511 , II 4", 17" are memory elements #: 0, -31, !, respectively. It is stored in the area designated by address 1 of +-2 and #-3. Next, when the lower two bits of the address become A 1 = l and AO = O (Fig. 4 fC
)), data “11” on data bus DA.

"10", "g ii , and u Bu are rotated by 2 bits in the same direction as the previous direction by raw data redundancy, and are output to memory elements #0 to #3. At this time.

The address conversion circuit 40 gives the address of address 2 (A1=1, AO=O) to all memory elements #0 to #3. Therefore, the data output from the raw data mark “
9'', ``8'', ``11'', and ``10'' are respectively stored in the areas specified by the 2nd addresses of memory elements #O, #11, #2, and #3.Next, the lower two bits of the address When Al=1 and AO=1 (FIG. 4(d)), data "15" on data bus DA.

“14”, “13”, “12°° are raw data 20
3 bits are rotated in the same direction and output. At this time, the address conversion circuit 10 converts the address 3 (A1=1°AO=
1) Give the address. Therefore, data “12” and “15” are output from the raw data 20.

"14" and "13" are stored in the areas specified by the three addresses of memory elements #O, #1, #2, and #3, respectively. Thereafter, data on data bus DA is processed in the same manner.

On the other hand, data is read from the memory 10 using the first access method nine times as shown in FIG. First, the lower two bits on address bus AD are AI=O, AO
In the case of =O (FIG. 5(a)), the address conversion circuit 40 gives the address of address 0 to all memory elements #0 to #3. According to this, data “3”, 12”, 1” read from memory elements #0 to #3 u Q 11
is output to the data node DA as transmission data as it is without being rotated by the raw data nod that is valid at the time of reading. Next, when the lower two bits of the address become Al=O and AO=1 (FIG. 5(b)), the address conversion circuit 40 gives the address of address 1 to all memory elements #0 to #3. According to this, data read from memory elements #0 to #3 "6","
5", "4°°, 7" is DO → D due to raw data 30
The bits are rotated by one pit in the direction of 1→D2→D3→DO, and the bits "7" and 1 are sent to the data bus DA in order from the lower bit.
6″, “5″.

Similarly, when the lower two bits of the address bus become AI=1 and AO=0, it is output as "4'."
(Fig. 5(C)), the data stored in the area specified by the 2nd address of memory elements #0 to #3 is the raw data I.
Only the pits were rotated.

It is output to data bus DA. Also, the lower two bits are A
When l=l and AO=1 (FIG. 5(d)), the data stored in the area specified by address 3 of memory elements #0 to #3 is loaded by 3 bits by adding the raw data, It is output to data bus DA.

Next, the operation during execution of the second access method will be explained. The write operation at this time is the same as the operation shown in FIG. 4, so the explanation here will be omitted.

On the other hand, the read operation at this time is performed as shown in FIG. When executing this second access method, a conversion specification is given to the address conversion circuit 40.1 First, when the lower two bits of the address bus AD are A1=0 and AO=O (FIG. 6(a)), the address conversion is performed. The circuit 40 includes memory elements #O, #1 . #:2. For #3, as shown in Table 1, address 3 (Al=1, AO=1) and address 2 (A1
=L, AO=O), address 1 (A1=O, AO=1),
Give address 0 (AI=0, AO=O). Therefore,
Data "12", '8", 04", and 40" are read from memory elements #O, #:l, #2, and #3, respectively.

Raw data is also supplied. These data are not rotated by the raw data I and are sent onto the Demebus DA as transmission data.

Next, the lower two bits of address bus AD are A1=0, A
When O=1 (FIG. 6(b)), the address conversion circuit 4
0 indicates memory elements #O, #l, #2 . Address 2 (Al=L, AO=O) and address 1 (A1=0) for #3, respectively.
, AO=1), address 0 (A I =O.

AO=0), address 3 (AL=L, AO=1)e is given. Therefore, memory element -AO, #t, +2, #-3
From there are data ``tgu'', ``u5i'', and ``11'', respectively.

“13” is read out. These data are DO-)D 1-aD 2-+D 3-+D by the raw data 30
Rotated by 1 bit in the direction of O, starting from the lowest focus, "13", "9", "5", "1'"
It is output to data bus DA as. Similarly, the lower 2 bits of the address are Al=l and AO=OC1.
When memory elements #0, #1. #2. #-3 to Day 7 ``6'', ``2'', ``14'', ``10''
” is read, the raw data 30 is rotated by 2 bits, and “14” and “10” are read from the lower bit.
,"5".

“2” is output to data bus DA. Also, address Al=1. When AO=1, memory element #o + #i
, #-2, :+3 to data "13 +i, L"
1511゜“11” and “7” are read out, 3 bits are rotated from the raw data 3o, and “15”, “11”, “7”, and “3” are output to the data bus DA in order from the lower focus. be done.

As mentioned above, in the first access method, a group of 4 pintos that a processor etc. access simultaneously is (0, 1,
2, 3), (4, 5, 6, 7).

(8,9,10,11), (12,13,14,15
), and in the second access method (0, 4, 8, 12), (
1゜5.9.13), (2,6,10,14), (3,
7°11.15) in total, and in all cases, the four focal points are always stored in separate memory elements. Therefore, by controlling memory access as described above, the first access method and the second access method can be performed simultaneously in a 4-bit width.

Next, the influence of this embodiment on memory access speed will be described. First, the address conversion circuit 4°, for example, R
OM″f: bf′L can be easily realized.

If dynamic RAMs are used as memory elements #0 to #3 and the lower address to be converted is supplied as a column address, the delay in access speed due to address conversion will not be a problem. Furthermore, if an Am25S10 (manufactured by AMD) with a raw data rate of 213.30 mm is used, data can be retrieved with a maximum delay of 12 nsec.

However, the present invention is not limited to the above embodiment, and n=8°16
, 32, . . . , the memo IJ' can be configured to allow the two access methods described above.

(Effects of the Invention) As explained above, according to the present invention, there is one pair of bit positions stored in the memory at the focus position of the entire logical memory space.
The memory can be accessed from multiple directions by arranging it in a predetermined position corresponding to the memory, converting all the lower addresses given to this memory as necessary, and rotating the data to the memory. . Therefore, data is written in memory as two-dimensional data.

Furthermore, the read operation can be made faster.

The present invention is suitable as a control system for a memory that records character patterns and images.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram for explaining the concept of two access methods performed by the present invention, and FIG. 3 is a diagram showing the memory and logical structure used in this embodiment. Figure 4 is a diagram for explaining the entire correspondence with memory space. Figure 4 is a diagram for explaining the operation when writing data to the memory in this embodiment. Figure 5 is a diagram for explaining the operation when lower address is not converted in this embodiment. FIG. 6 is a diagram for explaining the entire memory read operation during lower address conversion in this embodiment, and FIG. 7 is a diagram for explaining the entire conventional method. be. 10... memory, loa... memory input/output data line, group... raw data, 30... raw data, 4
0...address conversion circuit, AD...address bus,
DA...Data bus 0 1t312! 11 Yu O low day, L 2 pins, Drawtate book 1 is shown as an example with ICR'fT rotary memory storage λ,
Saizu A (Actually νIIT, Rodanshi Bisen no Meshichiri Nat Miroshi □ In the picture, Hochozu Figure 6 Traditional reading of the character Kuri 〇-Ibigomeaki ↑ Roshakume Diagram No. Figure 7

Claims (1)

[Claims] Having n A×1 bit configuration (A is address capacity),
Input a memory element with a predetermined bit array and one of the address lines of the memory element (however, 2^l=n), and perform address conversion according to the address conversion/no conversion specification. an address conversion circuit provided between a data line and the memory element, the bit position of input data being moved in a predetermined direction by a predetermined amount determined according to an address of one of the address lines of the memory element; and a rotation circuit that rotates and outputs data to the memory element, and when writing data to the memory element, specifies no address conversion to the address conversion circuit, and when reading data from the memory element, the address conversion circuit A memory control method characterized by specifying no conversion or conversion of an address.