JP3213200B2 - Decoding device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding / decoding apparatus for performing data compression using predictive encoding / decoding.

[0002]

2. Description of the Related Art An arithmetic encoder suitable for predictive coding has been known as an encoder mainly used for compressing image data. In particular, for images having hierarchies, JBIG (Joint), an organization of ISO / CCITT,
Bi-level Image experts Group), and a configuration for encoding an image having this layer at high speed has been proposed by the present applicant (for example, Japanese Patent Application No. 313700 in 1994).

[0003] Arithmetic encoders and decoders perform encoding and decoding according to the probability of occurrence of each pixel. The estimation of the appearance probability of each pixel is realized by a learning function that is appropriately updated according to the appearance probability of each pixel.

FIG. 6 is a diagram showing a phase according to a pixel arrangement. In the figure, reference numeral 306 denotes a pixel of interest (X) to be coded and decoded, and 300 to 305, 307 to 310
Is a reference pixel group used when predicting the pixel 306
(Template).

In hierarchical encoding and decoding, the relative positional relationship between a high-resolution pixel group and a low-resolution pixel group is determined by
As shown in FIGS. 6A to 6D, different phases have different templates.

FIG. 7 is a block diagram showing a configuration of a conventional encoding device.

The template forms the addresses of the predicted state storage devices 100 to 103 in FIG.
For example, if the template has a configuration as shown in FIG.
For each phase, a state of 10 bits (1024 kinds) can be predicted.

This phase is determined by the relative positional relationship between the high resolution and low resolution pixel groups.
When the occurrence probability and the symbol of the pixel 306 are predicted, encoded, and decoded, the next pixel is encoded and decoded using the one predicted by the phase 1 template. For example, assuming that the pixel 306 at phase 0 is the current pixel to be encoded and decoded, in the next process, the pixel 306 forms a template as the position of the pixel 311 (h33) at phase 1.

Therefore, when a certain line is being encoded and decoded, such prediction states are sequentially used, such as phase 0, phase 1, phase 0, phase 1, phase 0, and so on. become.

An encoding apparatus shown in FIG. 7 shows a configuration capable of performing high-speed encoding using this characteristic. In the figure, reference numeral 100 denotes a storage device for storing a predicted state of phase 0, and reference numeral 200 denotes an address of the storage device 100 configured by a template of phase 0. Similarly, the storage devices 101 to 103 and the addresses 201 to 203 correspond to the phases 1 to 3, respectively.

The operation of the apparatus shown in FIG. 7 will be described below with reference to the timing chart shown in FIG.

At the beginning of period 1 in FIG. 8, an address 200 is determined by a template of phase 0.
The value is set to PH0_a1. Based on the address 200, the output 210 is read from the storage device 100, and its value is set to PH0_o1.

Reference numeral 204 denotes a selection signal determined by the phase state when processing each pixel. PH0 above
_O1 is output from the selector 104 as outputs 205 and 214 by the selection signal 204 in the period 2.

The predicted state read as output 205 is then converted by decoder 105 into an estimated probability (LSZ01) of output 206. The arithmetic encoder 10
6 performs encoding based on the outputs 206 and 214 and the pixel input 230, and outputs the code 207 as appropriate.

At the time of decoding, outputs 206 and 21 are output.
4, decoding based on the code 207, and
Outputs 1.

When it is necessary to update the predicted state value in the course of the above processing, the arithmetic encoder 106 outputs an UPDATE 208 as an update request signal, and the above-mentioned outputs 205 and 214 generate update data. Thus, update data and a control output 209 are output together with a control signal for rewriting the storage device 100. This rewriting is performed in period 2 and is written to address PH0_a1.

The encoding (decoding) of the next pixel is performed using the state predicted by the phase 1 template (decoding).
Perform At the beginning of period 2, the address 201
1_a1 is input to the storage device 101, and PH1_o1 is read as the output 211. The output 211 is selected by the selection signal 204 in the period 3, and the outputs 205 and 2 are output.
It is output as 14.

These outputs are converted by the decoder 105 into LSZ11. And outputs 206 and 214
, The encoding in the period 3 is performed. When the update process is necessary, the update process is performed in the same manner as described above, and the update data is written to the storage device 101. Hereinafter, encoding is performed in the same manner. The same applies to the decoding process.

[0019]

However, in the above conventional example, at the time of decoding, a template for determining a predicted state value necessary for decoding of the next pixel is obtained until decoding of the previous pixel is completed. However, there is a problem that the decoding processing speed is lower than that at the time of encoding. Specifically, at the beginning of period 1 shown in FIG. 8, the address 200 is input to the storage device 100 and the decoded pixel is output at least at the output 206, and the decoding process ends. Since it is later, it is the latter half of period 2.

Therefore, at the beginning of the period 2, the address 20
Since 1 cannot be determined, if a value different from the predicted pixel value is decoded, the predicted value must be read again at the beginning of period 3.

With such a configuration, the processing speed is reduced as compared with the encoding (since the values of all pixels are known at the time of encoding, so that the above-mentioned problem does not occur), and the hardware of the apparatus is reduced. Not suitable.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an encoding / decoding device which does not lower the decoding processing speed as compared with the time of encoding.

[0023]

The object of the present invention is to provide a generating means for generating addresses corresponding to a plurality of target pixels to be decoded by referring to a plurality of pixels around the target pixel to be decoded in a template. The template is used such that a first template and a second template different from the first template are alternated with respect to successive pixels of interest, and the first and second templates are: A generation unit indicating the positions of a plurality of pixels excluding the pixel before the pixel of interest to be decoded, and an appearance probability of the pixel of interest whose previous pixel is a predetermined value is stored; A first storage unit that outputs an appearance probability based on an address generated by referring to a pixel of interest, and stores an appearance probability of a pixel of interest in which a previous pixel is not a predetermined value. A second storage unit that outputs an appearance probability based on an address generated by referring to a plurality of pixels in the first template, and an appearance probability of a pixel of interest in which a previous pixel has a predetermined value, A third storage unit that outputs an appearance probability based on an address generated by referring to a plurality of pixels in the second template, and stores an appearance probability of a pixel of interest in which a previous pixel is not a predetermined value, A fourth storage unit that outputs an occurrence probability based on an address generated by referring to a plurality of pixels in the template, and whether the generation unit refers to a plurality of pixels in the first or second template,
And selecting means for selecting one of the first, second, third and fourth storage means based on whether or not the previous pixel has a predetermined value; and This is achieved by the decoding device of the present invention, comprising: decoding means for decoding a pixel of interest based on the appearance probability output from one of the first, second, third, and fourth storage means.

In the above configuration, the function is such that the decoding process is performed easily and at high speed.

[0025]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Here, in order to simplify the description, a case where there are two phases will be described. In each phase, a reference pixel (template) is generated as follows. That is, the phase 0 in FIG. 6, the pixel of interest 306 is a target pixel for encoding and decoding, and a prediction value is determined by a pixel group composed of pixels excluding the pixel of interest 306, and the code And decryption are performed.

When the above encoding and decoding are completed, the encoding and decoding of the next pixel are performed, but the pixel 311 (h33), which is a pixel necessary to generate the phase 1 template, is obtained.
Is the pixel 3 that was the target pixel for encoding and decoding at phase 0
06.

As described above, templates are continuously generated, and encoding and decoding are performed. [First Embodiment] FIG. 1 is a block diagram showing a configuration of an encoding / decoding device according to a first embodiment of the present invention. In FIG. 1, reference numerals 1 and 2 denote template generation units that generate reference pixels (templates) of phase 0 and phase 1, respectively. 20 and 21 are the coding of the previous pixel, or
A pixel group excluding a pixel group including a pixel to be decoded.
Reference numerals 2 and 23 denote the removed pixel groups.

For example, if the pixel group to be excluded is limited to only the pixel to be coded and decoded for the previous pixel, at phase 0, 22 is the pixel 305 in FIG. 6, and 20 is the remaining pixel group. is there. In the phase 1, the excluded pixel is the pixel 311 in FIG. 6. If the phase 0 => the phase 1 is processed, the pixel 306 in the phase 0 is the same as the pixel 311 in the phase 1. Pixel.

The decoding operation of the apparatus according to the present embodiment will be described below with reference to the timing chart shown in FIG.

The storage devices 3 and 5 shown in FIG. 1 store the predicted state values of the phase 0, and the storage device 100 shown in FIG. In the case of the template as shown in FIG. 6, each storage device can store 512 prediction states.

Similarly, the storage devices 4 and 6 correspond to the storage device 101 in FIG.

Here, at the beginning of period 2 in the timing chart shown in FIG. 2, reading of the storage devices 4 and 6 of phase 1 is performed. The addresses of these storage devices 4 and 6 are constituted by a group of pixels excluding the pixel 311 and the value is set to PH1_a1. By this address input, outputs 25 and 27 are output from the storage devices 4 and 6, respectively.
Note that these values are referred to as PH1_o1_L and PH1, respectively.
1_o1_H (see FIG. 2).

The phase signal 43 input to the update data generation and control unit 12 is a signal indicating at which phase the current pixel to be processed is processed. Since the processing of the phase 0 is completed in the period 2 described above, the decoded pixel 51 is output in the period 2 from the arithmetic code / decoder 11 at the time of decoding.

The phase signal 43 and the decoded pixel 51
The selection signal 42 is further determined, and one of the outputs 24 to 27 from the storage devices 3 to 6 is selected by the selector 7 and output as the output 32 and the output 34.

During period 2, pixel 51, which is a pixel decoded in the previous phase, is determined, and assuming that the value is H, output 32 from selector 7 is PH0_o1
_H. This output 32 is then input to the decoder 8, where it is converted to an estimated probability (LSZ) 36.

In the period 3, the arithmetic coder / decoder 11
Performs decoding based on the estimated probability 36 and the output 34,
The pixel output 51 is output. This output 51 is output during period 3.
PH0_o2_L, PH0_o2 already read
_H, and the process is repeated in the same manner.

When the arithmetic code / decoder 11 outputs a signal 41 indicating a request for updating the predicted state value,
The update data generation and control unit 12 generates and controls the update data together with the outputs 32 and 34 and the phase signal 43 from the selector 7.

The updating of the storage devices 3 to 6 is appropriately performed by the update data generation and the outputs 28 to 31 from the control unit 12.

As described above, according to this embodiment,
A template is formed by excluding the immediately preceding decoded pixel, the prediction state for each phase is divided into two, and the output of the template is input to the divided storage devices in common and read out independently. With this output, a mechanism for independently determining the estimated probability, the predicted symbol, etc. from each prediction state is provided, and the decoding of the pixel currently being decoded is performed using the value of the decoded previous pixel. The arithmetic encoder and decoder can be used to select the estimated probability, estimated symbol, etc., and to enable rewriting to the storage device. It can be operated at high speed without depending on the update processing of.

Furthermore, not only can encoding and decoding be performed in real time, but also the speed adjustment memory, peripheral devices, control circuits, and the like, which have been conventionally required, can be greatly reduced. Second Embodiment Hereinafter, a second embodiment according to the present invention will be described.

FIG. 3 is a block diagram showing the configuration of the encoding / decoding device according to the second embodiment. In the figure, the same components as those of the device according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Therefore, the operation at the time of decoding in this embodiment will be described with reference to the timing chart shown in FIG.

At the beginning of period 2 in FIG. 4, reading from the storage devices 4 and 6 of phase 1 is performed as in the first embodiment. The addresses of these storage devices 4 and 6 correspond to the pixels 3 shown in FIG.
It is composed of a group of pixels other than 11 and its value is set to PH1_a1 here. Then, according to the address input, outputs 25 and 27 are output from the storage devices 4 and 6. The values are PH1_o1_L and PH1_o1_H, respectively.

The phase signal 43 indicates that the current pixel to be processed is
This signal indicates which phase is processed. here,
Since the processing of the phase 0 ends in the period 2, the decoded pixel 51 is output from the arithmetic code / decoder 11 in the period 2 during decoding.

Then, the selection signal 1 is
(42) is determined, and the selector 7 selects the storage device 3
Out of the outputs 24 to 27 of the first to third outputs 32, 27,
33 and 34 and 35 are output. These phase outputs 32, 33 are then converted by the decoders 8, 9 to an estimated probability of 3
8 and 39, respectively.

During period 2, a pixel output 51 which is a pixel decoded in the previous phase is determined, and when the value is H, the output (LSZ) 38 from the selector 10 is changed to LSZH by the selection signal 2 (44). , And output (MPS)
39 becomes MPSH.

In the period 3, the arithmetic code / decoder 11
Performs decoding based on the outputs 38 and 39, and outputs a pixel output 51. The output 51 output here is:
During period 3, LSZ11_L, L that has already been read
SZ11_H is used for selection, and thereafter, the processing is repeated in the same manner as described above.

When the arithmetic code / decoder 11 outputs the output 41 which is a request for updating the predicted state value, the output 32, 33, 34, 35 from the selector 7 and the phase signal 43
At the same time, the update data generation and control unit 12 generates and controls the update data. The update of the storage devices 3 to 6 is performed by generating the update data and outputting 28 from the control unit 12.
This is appropriately performed according to. <Modification> FIG. 5 shows an encoding / modification according to a modification of the above embodiment.
It is a block diagram which shows the structure of a decoding device. even here,
The same components as those in the apparatus according to the above embodiment shown in FIGS. 1 and 3 are denoted by the same reference numerals.

In this modification, prior to encoding and decoding,
To reset the storage devices 3 to 6 corresponding to each phase,
A reset means 90 is provided, and the storage devices 3 to 6 are simultaneously reset by an output 91 from the reset means 90.

Thus, the storage device can be reset in a shorter time.

In the above description, detailed timings and the like are omitted for simplification of the description. However, as described above, the feature of the present invention is that at certain times, pixels whose values are not known are excluded. A template is formed, a plurality of predicted state value candidates are read in advance, and the predicted state value is determined when the pixel value becomes known.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0053]

As described above, according to the present invention,
By performing encoding / decoding without depending on the update processing of the storage device that stores the predicted value, real-time encoding / decoding can be easily realized.

According to another aspect of the present invention, a plurality of storage devices are divided into a plurality of storage devices so that they can be reset at the same time, whereby the storage devices can be reset in a shorter time.

[0055]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encoding / decoding device according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the device according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of an encoding / decoding device according to a second embodiment.

FIG. 4 is an operation timing chart of the device according to the second embodiment.

FIG. 5 is a block diagram illustrating a configuration of an encoding / decoding device according to a modification.

FIG. 6 is a diagram illustrating a phase according to a pixel arrangement.

FIG. 7 is a block diagram illustrating a configuration of a conventional encoding / decoding device.

FIG. 8 is an operation timing chart of a conventional encoding / decoding device. .

[Explanation of symbols]

 1, 2 Template generating unit 3-4, 100-103 Storage device 7, 10, 104 Selector 8, 9, 105 Decoder 11, 106 Arithmetic code / decoder 12, 107 Update data generation and control unit 300-305 High resolution side Pixel 306 Encoding / decoding target pixel 307-310 Low resolution side pixel

Claims (10)

(57) [Claims] 1. A generating means for generating an address corresponding to each of a plurality of pixels of interest to be decoded by referring to a plurality of pixels around the pixel of interest to be decoded in a template, wherein the template comprises a first And a second template different from the first template are used alternately with respect to successive pixels of interest, wherein the first and second templates are pixels before the pixel of interest to be decoded. Generating means representing the positions of a plurality of pixels except for the first pixel, storing an appearance probability of a pixel of interest whose previous pixel is a predetermined value, and generating an address generated by referring to the plurality of pixels in the first template. A first storage unit that outputs an appearance probability based on the first pixel, and stores an appearance probability of a pixel of interest in which the previous pixel is not a predetermined value, and stores the probability in the first template. A second storage unit that outputs an appearance probability based on an address generated by referring to a plurality of pixels, and stores an appearance probability of a pixel of interest in which a previous pixel has a predetermined value, and A third storage unit that outputs an appearance probability based on an address generated by referring to a plurality of pixels, and stores an appearance probability of a pixel of interest in which a previous pixel is not a predetermined value; A fourth storage unit that outputs an appearance probability based on an address generated by referring to the pixel, and a generation unit that has referred to a plurality of pixels of the first or second template, Selecting means for selecting one of the first, second, third and fourth storage means based on whether or not the value is a predetermined value; and the first and second storage means selected by the selecting means , 3
And decoding means for decoding the pixel of interest based on the appearance probability output from one of the fourth storage means. 2. The decoding apparatus according to claim 1, further comprising an updating unit that updates an appearance probability stored in one of the first, second, third, and fourth storage units. . 3. The method according to claim 2, wherein said decoding means is configured to output said first, second, and third signals.
And the decoding means updates the appearance probability stored in one of the other storage means while decoding is performed based on the appearance probability output from one of the fourth storage means. The decoding device according to claim 2. 4. The decoding device according to claim 1, wherein the generation unit refers to a low-resolution pixel in addition to a plurality of pixels around the pixel of interest. 5. The decoding apparatus according to claim 1, wherein said decoding means decodes the pixel of interest using arithmetic coding. 6. A generating step of generating an address corresponding to each of a plurality of target pixels to be decoded by referring to a plurality of pixels around a target pixel to be decoded in a template, wherein the template includes a first template. And a second template different from the first template are used alternately with respect to successive pixels of interest, wherein the first and second templates are pixels before the pixel of interest to be decoded. From the first storage device that stores the occurrence probabilities of the pixel of interest in which the previous pixel is a predetermined value. A first output step of outputting an appearance probability of a target pixel based on an address generated by reference; and storing an appearance probability of a target pixel whose previous pixel is not a predetermined value. A second output step of outputting an appearance probability of a pixel of interest based on an address generated by referring to a plurality of pixels in the first template from the second storage device, wherein the previous pixel has a predetermined value. A third output step of, from a third storage device storing the appearance probability of a certain pixel of interest, outputting the appearance probability of the pixel of interest based on an address generated by referring to a plurality of pixels in the second template; A fourth storage device that stores an appearance probability of a target pixel whose previous pixel is not a predetermined value outputs an appearance probability of the target pixel based on an address generated by referring to a plurality of pixels in the second template. A fourth output step, based on which of the plurality of pixels of the first or second template was referred to in the generation step, and whether or not the previous pixel has a predetermined value. There are, first, second, and selection means for selecting one of the third and fourth storage devices, has been the first selected by the selection means, the second, third
And a decoding step of decoding the pixel of interest based on the appearance probability output from one of the fourth storage devices. 7. The decoding method according to claim 6, further comprising an updating step of updating an appearance probability stored in one of the first, second, third, and fourth storage devices. . 8. The method according to claim 1, wherein the first, second, and third steps are performed in the decoding step.
And decoding the pixel of interest based on the appearance probability output from one of the fourth storage devices, and updating the appearance probability stored in one of the other storage devices. The decoding method according to claim 7, characterized in that: 9. The decoding method according to claim 6, wherein in the generation step, a low-resolution pixel is referred to in addition to a plurality of pixels around the pixel of interest. 10. The decoding method according to claim 6, wherein, in said decoding step, the pixel of interest is decoded using arithmetic coding.