JP3871995B2 - Encoding device and decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image data encoding apparatus using a predictive encoding method and a decoding apparatus for the encoded data.
[0002]
[Prior art]
As one of binary image encoding techniques, there is a predictive encoding method that predicts the state of a target pixel from surrounding pixels and encodes the predicted result. In predictive coding, surrounding pixels that are considered to have a correlation with the target pixel are used for prediction as Markov information sources.
[0003]
As a prediction method, a method for directly determining a prediction value and a method for indirectly determining a prediction value are known. As a method for directly determining a prediction value, for example, as disclosed in Japanese Patent Laid-Open No. 5-316370, a predictor with a high hit ratio is adaptively switched among a plurality of predictors, and finally one prediction is performed. There is a method of selecting a container and using it for prediction of an original image. In addition, as a method for indirectly determining a prediction value, for example, there is a method in which information such as a prediction value is stored in a memory, and information in the memory is read from surrounding pixel values and used for prediction.
[0004]
The prediction method disclosed in Japanese Examined Patent Publication No. 6-95645 is a prediction method that indirectly determines a prediction value using the latter memory, and uses a table lookup method with the values of peripheral pixels as addresses. Prediction error data is generated using the output predicted value. However, the position of the predicted pixels is not fixed, but the position of only one pixel is made variable, and the predicted position is changed by the predictive middle rate. ITU-T TT. 82, the prediction method used in JBIG (Joint Bi-level Image coding expert Group) defined in T-85 is the prediction method shown in the above-mentioned Japanese Patent Publication No. 6-95645, and depends on the encoding state. A learning type method of updating information in the prediction table is adopted. For the encoding, prediction error data which is a result of predicting the target pixel by the above-described prediction method is used.
[0005]
In JBIG, arithmetic coding is adopted as a coding unit that codes prediction error data. In arithmetic coding, for example, as shown in Japanese Patent Publication No. 1-17295, a region on a number line is divided according to the occurrence probability of 1 and 0 of an input symbol, and the region is determined by the value of the input symbol. Select. At this time, a symbol (predominant symbol) that matches the prediction is referred to as MPS (More Probable Symbol), and a symbol that does not match (inferior symbol) is referred to as LPS (Less Probable Symbol). The MPS and LPS occurrence probability estimates are changed according to the predictive predictive value. In JBIG, a symbol appearance probability estimation unit has a probability value (= region width LSZ) at the time of occurrence of LPS, and has a learning function for updating the probability estimation value according to a symbol appearance process. The learning function for probability estimation works in conjunction with the learning function for the predicted value. This division selection processing is performed for the output series of the information source, and the output series is represented by a binary decimal display of one point in the area obtained by the final division.
[0006]
FIG. 10 is a conceptual diagram of arithmetic coding. The areas indicated by diagonal lines are the effective areas after the end of the symbol encoding. In the initial state, the effective area is the [0, 1) section, and the area width LSZ (0) when LPS occurs is set. 1-LSZ (0) is the area width when MPS occurs. Here, when the symbol is “0”, it is MPS, and when it is “1”, it is LPS. In FIG. 10, the probability value is indicated by a binary number.
[0007]
In FIG. 10, since the first input symbol is “0”, the effective area becomes the hatched area in FIG. 10A due to the occurrence of MPS. Then, a new area width LSZ (1) is set to divide the effective area into areas when LPS occurs and when MPS occurs. When the next symbol is “1”, the hatched area in FIG. 10B becomes the effective area due to the occurrence of LPS. Similarly, when the third symbol is “0”, the hatched area in FIG. 10C becomes an effective area, and when the fourth symbol is “1”, hatching in FIG. 10D. The area subjected to is an effective area.
[0008]
The output code is represented by C. The code for the input symbol string “0101” may be one point in the effective area in FIG. Here, the base of the effective area, that is, the smallest value C (3) of the effective area is expressed as a code and output.
[0009]
In arithmetic coding, since one point in the effective area is used as a code in the encoding process, if the area is increased, the effective digits are reduced and the code amount is reduced. That is, by reducing the value of LSZ as much as possible when MPS occurs and increasing the value of LSZ as much as possible when LPS occurs, a large effective area can be secured and the amount of codes can be reduced.
[0010]
FIG. 11 is a schematic diagram of a predictive coding method employed in JBIG. In the figure, 1 is image data, 2 is a context generation unit, 3 is context, 4 is a prediction unit, 5 is a state, 6 is a probability estimation table, 7 is LSZ and SW, 8 is a predicted value, and 9 is an arithmetic coding unit. 10 is code data, 11 is rewrite data, and 12 is a rewrite signal.
[0011]
The image data 1 is input to the arithmetic encoding unit 9 for encoding and also input to the context generation unit 2. In the context generation unit 2, in order to perform prediction of the target pixel, a prediction model template is created using surrounding pixels. FIG. 12 is an explanatory diagram of an example of a template used in JBIG. If P is a target pixel, the reference pixel X shown in FIG. ₉ ~ X ₀ A template that uses is generated. This reference pixel X ₉ ~ X ₀ Value of 2 ^Ten It becomes a 10-fold Markov information source of the state (context), and is directly input to the prediction unit 4 as context 3 and used for prediction.
[0012]
The prediction unit 4 includes a reference pixel X ₉ ~ X ₀ A prediction table in which a prediction value 8 corresponding to each value and a state 5 for referring to the probability estimation table 6 is paired is stored. Reference pixel X ₉ ~ X ₀ Context 3 that is the value of is input as it is to the prediction table as an address, and one of the 1024 entries of the prediction table is selected. The prediction value 8 and the state 5 are extracted from the prediction table entry selected by the context 3, the prediction value 8 is input to the arithmetic coding unit 9, and the state 5 is input to the probability estimation table 6. FIG. 13 is an explanatory diagram of an example of a prediction table stored in the prediction unit 4. The prediction table shown in FIG. 13 stores prediction values and states in pairs corresponding to addresses. The address is shown in binary, but this is the reference pixel X input as the context 3 ₉ ~ X ₀ Correspond to the respective pixel values. For example, reference pixel X ₀ If only the value of “1” is “1” and the other reference pixels are “0”, the address “0000000001” is referred to, and the predicted value “1” and the state “2” are obtained.
[0013]
The probability estimation table 6 corresponds to the state 5, the area width LSZ when the LPS occurs, the NLPS that is the next state value when the LPS occurs, the NMPS that is the next state value when the MPS occurs, and the normalization occurrence In some cases, SW that is a flag indicating whether or not to rewrite the predicted value is stored. LSZ and SW7 corresponding to the inputted state 5 are output to the arithmetic coding unit 9 and NMPS and NLPS are sent to the prediction unit 4 as a part of the rewrite data 11. FIG. 14 is an explanatory diagram of an example of the probability estimation table 6. In FIG. 14, LSZ, NMPS, NLPS, and SW are stored as a pair corresponding to the state 5 number. For example, when the state is “2”, “0x1114” as LSZ, “16” as NLPS, “3” as NMPS, and “0” as SW are obtained. Here, the numerical value starting with “0x” is a hexadecimal number.
[0014]
The arithmetic coding unit 9 compares the prediction value 8 input from the prediction unit 4 with the image data 1, and if they match, it is assumed that the symbol to be encoded is “0”, that is, MPS has occurred, and there is a mismatch. If so, it is assumed that the symbol to be encoded is “1”, that is, LPS has occurred. Then, using the LSZ input from the probability estimation table 6, arithmetic coding is performed as outlined in FIG. 10 to output code data 10. When an LPS occurs, the new predicted value is rewritten only when the predicted value is rewritten by the SW input from the probability estimation table 6 (for example, when SW is “1”). A rewrite signal 12 is sent to the prediction unit 4 as part of the data 11, and the prediction value of the prediction table stored in the prediction unit 4 is rewritten.
[0015]
In JBIG, the arithmetic encoding unit 9 is adjusted so that the effective area is always 0.5 or more and less than 1 so as not to increase the effective digits of the effective area. This process is called normalization. The probability estimation table is configured so that the value of LSZ is always less than 0.5. As a result, when LPS occurs, the effective area becomes less than 0.5, and normalization always occurs. Further, even when MPS occurs, the new effective area may be less than 0.5 because it is obtained by subtracting LSZ from the current effective area, and normalization may occur. When this normalization occurs, a rewrite signal 12 is sent to the prediction unit 4. The prediction unit 4 writes the NMPS given from the probability estimation table 6 to the prediction table as the state of the context 3 given from the context generation unit 2 when MPS occurs. When LPS occurs, the NLPS given from the probability estimation table 6 is written in the prediction table as the state of the context 3. After the prediction table is updated in this way, processing for the next image data 1 is started.
[0016]
A learning-type prediction / probability estimation method in which the above-described prediction unit 4 and probability estimation table 6 are sequentially rewritten will be further described using a specific example. FIG. 15 is an explanatory diagram of a specific example of input image data. FIG. 15 shows only the image data 1 of the template portion shown in FIG. As shown in FIG. ₉ ~ X ₀ Let us consider a case where the pixel of interest P is 1 when is “0000000011”. It is assumed that the contents shown in FIGS. 13 and 14 are set in the prediction table and the probability estimation table 6 of the prediction unit 4, respectively.
[0017]
First, the context “0000000011” is input to the prediction unit 4 as the context 3. At this time, the prediction value “0” and the state value “80” are stored in the address “0000000011” of the prediction table 4 of the prediction unit 4 as shown in FIG. The state value “80” read from the prediction table is input to the probability estimation table 6. Next, the state number “80” in the probability estimation table 6 is referred to. Since the contents shown in FIG. 14 are set in the probability estimation table 6, the LSZ value “0x5832” corresponding to the state number “80” is read and output to the arithmetic coding unit 9.
[0018]
At this time, the value of the pixel of interest P is “1”, but the predicted value read from the prediction table of the prediction unit 4 is “0”, which means that LPS has occurred. When LPS occurs, the area corresponding to the LSZ value read from the probability estimation table 6 is basically the next effective area. Since the LSZ is less than 0.5, normalization is performed so that the LSZ is 0.5 or more and less than 1, and the NLPS value “80” of the state number “80” is the address “0000000011” of the prediction unit 4. "Is overwritten as the state value. In addition, since the SW of the state number “80” in the probability estimation table 6 is “1”, the prediction value is inverted to “1” and is overwritten as the prediction value of the address “0000000011” of the prediction table of the prediction unit 4. The FIG. 16 is an explanatory diagram of a specific example of the prediction unit table after rewriting. In this way, as shown in FIG. 16, the prediction value and state value of the address “0000000011” of the prediction unit are rewritten. Prediction for the next image data 1 is performed using the rewritten prediction unit. Next, when the same context is input, the predicted value is 1.
[0019]
In this example, LPS has occurred, but when MPS has occurred, when normalization is performed, the state value of the prediction table of the prediction unit 4 is rewritten to NMPS “81”. When the same context 3 is input next after rewriting, the state value is “81”, and the LSZ at this time is “0x4d1c” from FIG. This value is smaller than LSZ “0x5832” when the state value is “80”, that is, the probability of occurrence of LPS is small. This is because the prediction at the same time of the previous context was hit, so when the same context is input next time, the area width when MPS occurs is widened, and when the prediction hits again, the effective area can be widened Thus, the final effective area can be increased and the code amount can be decreased.
[0020]
As described above, the prediction unit is sequentially rewritten according to the probability estimation table, the predictive predictability is improved, the number of MPS occurrences is increased, and the area width when MPS / LPS occurs is controlled to improve the coding efficiency. I am letting.
[0021]
Also, the decoding process is performed while performing region segmentation, similar to the encoding process. The difference from the encoding is that the prediction value is compared with the target pixel at the time of encoding, and the LPS / MPS area is calculated while it is calculated. Is obtained by calculation, and then the target pixel is obtained from the surrounding decoded reference pixels while performing reverse prediction.
[0022]
FIG. 17 is a schematic diagram of a predictive decoding method adopted in JBIG. In the figure, the same parts as those in FIG. 21 is an arithmetic decoding unit, 22 is an inverse prediction unit, 23 is an inverse prediction value, and 24 is rewritten data. The context generation unit 2 and the inverse prediction unit 22 operate exactly the same as the context generation unit 2 and the prediction unit 4 at the time of encoding. The inverse prediction unit 22 is the same as the prediction unit 4 at the time of encoding. Naturally, the same probability estimation table 6 as that used for encoding must be used.
[0023]
First, as in the case of encoding, a context is generated based on the values of reference pixels around the target pixel of the decoded image data 1, and the LSZ and the inverse prediction value 23 are arithmetically calculated from the inverse prediction unit 22 and the probability estimation table 6. The data is output to the decoding unit 21.
[0024]
Next, the code data 10 is subjected to comparison of effective areas in the arithmetic decoding unit 21, and then the image data 1 is output using the inverse prediction value 23. FIG. 18 is an explanatory diagram of the basic operation of the arithmetic decoding unit. First, the LSZ width input from the probability estimation table is subtracted from the current effective area,
(Effective area-LSZ)
Get. The MPS area and the LPS area are divided on the basis of this value. Next, it is compared whether or not the input code C is larger than the previously obtained (effective region−LSZ) value. That is,
C> Effective area-LSZ
Judgment is made. Since this comparison determination can determine whether the pixel of interest is LPS or MPS, the level of the pixel of interest is obtained from the input reverse prediction value. That is, in the case of MPS, the value of the target pixel is a reverse prediction value, and in the case of LPS, the reverse prediction value may be inverted to be the value of the target pixel. With the above processing, the target pixel can be basically decoded.
[0025]
However, in order to decode the next pixel, further processing such as determination of a new effective area and subtraction of a code-effective area is necessary. For example, in the example shown in FIG. 18, since the code data C exists in the LPS area, the LPS area is set as a new effective area, a new LSZ is set, and the above-described processing is repeated. Similarly to the encoding, the prediction value and state value of the prediction table stored in the prediction unit 4 are also rewritten.
[0026]
As described above, JBIG uses a learning-type prediction method that is updated using a rewritable memory as a probability estimation table, and uses an arithmetic coding method for the entropy coding unit, so that High-efficiency encoding of binary images and decoding of code data are achieved compared to length encoding and the like.
[0027]
However, in the JBIG system, high-efficiency encoding is achieved, but there is a problem that processing is slow. The learning-type prediction method using the prediction table adopted by JBIG has the advantage of improving the predictive predictive value because it rewrites the predicted value and state to bring it closer to the optimal state, but it takes time to access the memory. In addition, when the rewriting of the prediction table occurs, the predicted value cannot be read out until after the rewriting is completed, and it is difficult to increase the speed.
[0028]
In Japanese Patent Application Nos. 8-301889 and 8-2888731, a plurality of data are read in advance from a prediction table or an inverse prediction table at the time of encoding or decoding, and the encoding result or decoding of the current image is read out. A method has been proposed in which data is selected and speeded up according to the result. In addition, as disclosed in, for example, Japanese Patent Laid-Open No. 8-1554059, a method for speeding up arithmetic coding itself has been proposed. However, in any case, since there is a possibility that the prediction table is rewritten for each pixel, it is not possible to take measures for speeding up such as processing a plurality of adjacent pixels simultaneously.
[0029]
In order to speed up the encoding process, a method of processing in parallel using a plurality of encoders is generally considered. That is, the input image is divided into a plurality of regions and encoded by encoders corresponding to the respective regions. However, this method cannot cope with a case where an input image is transferred pixel by pixel from the top of the page from a scanner or the like. For example, when an input image is divided into two and encoded by two encoders, pixels in one region are transferred continuously, and only the encoder corresponding to one region operates during that time, and then the other encoder operates. The encoder corresponding to the other region cannot operate until the transfer of the pixels in the region is started. For this reason, although a plurality of encoders are provided, they cannot be processed in parallel. In order to perform parallel processing, it is conceivable to transfer an image after it is temporarily stored in a memory, but there is a problem that the amount of memory increases. Also, when outputting in real time to an output device or the like at the time of decompression, it is necessary to temporarily store it in the memory.
[0030]
As another method, as described in, for example, US Pat. No. 4,982,292, a method of encoding an input image every other pixel has been proposed. However, this method has a problem that JBIG generates a context that realizes high-efficiency encoding every other pixel, resulting in a decrease in prediction efficiency, which affects the encoding efficiency.
[0031]
Further, in any of the above-described methods for speeding up, since codes processed in parallel are output separately, there is a problem that memory management for storing codes becomes complicated.
[0032]
As a method of combining the separately generated code data into one, there is a method of inserting an identification code at the head of each code data as described in, for example, JP-A-6-38048. According to this method, one code is used, but if each code data length is increased, an extra memory is required, and if the switching is made finer, the identification code amount increases. there were.
[0033]
[Problems to be solved by the invention]
The present invention has been made in view of the above-described circumstances, and can perform high-efficiency encoding or decoding at high speed and generate code data that can be managed as one code data while suppressing the amount of code data. It is an object of the present invention to provide an encoding device that performs the decoding and a decoding device that decodes the encoded data.
[0034]
[Means for Solving the Problems]
In order to solve the above-described problem, the encoding device according to the first aspect of the present invention (invention 1), when combining the code data encoded by the plurality of encoding means by the combining means, The output code data is output in order for each unit code data. When the code data is not output from the encoding means, the code data cannot be output sequentially. Only in that case, the identification data is attached and the code data is output from the other encoding means. Accordingly, since the identification code is not output to the synthesized code data output from the synthesizing unit in a normal state, only the identification code is output only in a special case where the encoded data is not output from the encoding unit. Therefore, it is possible to reduce the data amount of the entire synthesized code data.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block configuration diagram showing an embodiment of an encoding apparatus of the present invention. In the figure, the same parts as those in FIG. Reference numeral 31 denotes an encoding unit, 32 denotes a FIFO memory, 33 denotes a memory status signal, 34 denotes a read signal, 35 denotes unit code data, 36 denotes a synthesis unit, and 37 denotes synthesis code data. FIG. 1 shows an example in which two blocks of the encoding unit 31 are provided. One is an A block, the other is a B block, and A or B is written after “-” in a configuration related to each block. Distinguish.
[0037]
Each of the encoding units 31-A and B includes a prediction unit 4, a probability estimation table 6, and an arithmetic encoding unit 9, and the context generation unit 2 has a configuration common to the encoding units 31-A and B. Provided. The image data 1 is input to the context generation unit 2 provided in common and also input to the arithmetic encoding unit 9 of each of the encoding units 31-A and B. The contexts 3-A and B generated by the context generation unit 2 are input to the prediction units 4 of the respective encoding units 31-A and B.
[0038]
Corresponding to the respective encoding units 31-A, B, FIFO memories 32-A, B for temporarily storing the code data 10-A, B output from the respective encoding units 31-A, B are provided. Provided. The FIFO memories 32-A and B basically read out in advance from the previously stored code data in units of a predetermined data amount in accordance with the read signals 34-A and B from the synthesizer 36, and unit code data 35- A and B are transferred to the synthesis unit 36. The FIFO memories 32-A and B can each store a plurality of units of code data, and output memory status signals 33-A and B indicating whether the data is empty or full.
[0039]
Based on the memory status signals 33-A and B from the FIFO memories 32-A and B, the synthesizer 36 basically reads the read signal 34- alternately with respect to the FIFO memory 32-A and the FIFO memory 32-B. A or a read signal 34 -B is sent to read out the code data, unit code data 35 -A or unit code data 35 -B is obtained and output as synthesized code data 37. When one of the FIFO memory 32-A and the FIFO memory 32-B is empty and the other is full, the identification code of the full side is inserted and the FIFO memory 32-A continues from the full FIFO memory. Then, the unit code data is read out and output as composite code data 37. At the end of the code data, the code data remaining in the FIFO memory 32-A or the FIFO memory 32-B is read and output.
[0040]
Next, an example of the operation in the embodiment of the encoding apparatus of the present invention will be described. FIG. 2 is an explanatory diagram of an example of image data. FIG. 2A shows an original image composed of (n + 1) × (n + 1) pixels, in which data of each pixel from the left end of each line to the right end in order from the top to the bottom in the figure is input. And That is, P ₀₀ , P ₀₁ , ..., P _0n , P _Ten , P ₁₁ , ..., P _1n , P ₂₀ , ..., P _mn In this order, the image data 1 of each pixel is input. In the configuration shown in FIG. 1, two blocks are provided in the encoding unit, but each encoding unit 31-A, B encodes input image data 1 alternately. That is, the encoding unit 31-A performs P as shown in FIG. ₀₀ , P ₀₂ , ..., P _Ten , P ₁₂ ,... (The second subscript is an even pixel) is encoded. In addition, the encoding unit 31-B, as shown in FIG. ₀₁ , P ₀₃ , ..., P ₁₁ , P ₁₃ ,... (The second subscript is an odd number pixel) is controlled to be encoded.
[0041]
The context generation unit 2 generates the context 3 from the input image data 1 according to a template as shown in FIG. 12, for example. For example P _{twenty two} When image data 1 is input, P shown in FIG. _{twenty two} A context is generated by 10 pixels excluding. Next P _{twenty three} When image data 1 is input, P shown in FIG. _{twenty three} A context is generated by 10 pixels excluding. These contexts are generated uniformly regardless of which encoding unit is used. Thus, by generating the context 3 regardless of the encoding unit, the prediction accuracy is improved and the encoding can be performed efficiently.
[0042]
The encoding unit 31-A takes in the context 3-A and the image data 1-A output from the context generation unit 2 when a pixel with an even second subscript is input. For example, P _{twenty two} When image data is input, it is captured as image data 1-A and P _{twenty two} Context 3-A generated by the template shown in FIG. Similarly, the encoding unit 31-B captures the context 3-B and the image data 1-B output from the context generation unit 2 when a pixel with an odd second subscript is input. For example, P _{twenty three} Image data is input as image data 1-B, and P _{twenty three} Context 3-B generated by the template shown in FIG.
[0043]
In each of the encoding units 31-A and B, the image data 1-A and B are adaptively predictively encoded according to the contexts 3-A and B by the same operation as in FIG. Is output.
[0044]
FIG. 3 is a timing chart showing an example of image input and operation of each encoding unit in the embodiment of the encoding apparatus of the present invention. Image data 1 for one pixel is input together with the input image clock. The encoding unit 31-A and the encoding unit 31-B are input with clocks having different phases, respectively, obtained by dividing the input image clock by two. Since the encoding units 31-A and B latch the image data 1 at the rising edge of each clock, as a result, the latched image data A and B are input to the respective encoding units every other pixel. become. In the example of FIG. ₂₀ Is input, the clock of the encoding unit 31-A rises and P ₂₀ Is taken into the encoding unit 31-A and encoded. Next, pixel P _{twenty one} Is input, the clock of the encoding unit 31-B rises and P _{twenty one} Is taken into the encoding unit 31-B and encoded. P _{twenty one} Since the clock of the encoding unit 31-A does not rise while is input, P _{twenty one} Is not captured by the encoding unit 31-A. In this way, the image data 1 is alternately taken into the encoding unit 31-A and the encoding unit 31-B and encoded.
[0045]
As shown in FIG. 3, the encoding units 31-A and 31B can perform encoding processing for only two cycles of the input image clock. On the contrary, since the encoding units 31-A and B operate in parallel, the image data 1 can be input and encoded at a speed twice the processing speed, and the overall encoding speed is determined by the encoding unit. Doubled compared to a single case. At this time, since the context generator 2 is shared, the encoding unit 31-A and the encoding unit 31-B perform encoding processing independently, but the prediction with a high hit rate is performed. And the compression efficiency is improved.
[0046]
Code data 10-A and B encoded and output by the encoding units 31-A and B are stored in the FIFO memories 32-A and B, respectively. At this time, the FIFO memories 32-A and B store a plurality of units of code data in units of a predetermined data amount. Here, as an example, code data is stored in units of words.
[0047]
FIG. 4 is a flowchart showing an example of the operation of the synthesis unit in the embodiment of the encoding apparatus of the present invention. In this flowchart, the FIFO memory 32-A is indicated as 'A', and the FIFO memory 32-B is indicated as 'B'. The synthesizer 36 basically repeats the operations of S71 to S74. That is, referring to the memory status signal 33-A in S71, it is determined whether or not the FIFO memory 32-A is empty. If not, the code data (unit code data) for one word is read from the FIFO memory 32-A in S72. 35-A) is read out and output as composite code data 37. Next, in S73, the memory status signal 33-B is referenced to determine whether or not the FIFO memory 32-B is empty. If it is not empty, code data (unit code data) for one word is read from the FIFO memory 32-B in S74. 35-B) is read out and output as composite code data 37. By repeating this, the code data encoded by the encoding unit 31-A and the encoding unit 31-B are alternately output for each word, and generated by the encoding units 31-A and B. The code data is synthesized. By performing such synthesis, the code data generated by the encoding units 31-A and 31B can be managed as one code data without being managed separately. Also, identification codes for identifying the respective code data can be eliminated as much as possible, and an increase in the amount of data during synthesis is suppressed.
[0048]
In the arithmetic coding system, one code is not always output for input of one image data. For example, when encoding can be performed very efficiently, a code is not output unless a large number of image data is input. Also, as described with reference to FIG. 10, since the decimal part of the base of the effective area is used as a code, a carry may occur depending on the change of the effective area. For example, when the base of the effective area is 0.0111 in binary, it may be changed to 0.10001, for example, by dividing the effective area. In such a case, the code cannot be output in consideration of the possibility of this carry.
[0049]
There is a case where the state where the code data is not output occurs in one encoding unit, and the output of the code data from the other encoding unit is accumulated in the FIFO memory. For example, in a case where the code data is not output from the encoding unit 31-A and the code data from the encoding unit 31-B is accumulated in the FIFO memory 32-B, is the encoding completed in S75? After determining whether or not, in S76, it is determined whether or not the FIFO memory 32-B is full. If it is not full, the process directly returns to S71. This is to avoid losing the format for outputting the code data alternately for each word as much as possible. When the code data is output from the encoding unit 31-A, the process of alternately reading and outputting the words one by one again is performed. Start.
[0050]
Further, if code data is not output from the encoding unit 31-A and the FIFO memory 32-B is full, the encoding unit 31-B cannot output the code data, and thus must stop the encoding process. In order to avoid such a situation, when the memory status signal 33-A indicates empty and the memory status signal 33-B indicates full, in S77, the code data from the same block as the code data output immediately before is output. An identification code indicating that the code data is to be output continuously is output, and all words are read from the FIFO memory 32-B and output. Then, the process returns to S71 and again waits for the code data to be stored in the FIFO memory 32-A.
[0051]
The same applies to the case where the code data is not output from the encoding unit 31-B and the code data from the encoding unit 31-A is stored in the FIFO memory 32-A. After reading and outputting the unit code data 35-A for one word from the FIFO memory 32-A in S72, it is determined in S73 that the FIFO memory 32-B is empty. After determining whether or not the encoding process is completed in S78, it is determined whether or not the FIFO memory 32-A is full in S79. If the FIFO memory 32-A is not full, the process returns to S73 and waits for the code data to be stored in the FIFO memory 32-B. When the FIFO memory 32-A is full while the FIFO memory 32-B is empty, in S80, an identification code is output, and all words are read out from the FIFO memory 32-A and output. Then, the process returns to S73 and again waits for the code data to be stored in the FIFO memory 32-B.
[0052]
As described above, when the FIFO memory is full, the code data is output together with the identification code, so that the data amount of the composite code data is slightly increased. However, high-speed encoding processing can be performed without stopping the encoding unit. Can be done.
[0053]
Even when the input of the image data 1 to be encoded is lost and the encoding process is completed, the code data is stored in one of the FIFO memories, and the code data is stored in another FIFO memory and waits. become. In order to avoid this, the end of the encoding process is determined in S75 and S78. If it is determined in S75 that the encoding process has been completed, since it is determined in S71 that the FIFO memory 32-A is empty, data remains in the FIFO memory 32-B. In S81, after outputting the identification code, all the code data in the FIFO memory 32-B is read and output. If the end of the encoding process is determined in S78, it is determined in S73 that the FIFO memory 32-B is empty. Therefore, after the identification code is output in S82, the code in the FIFO memory 32-A is output. Read and output all data. In this way, all code data can be output.
[0054]
FIG. 5 is an explanatory diagram of an example of the composite code data. An example of the combined code data 37 output from the combining unit 36 as described above is shown in FIG. Here, 'A' is unit code data 35-A read from the FIFO memory 32-A, and 'B' is unit code data 35-B read from the FIFO memory 32-B. Basically, the unit code data 35-A and B are alternately read and output one word at a time from the FIFO memory 32-A and the FIFO memory 32-B, so that the unit code data 35-A read from the FIFO memory 32-A The unit code data 35-B read from the FIFO memory 32-B are alternately arranged one by one. That is, the unit code data 35-A read from the FIFO memory 32-A is sequentially converted to A. ₀ , A ₁ ,..., And the unit code data 35-B read from the FIFO memory 32-B are sequentially B ₀ , B ₁ If so, first of all, A ₀ , B ₀ , A ₀ , B ₁ .. And the code of each block are output alternately.
[0055]
A _n Is output, the code data 10-A is not output from the encoding unit 31-A, and the code data 10-B is output from the encoding unit 31-B during that period. B _n Is output, the code data is not read out until the FIFO memory 32-B is full, and is simply stored in the FIFO memory 32-B as it is. When this state further continues and the FIFO memory 32-B becomes full, an identification code is output, and all the code data in the FIFO memory 32-B is read and output. Here, the capacity of the FIFO memory 32 is 16 words. As shown in FIG. _{n + 1} To B _{n + 16} Is output.
[0056]
In this example, thereafter, there is an output of code data from the encoding unit 31-A, and A _{n + 1} , B _{n + 17} ,... Are alternately read and output alternately. Of course, if no code data is output from the encoding unit 31-A and the FIFO memory 32-B becomes full again, all the code data in the FIFO memory 32-B is output together with the identification code. The same applies to the case where code data is not output from the encoding unit 31-B and code data is accumulated in the FIFO memory 32-A. In this way, the code data separately encoded by the encoding unit 31-A and the encoding unit 31-B can be combined into one, and the combined code data 37 in which the increase in the data amount is suppressed is output. be able to.
[0057]
The above identification code may be anything as long as it is different from a normal code. For example, a comment marker such as FF04 (hexadecimal) defined by the JBIG standard may be used.
[0058]
FIG. 6 is a block configuration diagram showing an embodiment of the decoding apparatus of the present invention. In the figure, parts similar to those in FIG. Reference numeral 41 denotes a decoding unit, 42 denotes a FIFO memory, 43 denotes a memory status signal, 44 denotes a write signal, 45 denotes unit code data, 46 denotes a division unit, and 47 denotes composite code data. FIG. 6 shows an example in which two blocks of the decoding unit 41 are provided. One is an A block, the other is a B block, and A or B is written after “-” in a configuration related to each block. Distinguish.
[0059]
The dividing unit 46 divides the combined code data 47 into unit code data 45-A and B, and controls the FIFO memories 42-A and B while referring to the memory status signals 43-A and B, The unit code data 45-A and B are written into the FIFO memories 42-A and B, respectively. The dividing unit 46 performs the completely opposite operation to the combining unit 36 in the above-described encoding device. That is, basically, the composite code data 47 is divided into predetermined data amounts and written alternately into the FIFO memory 42-A or the FIFO memory 42-B. When the identification code is detected, unit code data having a predetermined data amount is continuously written in one FIFO memory.
[0060]
The FIFO memories 42-A, B are provided in the preceding stage corresponding to the decoding units 41-A, B, respectively, and unit code data 45-A, a predetermined amount of data according to the write signals 44-A, B, Store B. The decoding units 41-A and B read the code data 10-A and B from the corresponding FIFO memories 42-A and B and decode them.
[0061]
The decoding units 41-A and B include the arithmetic decoding unit 21, the probability estimation table 6, and the inverse prediction unit 22 excluding the context generation unit 2 in the configuration illustrated in FIG. The context generation unit 2 is provided in common to the two decoding units 41-A and B. Image data 1 is alternately output from the decoding units 41-A and B. The output image data 1 is input to the context generation unit 2, and a context 3 is generated according to a template as shown in FIG. 12, for example. The context 3 generated by the context generation unit 2 is alternately input to the decoding unit 41-A or the decoding unit 41-B.
[0062]
Next, an example of the operation in the embodiment of the decoding device of the present invention will be described. For example, composite code data 47 as shown in FIG. The dividing unit 46 basically divides the synthesized code data 47 into units of a predetermined data amount, for example, one word unit, and divides the divided unit code data 45-A and B together with the write signals 44-A and B into a FIFO memory. 42-A and B are written alternately. The writing is performed by referring to the memory status signals 43-A and 43B and confirming that the FIFO memory on the writing side is not full.
[0063]
For example, in the composite code data 47 shown in FIG. 5, the unit code data A of the first one word ₀ Is written into the FIFO memory 42-A, and the unit code data B of the next one word is written. ₀ Is written into the FIFO memory 42-B. Similarly A ₁ , ..., A _n To the FIFO memory 42-A, B ₁ , ..., B _n Are sequentially written in the FIFO memory 42-B. With reference to the memory status signals 43-A and B, if any of the FIFO memories 42-A and B is full, the writing is temporarily stopped at that time.
[0064]
When the identification code is detected, a predetermined number of unit code data subsequent thereto is written in one of the FIFO memories. In the case of the composite code data 47 shown in FIG. 5, since writing is performed in the FIFO memory 42-B before the identification code, unit code data of 16 words following the identification code is sequentially written in the FIFO memory 42-B. Go out. In this case as well, the memory status signal 43-B is referred to, and when the FIFO memory 42-B is full, the writing is temporarily stopped.
[0065]
The operations in the decoding units 41-A and B are the same as those in FIG. 17 described above, and the codes read from the FIFO memories 42-A and B using the contexts 3-A and B generated by the context generation unit 2 Data 10-A and B are decoded and output as image data 1-A and B. At this time, the decoding units 41-A and B alternately capture and decode the context output from the context generation unit 2 according to the pixel position to be decoded. For example, when the image shown in FIG. 2A is restored, the decoding unit 41-A that decodes the code data obtained by encoding the pixel shown in FIG. 2B is an image of a pixel whose second subscript is an even number. Context 3-A for decrypting data is captured. Similarly, the decoding unit 41-B that decodes the code data obtained by encoding the pixel illustrated in FIG. 2C performs the context 3-B when decoding the image data of the pixel whose second subscript is an odd number. take in.
[0066]
FIG. 7 is a timing chart showing an example of the relationship between the operation of the decoding unit and the output of image data in the embodiment of the decoding device of the present invention. The decoding units 41-A and 41B are given clocks having different phases, and decoding is performed according to these clocks. By decoding processing, image data that is a decoding result is determined at a certain point in time. At this time, each of the decoding unit 41-A and the decoding unit 41-B performs decoding processing independently, and can perform decoding at a speed twice that of the case of one decoding unit.
[0067]
Since the decoding unit 41-A and the decoding unit 41-B operate according to clocks having different phases, timings at which decoding results are determined are different as shown in FIG. This is alternately output by the output image clock having a cycle of 1/2 of the clock given to the decoding units 41-A and B. Thereby, the decoding result of the decoding unit 41-A that has decoded the pixel shown in FIG. 2B and the decoding result of the decoding unit 41-B that has decoded the pixel shown in FIG. The image data shown in FIG. 2A is sequentially output.
[0068]
Further, the image data obtained by alternately selecting the decoding results of the decoding units 41-A and B in this way is also input to the context generation unit 2. As a result, the context generator 2 can generate a context referring to continuous pixels as shown in FIGS. 2D and 2E as in the case of encoding.
[0069]
However, since the context generation unit 2 cannot generate the context of the current pixel unless decoding of the previous pixel is completed, there is a problem that the current pixel cannot be decoded. That is, if the decoding process is delayed in one decoding unit, the other decoding process cannot be started, and the processing speed decreases. In order to avoid this, for example, as disclosed in the above-mentioned Japanese Patent Application No. 8-288873, reverse prediction is performed according to all values that can be taken by the previous pixel during decoding, and a plurality of reverse prediction data is generated. Then, a method has been proposed in which one of the inverse prediction data is selected at the time when the value of the previous pixel is determined, and the decoding process is accelerated, and this technique can also be used in the present invention.
[0070]
In the decoding apparatus of the present invention shown in FIG. 6, the decoding is performed every other pixel in each decoding unit 41-A, B. Therefore, for example, when the decoding unit 41-A decodes the current pixel, the decoding unit 41-A immediately performs the decoding process, that is, the pixel two pixels before the original image and the other decoding unit 41. The pixel being decoded in -B, that is, the previous pixel on the original image is used for the context. Although the values of the pixels decoded immediately before by the decoding unit 41-A are fixed, if the inverse prediction table in the inverse prediction unit 22 is rewritten, the inverse prediction cannot be performed until the rewriting is completed. Further, since the pixels decoded by the decoding unit 41-B are processed in parallel, the values may not be fixed. Therefore, when decoding the current pixel, a plurality of inverse prediction values corresponding to all possible combinations of values are obtained for the pixels one pixel before and two pixels before on the original image. Then, when the value of the pixel decoded immediately before by the decoding unit 41-A and the value of the pixel currently decoded by the decoding unit 41-B are determined, a plurality of inverse prediction values are obtained from the values of these pixels. Select the correct one from the list.
[0071]
A configuration for realizing such an operation is shown below. FIG. 8 is a block configuration diagram showing another example of the decoding unit in the embodiment of the decoding apparatus of the present invention. In the figure, 51 to 54 are inverse prediction tables, 55 is a write control unit, 56 is a write signal, 57 is a write address, 58 is a selection unit, 59 is image data from another decoding unit, and 60 is previous image data. . Here, only the configuration of one decoding unit is shown. The configuration shown in FIG. 8 is applied to the decoding units 41-A and B in FIG.
[0072]
In this configuration, for example, the template X shown in FIG. ₁ , X ₀ X excluding ₉ ~ X ₂ A context consisting of eight image data is used. Each of the inverse prediction tables 51 to 54 is a table configured as shown in FIG. 13, for example, and is stored in a storage device such as a RAM. Unlike those shown in FIG. 13, the addresses of the reverse prediction tables 51 to 54 are composed of 8 bits. The reverse prediction table 51 is X ₁ , X ₀ The inverse prediction value and the state when the pixels are assumed to be 0, 0 are stored. Similarly, the inverse prediction tables 52 to 54 are represented by X ₁ , X ₀ Are stored as inverse prediction values and states when the pixels are assumed to be 0, 1, 1, 0 and 1, 1, respectively. Inverse prediction values and states are read from the four inverse prediction tables 51 to 54 according to an 8-bit context, and are input to the selection unit 58.
[0073]
The selection unit 58 captures the image data 1 output from the arithmetic decoding unit 21 as the previous image data 60 and also captures the image data 59 from the other decoding units, and based on these, from the inverse prediction tables 51 to 54. One of the output reverse prediction value and state is selected, and the state is output to the probability estimation table 6 and the reverse prediction value 23 is output to the arithmetic decoding unit 21. For example, when the previous image data 60 is 0 and the image data 59 from the other decoding unit is 0, the output of the reverse prediction table 51 is selected. Similarly, when the previous image data 60 and the image data 59 from the other decoding unit are 0 and 1, the output of the reverse prediction table 52 is selected, and when the image data 59 is 1, 0, the output of the reverse prediction table 53 is selected. In the case of 1, 1, the output of the reverse prediction table 54 is selected.
[0074]
The write control unit 55 uses the context X used in the inverse prediction tables 51 to 54. ₉ ~ X ₂ As a write address to the inverse prediction tables 51 to 54, and in response to a rewrite instruction of the rewrite signal 12, the image data 1 output from the arithmetic decoding unit 21 and the image data 59 from the other decoding unit One of the reverse prediction tables 51 to 54 to be written is selected from the values, and a write signal 56 is sent to the selected reverse prediction table. In each of the inverse prediction tables 51 to 54, the NMPS or NLPS output from the probability estimation table 6 and the new inverse prediction value output from the arithmetic decoding unit 21 are given as the rewrite data 24. Therefore, the write control unit 55 In the reverse prediction table to which the write signal 56 is sent, the rewrite data 24 is written to the write address sent from the write control unit 55.
[0075]
FIG. 9 is a timing chart for explaining an example of the operation of another example of the decoding unit in the embodiment of the decoding apparatus of the present invention. In FIG. 9, P in FIG. _{twenty four} The example which performs decoding of the pixel of the position by the decoding part 41-A is shown. In the decoding unit 41-A, P _{twenty four} Immediately before decoding the pixel at position P _{twenty two} The pixel at the position is decoded. The write control unit 55 _{twenty two} Context X ′ with the pixel at the position of interest as the pixel of interest ₉ ~ X ' ₂ Holding.
[0076]
P _{twenty two} While decoding the pixel at position P _{twenty four} Context X with the pixel at the position of the target pixel ₉ ~ X ₂ Is input to the reverse prediction tables 51 to 54 as an address. From the inverse prediction tables 51 to 54, X ₁ , X ₀ Four types of reverse predicted values and states in the case of “00”, “01”, “10”, and “11” are read out and input to the selection unit 58.
[0077]
On the other hand, in the decoding unit 41-B, P _{twenty three} Is decoded by the decoding unit 41-A. _{twenty two} This is started with a half cycle delay in decoding of the pixel at the position. Eventually P in the decoding unit 41-A _{twenty two} The pixel at the position is decoded to output image data, which is input to the selection unit 58 as previous image data 60. Thereafter, P in the decoding unit 41-B _{twenty three} Is decoded to output image data, which is input to the selection unit 58 as image data 59 from another decoding unit. X at this point ₁ , X ₀ Therefore, the selection unit 58 selects any output (reverse prediction value, state) of the reverse prediction tables 51 to 54, and P is determined. _{twenty four} Is passed to the arithmetic decoding unit 21 and the probability estimation table 6 as an inverse prediction value and a state for decoding the pixel at the position. As a result, P in the next cycle _{twenty four} The decoding of the pixel at the position can be started.
[0078]
P _{twenty two} When the reverse prediction table is rewritten by decoding, the write control unit 55 holds the stored P _{twenty two} Context X ′ with the pixel at the position of interest as the pixel of interest ₉ ~ X ' ₂ Is output to the prediction tables 51 to 54 as the write address 57. Further, P output from the arithmetic decoding unit 21 _{twenty two} Image data 1 at the position of P and P output from the decoding unit 41-B _{twenty three} The reverse prediction table to be rewritten is specified from the image data 59 from the other decoding unit, which is the image data at the position, and a write signal 56 is sent to the reverse prediction table. In the inverse prediction tables 51 to 54, the probability estimation table 6 and the arithmetic decoding unit 21 receive P _{twenty two} Since the rewrite data 24 relating to the image data at the position is input, the reverse prediction table to which the write signal 56 is given from the write control unit 55 rewrites the data at the write address 57 to the rewrite data 24. Next P ₂₆ In the decoding of the pixel at the position, four types of reverse prediction values and states are output using the rewritten reverse prediction table.
[0079]
Of course, P output from the decoding unit 41-A _{twenty two} , P _{twenty four} The image data 1 at the position is sent to the decoding unit 41-B and used as the image data 59 from the other decoding unit, and decoding is performed by the same processing.
[0080]
In this way, since the reverse prediction table can be read even before the reverse prediction table is rewritten, the arithmetic decoding unit 21 and the reverse prediction tables 51 to 54 can be read in parallel. Processing can be speeded up.
[0081]
The inverse prediction tables 51 to 54 are configured as two inverse prediction tables based only on the value of one pixel before the image data 59 from the other decoding unit, and after the image data 1 is output from the arithmetic decoding unit 21. Context X ₉ ~ X ₁ May be used. Alternatively, a three-port memory may be used to form two or one memory.
[0082]
Here, an example is shown in which the decoding apparatus performs pre-reading of the reverse prediction table as shown in FIG. 8 to increase the speed, but for example, as described in the above-mentioned Japanese Patent Application No. 8-301890, If the prediction table is prefetched, the encoding apparatus can perform the encoding process without causing a delay due to the writing of the prediction table, and the encoding can be performed at high speed.
[0083]
As described above, an example of the encoding device and the decoding device that perform parallel processing by arranging a plurality of encoding units or decoding units according to the present invention has been shown. The present invention is not limited to these examples. For example, the encoding unit and the decoding unit can be further parallelized with a larger number of configurations instead of two blocks. In addition, the unit of the code data amount when combining in the combining unit 36 may be other than one word, and can be combined sequentially with an arbitrary data amount as a unit. In addition, the number of units of code data from a specific encoding unit continued after the identification code can be arbitrarily set. These may be set with the decoding apparatus, and the dividing unit 46 may divide the combined code data according to the same rules as those used for encoding.
[0084]
Further, the capacities of the FIFO memory 32 and the FIFO memory 42 are not limited to 16 words, and may be arbitrary capacities. Of course, the capacities of the FIFO memory 32 and the FIFO memory 42 may be different, and the combining unit 36 and the dividing unit 46 may control the FIFO memory 32 and the FIFO memory 42 in accordance with the format of the combined code data.
[0085]
Furthermore, the present invention is not limited to the one that synthesizes the code data of the predictive coding method into the synthesized code data, and can be configured to synthesize the code data of different coding methods.
[0086]
As described above, according to the present invention, it is possible to increase the speed even in an encoding method such as JBIG, which is difficult to increase in speed. Therefore, even in a system such as a printer or a copier that requires high-speed real-time processing, Data can be compressed by applying an efficient encoding method.
[0087]
【The invention's effect】
As is apparent from the above description, according to the encoding device of the first aspect of the invention, the code data that has been processed in parallel can be efficiently combined into one code, so that the data amount of the combined code data is increased. And the management of the code data can be simplified.
[0088]
Further, according to the decoding device of the second invention, the efficiently synthesized code data is distributed as input to the plurality of decoding means by the dividing means, and the decoding that can be processed in parallel by the plurality of decoding means There is an effect that an apparatus can be obtained.
[0089]
In addition, since predictive encoding can be performed in parallel by a plurality of encoding means, encoding can be performed at high speed. At this time, a large image memory is not required in the previous stage, and since the context can be generated in the same manner as when a single encoding unit is used, encoding can be performed without impairing encoding efficiency. Similarly to this encoding apparatus, a large image memory is not required in the previous stage, and decoding processing can be performed in parallel by a plurality of decoding means, so that decoding can be performed in real time at high speed.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram showing an embodiment of an encoding apparatus of the present invention.
FIG. 2 is an explanatory diagram of an example of image data.
FIG. 3 is a timing chart showing an example of image input and operation of each encoding unit in the embodiment of the encoding apparatus of the present invention.
FIG. 4 is a flowchart showing an example of the operation of the synthesis unit in the embodiment of the encoding apparatus of the present invention.
FIG. 5 is an explanatory diagram of an example of composite code data;
FIG. 6 is a block configuration diagram showing an embodiment of a decoding device of the present invention.
FIG. 7 is a timing chart showing an example of the relationship between the operation of the decoding unit and the output of image data in the embodiment of the decoding device of the present invention.
FIG. 8 is a block configuration diagram showing another example of a decoding unit in an embodiment of the decoding apparatus of the present invention.
FIG. 9 is a timing chart for explaining an example of operation of another example of the decoding unit in the embodiment of the decoding apparatus of the present invention;
FIG. 10 is a conceptual diagram of arithmetic coding.
FIG. 11 is a schematic diagram of a predictive coding method employed in JBIG.
FIG. 12 is an explanatory diagram of an example of a template used in JBIG.
13 is an explanatory diagram of an example of a prediction table stored in a prediction unit 4. FIG.
FIG. 14 is an explanatory diagram of an example of a probability estimation table 6;
FIG. 15 is an explanatory diagram of a specific example of input image data.
FIG. 16 is an explanatory diagram of a specific example of a prediction unit table after rewriting.
FIG. 17 is a schematic diagram of a predictive decoding method employed in JBIG.
FIG. 18 is an explanatory diagram of a basic operation of an arithmetic decoding unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Image data, 2 ... Context generation part, 3 ... Context, 4 ... Prediction part, 5 ... State, 6 ... Probability estimation table, 7 ... LSZ and SW, 8 ... Predicted value, 9 ... Arithmetic coding part, 10 ... Code data, 11 ... rewrite data, 12 ... rewrite signal, 21 ... arithmetic decoding unit, 22 ... inverse prediction unit, 23 ... reverse prediction value, 24 ... rewrite data, 31 ... encoding unit, 32 ... FIFO memory, 33 ... Memory state signal 34 ... Read signal 35 ... Unit code data 36 ... Synthesis unit 37 ... Synthesis code data 41 ... Decoding unit 42 ... FIFO memory 43 ... Memory status signal 44 ... Write signal 45 ... Unit code data, 46... Dividing unit, 47... Synthetic code data, 51 to 54 .. Inverse prediction table, 55... Write control unit, 56 ... Write signal, 57 ... Write address, 58. , 59 ... image data, 60 ... front image data from the other decoder.

Claims (1)

A plurality of encoding means for encoding data input after being sequentially assigned to each pixel; a plurality of memories each storing code data generated by the plurality of encoding means; and the code from the plurality of memories Combining means for reading out data and combining it into one combined code data in a predetermined order for each unit code data, the combining means is configured such that the memory for storing code data to be output by a certain encoding means is empty. When the memory corresponding to the other encoding means is full, the code data output from the other encoding means together with the identifier is read out from the memory corresponding to the other encoding means and output. An encoding apparatus characterized by that.

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