KR960011111B1 - Variable length decoder of digital image signal - Google Patents

Abstract

the first latch (22) for latching a variable length coded data from a FIFO(First-In First-Out) buffer (10); a barrel shifter (24) for outputting the variable length data shifted based on the shift value from the second latch (28) using the latched variable length coded data as the upper bits to a decoding table (30); an adder (26) for outputting a carrier signal to a read signal generator (12); and the second latch (28).

Description

Variable Length Decoder in Decoding Device of Digital Video Signal

1 is a block diagram of a variable length decoder in an apparatus for decoding a digital video signal according to the present invention.

2 and 3 are flow charts and timing diagrams of a berel shifter employed in a variable length decoder in the apparatus for decoding a digital video signal of the present invention shown in FIG.

4 and 5 are flowcharts and timing diagrams of an adder used in a variable length decoder in the apparatus for decoding a digital video signal of the present invention shown in FIG.

6 is a block diagram of a conventional variable length code decoding apparatus.

7 shows a memory structure of a code length table in a decoding table.

(a) is a memory structure diagram of a code length table according to the present invention;

(b) is a memory structure diagram of a code length table according to a conventional apparatus.

* Explanation of symbols for main parts of the drawings

10: first-in first-out buffer (FIFO) 12: read signal generator / AND gate

20: signal processing means 22: first latch

24: berel shifter part 26: adder part

28: second latch 30: decoding table

32: codeword table 34: code length table

36: decryptor table

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to variable length decoding in an apparatus for decoding a digital video signal. In particular, the present invention relates to a digital video signal decoding apparatus capable of improving processing speed and simplifying configuration according to decoding. It relates to a variable length decoder.

In general, when a video signal is to be transmitted as a digital signal, such as an HDTV or a video telephone, the transmitting side uses a compression encoding method to reduce a large amount of data due to such a transmission.

Accordingly, the video signal decoding apparatus performs variable length decoding on the transmission side to perform variable length decoding on the original signal to restore the variable length coded image data.

In the case of such a transmission, a first-in first-out buffer is provided at the output end of the receiving side and the input end of the transmitting side for smooth transmission of data, and the first-in first-out buffer processes the input variable length coded data.

The present invention relates to variable length decoding in a video signal decoding apparatus which is substantially a receiving side apparatus in such a system.

FIG. 6 illustrates a conventional variable length code decoding apparatus for receiving variable length coded image data through a first-in, first-out buffer through a conventional video signal encoding apparatus.

As shown in the figure, the conventional variable length decoding apparatus decodes the signal appropriately for processing the variable length code data output from the first-in, first-out buffer 40 based on the read signal from the AND gate 42. It consists of 60.

In addition, the signal processing means 50 for processing the variable length coded data for decoding includes four latches 52, 54, 56 and 58 and a predetermined bit length input through the two latches 52 and 54. And a berel shifter 53 and an accumulator 56 for dividing and outputting predetermined bits sequentially according to the signal.

The decoding table 60 includes a codeword table 62 made of an AND-PLANE for detecting a variable length code section from a series of variable length codes input from the berel shifter 53, and the detected variable length. It consists of a code length table 64 in an OR-PLANE for detecting the number of bits in a code section, and a decoded table 66 in an end plan for decoding the detected variable length code section.

An operation process of a conventional variable length code decoding apparatus having such a configuration will be described below. Whenever a read signal from the AND gate 42 is applied to the senior election buffer 40 while the system is operating, the senior election buffer 40 in turn stores the variable length code data, i.e., 24-bit data, which are stored in sequence. The output will be sequentially.

Accordingly, the latch 54 outputs 24-bit variable length code data when the read signal is applied from the AND gate 42 after latching the variable length code data from the first-in, first-out buffer 40 as shown in FIG. In addition, the latch 52 also outputs 24-bit variable length code data when the read signal is applied from the AND gate 42 described above after latching the output data of the latch 54.

In this way, variable-length code data of 24 bits, that is, a total of 48 bits, respectively, output from the two latches 52 and 54 is input to the next stage berel shifter 53. The Berrel shifter 53 applies 24-bit variable length code data of the first 48 bits to the decoding table 60, and the decoding table 60 has a 24-bit variable length input through the built-in codeword table 62. The variable length code data of a predetermined bit is detected from the code data, and the detected variable length code is decoded into the original data, that is, the data before the variable length code is encoded, through the decode word table 66, and then output.

At this time, the code length table 64 detects the number of bits of the variable length code detected by the codeword table 62 and inputs it to the accumulator 55 through a 24-bit line corresponding to the number of input bits.

As the above process continues, the accumulator 55 accumulates the total number of bits of the variable length code decoded in the decoding table 60.

Then, the value accumulated in the accumulator 55 is latched in the latch 56 and then synchronized with the clock signal to apply the number of bits for the variable length code to be decoded to the berel shifter 53.

In this case, when the accumulated value exceeds 24, that is, when a variable length code of 24 bits or more is decoded in the decoding table 60, the accumulator 55 generates a carry signal and applies it to the latch 58. The latch 58 then applies a carry signal that has been latched corresponding to the input of the clock signal to one terminal of the AND gate 42. As a result, the AND gate 42 outputs a read signal, that is, a high level signal, to the first-in, first-out buffer 40 described above.

Therefore, the first-in, first-out buffer 40 outputs the next 24-bit variable length code data which are sequentially stored based on the read signal as described above, and by repeating such a process continuously, the conventional apparatus has variable length encoding. Variable length decoding the received video signal.

In the above variable length decoding apparatus, the code length table in the decoding table has the same number of bits as the number of bits of the variable length code, as shown in FIG. That is, it has a 24-bit line.

Although the conventional variable length code decoding apparatus smoothly variable length decodes the variable length coded data through the above-described process, a fast operation speed is required in the decoding device for variable length decoding the variable length coded data. The recent trend of miniaturization, weight reduction and low price of point and decoding devices has not been met.

Accordingly, the present invention has been made in view of this point, and the variable length processing speed is improved by reducing the latch that causes unnecessary delay and the bit line having the same line as the number of bits of the variable length code in the code length table of the decoding table. An object of the present invention is to provide a variable length decoder in an apparatus for decoding a digital video signal, which can simplify the configuration.

According to the present invention for achieving the above object, the variable length coded data stored in the first-in, first-out buffer 10 is output in accordance with the control signal from the read signal generator for processing through a signal processing means, and then codeword table, In the variable length code decoding apparatus for variable length decoding through a decoding table consisting of a code length table and a decoded table, the signal processing means 20 is a variable outputted from the first-in, first-out buffer 10 in synchronization with a clock signal. A first latch 22 for latching the length data; From the second latch 28 connected to one side, the variable length code data output from the first-in, first-out buffer 10 is the lower bit, and the latched variable length code data from the first latch 10 is the higher bit. A berel shifter section 24 for outputting, to the decoding table 30, variable length code data shifted on the basis of a shift value of? An adder for accumulating the code length value input from the code length table 34 and the previous code length value through a plurality of bit lines, and outputting a carry signal to the read signal generator 12 when it is equal to or greater than the next variable length value ( 36) and; And a second latch 28 that outputs the code length value calculated by the adder 26 to the berel shifter 24 as a shift value in synchronization with a clock signal.

Other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. 1 is a block diagram of a variable length decoder in a digital video signal decoding apparatus according to the present invention.

Referring to FIG. 1, a variable length decoder in a digital video signal decoding apparatus according to the present invention includes a first-in first-out buffer 10, a read signal generator 12, a signal processing means 20, and a decoding table. (30).

The first-in, first-out buffer 10 receives and stores variable length coded data through a coding apparatus, not shown, and restores the stored data based on a read signal from the read signal generator 12 to be described later. It is configured to output to one latch 22 and the barrel shifter 24.

The read signal generator 12 is configured to provide a read signal multiplied by an input clock and a carry signal from the adder 26 to be described later to the first-in, first-out buffer 10. 12 consists of an AND gate. The signal processing means 20 receives the variable length coded data from the first-in, first-out buffer 10 so that the signal processing means 20 is provided to a decoding table 30 which will be described later. 20) outputs a carry signal to the read signal generator 12 when the accumulated code length value is equal to or greater than the variable length code length value, and the signal processing means 20 includes the first latch 22 and the berel shifter. (24), an adder (26) and a second latch (28).

The first latch 12 is configured to latch a variable length coded data from the first-in, first-out buffer 10 to an input clock and provide the latched data to the bevel shifter unit 24 described later.

The bevel shifter part 24 uses the variable length code data output from the first-in, first-out buffer 10 as a lower bit, and the variable length code data latched from the first latch 10 as an upper bit and is connected to one side. The variable length code data shifted on the basis of the shift value from the latch 28 is output to the decoding table 30 described later.

The adder 26 accumulates the code length value and the previous code length value inputted from the code length table 34 to be described later through a plurality of bit lines, and then outputs a signal for allocating a shift value for the variable length code. When the accumulated code length value is equal to or greater than the code length value of the variable length code, a carry signal is generated and output to the read signal generator 12.

The second latch 28 is configured to output the shift value to the berel shifter 24 and the adder 26 in association with the code length accumulated by the adder 26 and the input clock.

The decoding table 30 is configured to variable length decode and output variable length coded data from the signal processing means 20. The decoding table 30 includes a codeword table 32, a code length table 34, It consists of a decryptor table 36.

The codeword table 32 detects a variable length code section from the variable length code data from the berel shifter section 24 of the signal processing means 20, and decodes the code length table 34 and the following to describe the detected data. A table 36 is configured to be provided.

The code length table 34 is configured to detect the number of bits of the code section detected in the codeword table 32 and provide it to the adder 26 through five bit lines.

Referring to the operation of the present invention configured as described above in detail.

First, the first-in, first-out buffer 10 sequentially stores variable length code data (for example, 24 bits) that are encoded and input, and an input clock signal from the outside is connected to one side terminal of the AND gate 12 and the first latch 22. ) And second latch 28 to be synchronized.

In an initial operation, the adder 26 generates a carry signal and a code length value of 24 bits, and the carry signal is applied to the other terminal of the AND gate 12. Therefore, the AND gate 12 is logically multiplied based on the clock signal CLK inputted through the other terminal thereof and the carry signal, and the read signal generated at this time is output to the first-in, first-out buffer 10.

Accordingly, the first-in, first-out buffer 10 sequentially supplies the stored variable length code data to the first latch 22 and the berel shifter 24 based on the read signal of the AND gate 12. The variable length code data is latched by the first latch 22 and then provided to the berel shifter portion 24.

The Berrel shifter section 24 has variable length code data stored in the first-in, first-out buffer 10, that is, the lower 24 bits and the latched value of the first latch 22, that is, the 48-bit variable length code as the upper 24 bits. It is input.

Therefore, the upper 24 bits of the 48-bit variable length code data are first applied to the decoding table 30, where the flow and timing of the berel shifter section 24 are as shown in Figs. .

That is, the berel shifter 24 has a variable length code data of 48 bits (24 bits each of a and b as shown in FIG. 3) input from the first-in first-out buffer 10 and the first latch 22. The variable length code data of the upper 24 bits is shifted according to the shift value (5 bits) output from the second latch 28 and then applied to the decoding table 30.

On the other hand, the decoding table 30 detects a variable length code section with respect to 24-bit variable length coded data input through the embedded codeword table 32, and detects the variable length coded section through the decoded table 36. The coded data is decoded into original data (data before variable length coding) and output.

At this time, the code length table 34 detects the number of bits of the variable length code section detected by the codeword table 32 and transfers the number of bits to the adder 26 through five bit lines.

Herein, the code length table 34 according to the present invention has the same number of bit lines (24 bit lines) as the number of bits (24 bits) of the variable length code as shown in FIG. Unlike that in the conventional apparatus, as shown in Fig. 7 (b), the number of sign digits representing a 24-bit number is reduced to a value (that is, 5 bits).

Therefore, the adder 26 assigns a shift value for the next variable length code input according to the code length value input from the code length table 34 and the result of accumulating the previous code length value. The shift value is latched to the second latch 28 and then provided to the above-described berel shifter 24 and the adder 26 in synchronization with the clock signal CLK.

4 and 5 show a flowchart and a timing diagram of an adder employed in the variable length code decoding apparatus of the present invention. The input value to the adder 25 is 5 bits and the output value is 5 bits. Therefore, the adder 26 accumulates the code length value for the next variable length code according to the 5-bit input value as described above, and generates a carry signal when the code length value is 24 bits or more.

As described above, in the present invention, the variable length code decoding apparatus performs variable length decoding on the variable length coded data through a process similar to that of the conventional apparatus described above, but the present invention substantially differs from the first-in first-out buffer in the conventional apparatus. The number of bit lines in the code length table in the decoding table is reduced (from 24 bit lines to 5 bit lines) without using the latch used to configure the bits. The structure is simplified compared to the conventional apparatus to correspond to the reduced number of bit lines by changing the structure to obtain a shift value according to an arbitrary code length value (5 bits).

In addition, by eliminating the latch used to carry the carry signal in the conventional device in the device of the present invention, the overall device is not only simplified, but also a significant reduction in the memory portion (for example, from ²⁴ to 2 ⁵ for 24 bit). ) Can improve the processing speed of the decoding process.

Claims (2)

The variable length coded data stored in the first-in, first-out buffer 10 is output in accordance with the control signal from the read signal generator, processed by the signal processing means 20, and then composed of a codeword table, a code length table, and a decoded table. In the variable length code decoding apparatus for variable length decoding through a decoding table 30, the signal processing means 20 latches the variable length code data output from the first-in, first-out buffer 10 in synchronization with a clock signal. The first latch 22; From the second latch 28 connected to one side, the variable length code data output from the first-in, first-out buffer 10 is the lower bit, and the latched variable length code data from the first latch 10 is the higher bit. A berel shifter section 24 for outputting, to the decoding table 30, variable length code data shifted on the basis of a shift value of? The signal length value inputted from the code length table 34 and the previous code length value are accumulated through a plurality of bit lines, and a signal for allocating a shift value for the next variable length code is output. An adder 36 for outputting a carry signal to the read signal generator 12 when it is equal to or greater than a code length value of a variable length code; And a second latch 28 which outputs the code length value accumulated by the adder 26 to the berel shifter 24 as a shift value in synchronization with a clock signal. Variable-length decoder in. The variable length decoder of claim 1, wherein the plurality of bit lines are five bit lines.