KR0125125B1 - High-speed apparatus for decoding variable length code - Google Patents

Abstract

The apparatus improves operation speed by demodulating code word every half period of clock signal. It includes processors(120,140) latching bit stream of variable length code and providing variable length code data having preset number of bit according 1st and 2nd length signal out of the latched bit stream, a demodulator(200) detecting the code word and providing decoded word, latches(310,320) latching the length signal respectively with falling and rising edges, and a selector(340) providing the length signal of the latch(310) and adder(330) as 2nd length signal selectively.

Description

High speed variable length code decoding device

1 is a block diagram for schematically illustrating a fast variable length code decoding apparatus according to the present invention;

2 is a timing diagram for explaining the operation of the control unit constituting the fast variable length code decoding apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

100: interface unit 120: first processing unit

140: second processing unit 200: decoding unit

300: control unit 310: first latch

320: second latch 330: first adder

340: selection unit 350: first accumulator

360: second accumulator 370: fourth adder

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a variable length code decoding device, and more particularly, to a fast variable length code decoding device capable of high speed operation due to structural improvement.

In high definition image systems, variable length coding is used for various lossless data compression. Variable-length coding converts fixed-length data into variable-length data based on the statistics of the data.The frequency of occurrence of each code included in the information source is shorter and less frequent. This is a method of displaying a long length code. In this way, the average value of the code lengths can be reduced compared to assigning the same length to all codes. A typical variable length code is the Huffman code.

In general, the coding process may be implemented by a lookup-table that uses input data for the table address, code-word and word-word. length) is stored as table contents. However, the decoding process is very complicated. That is, due to the variable length feature, each codeword is decoded from the received bitstream of the variable length code and then decoded into an information source codeword. Therefore, the design of the variable length code decoding apparatus is generally more difficult than the design of the variable length coding apparatus.

Various methods have been proposed for such variable length code decoding. As one of the methods, a tree search algorithm is mainly used, and a decoding apparatus using the tree search algorithm includes a logic circuit corresponding to a tree and a control circuit for performing tree traversal on a code tree. do. However, this approach is considerably slower and requires a bitwise search through the code tree for each codeword. Therefore, the decoding apparatus based on the tree search requires a large number of tree searches to obtain one decoded word data, which causes a large problem of delaying the overall operation speed of the apparatus.

The most representative of the proposed methods for improving the speed of the variable length code decoding device is the variable length code decoding device of US Patent No. 5,245,338, which was granted to Ming-Ting Sun on September 14, 1993. to be.

The conventional fast variable length code decoding apparatus proposed by mingming and the like includes a barrel shifter for sequentially dividing input code data, that is, bit stream data, by predetermined bits according to a length signal. It includes a decoding table. The decoding table may include a code length table of an AND-plane for detecting a meaningful variable length code interval, that is, a code word, among a series of variable length codes applied from a beryl shifter, A code length table of an OR-Plane for detecting the number of bits of the detected variable length code interval and a decoded word table of the end plan for decoding the detected variable length code interval.

Unlike the conventional bit unit search, the conventional variable length code decoding apparatus can shift the entire detected code word at one period of the click signal by using a beryl shifter, thereby receiving the received bitstream data. Since codewords can be detected for each cycle of the clock signal, the fast encoding is possible.

By the way, the above-described fast variable length code decoding apparatus has a certain speed improvement compared to the conventional decoding and decoding apparatus based on the tree search. However, in the high quality video system which needs to process a large amount of data in a short time, Increasing the data processing speed of the variable length code decoding apparatus has been increasingly demanded in recent years.

Accordingly, an object of the present invention is to provide a fast variable length code decoding apparatus capable of further improved high speed operation due to structural improvement.

In order to achieve the object described above, a bit stream of an input variable length code is latched, and a first length signal of the latched bit stream data is latched. A first processor for outputting a variable length code data of a predetermined number of bits from the bit position shifted in response, and a variable length code data of a predetermined number of bits provided from the first processor, and latching the latched variable length. A variable length code having a second processor for outputting variable length code data of a predetermined number of bits from a bit position shifted in response to a second length signal of the code; and a variable length code of a predetermined number of bits provided from the interface unit. Detects a code word which is a meaningful variable length code section among data and decodes the detected code word. A decoding unit for outputting a decoded word, outputting the number of bits of the detected code word as a length signal, and latching the length signal provided from the decoding unit, the length signal in response to a clock signal. The fast variable length code decoding apparatus of the present invention having a control unit for outputting the control unit to the interface unit comprises: a first control unit for latching a length signal provided from the decoding unit in response to a falling edge of a clock signal; A latch portion 310; A second latch unit for latching a length signal provided from the decoder in response to a rising edge of a clock signal; A first adder which adds and outputs length signals provided from the first and second latch units; A signal is received from the first latch unit and the first adder, the length signal provided from the first latch unit in response to the falling edge of the clock signal, and the first adder in response to the rising edge of the clock signal. A selection unit for outputting a signal provided from the second processing unit as a second length signal; A first accumulating unit accumulating and outputting a length signal provided from the first latch unit; A second accumulating unit which accumulates and outputs the length signal provided from the second latch unit; And a second adder that adds signals provided to the first and second accumulators and outputs the first length signal to the first processor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram schematically illustrating an operation of the fast variable length code decoding apparatus according to the present invention, and includes an interface unit 100, a decoder 200, and a controller 300.

The interface unit 100 includes first and second processing units 120 and 140, and the first processing unit 120 includes a bit stream of a variable length code transmitted from a transmitting end (not shown). Latch the bitstream data at a constant rate from a buffer unit (not shown) that temporarily stores data, and accumulate the length signal (1) provided from the controller 300 to be described later among the latched bitstream data. In response to the Accumulated Length Signal), a variable length code of a predetermined number of bits is output from the shifted bit position. The second processor 140 latches a variable length code of a predetermined number of bits provided from the first processor 120, and responds to a length signal provided from the controller 300, which will be described later, among the latched variable length codes. Outputs a variable length code of a predetermined number of bits from the shifted position.

The variable length code of the predetermined number of bits output from the interface unit 100 by the above-described process is input to the decoder 200, and the decoder 200 has a meaningful variable length code among the input variable length codes. A section, that is, a code word is detected, a decoded word is output by decoding the detected code word, and the number of bits of the detected code word is output as a length signal. In this case, the decoded word passes through a subsequent line length encoder (not shown) and an inverse quantizer (not shown), and the length signal is provided to the controller 300.

The controller 300 includes first and second latches 310 and 320, a first adder 330, a selector 340, first and second accumulators 350 and 360, and a fourth adder 370. It consists of. In this case, the first accumulator 350 includes a second adder 352 and a third latch 354, and the second accumulator 360 includes a third adder 362 and a fourth latch 354. .

The operation of the fast variable length code decoding apparatus according to the present invention configured as described above will be described in more detail.

First, bitstream data having a variable length code transmitted from a transmitting end (not shown) is temporarily stored in a buffer unit (not shown) and then provided to the first processing unit 100 at a constant rate. At this time, the first processing unit 120 includes a latch unit (not shown) and a barrel shifter (not shown), so that the input bitstream data is latched to the latch unit (not shown) and provided to the barrel shifter (not shown). . The barrel shifter (not shown) outputs the input bitstream data in units of a predetermined number of bits. The barrel shifter (not shown) varies the preset number of bits starting from the shifted bit position in response to the accumulated length signal provided from the controller 300. Output length code. For example, if the accumulated length signal provided from the control unit 300 is 8 bits and the preset number of bits to be output is 48 bits, starting from the position of the upper 9 bits of the bitstream data input from the buffer unit (not shown), the 48 bits are stored. Outputs the variable length code of the bit. The 48-bit variable length code output from the first processor 120 is provided to the second processor 140.

Like the first processing unit 120, the second processing unit 140 includes a latch unit (not shown) and a barrel shifter (not shown). Accordingly, the 48-bit variable length code provided from the first processing unit 120 is latched by the latch unit (not shown) and provided to the barrel shifter (not shown). At this time, as in the first processing unit 120, the barrel shifter (not shown) outputs the input bitstream data in units of a predetermined number of bits, and shifts the seat in response to the length signal provided from the controller 300. Outputs a variable length code of a predetermined number of bits starting from the specified position.

Through the above-described process, the 48-bit variable length code output from the second processor 140 is input to the decoder 200. The decoding unit 200 is a decoding table means using known decoding table means used in a conventional variable length code decoding apparatus, that is, PLAs (PLAs), which is meaningful among the input 48-bit variable length codes. A code word is detected, the detected code word is decoded to output a decoded word, and the number of bits of the detected code word is output as a length signal. For example, if the detected protection word is 3 bits, the decoding unit 200 outputs a 3-bit length signal.

2 is an exemplary timing diagram for explaining an operation of the controller 300, (A) is a clock signal, (B) is a length signal output from the decoder 200, (C) is The length signal latched in the first latch 310, (D) is the length signal latched in the second latch 320, (E) is a signal added and output from the first adder 320, (F) is a selector The length signal outputted from 340 (or inputted to the second processor 140), (G) is added to and output from the second adder 352, and (H) is transmitted to the third latch 354. The latched signal, (I), is added to and output from the third adder 362, (J) is latched to the fourth latch 364, and (K) is added and output from the fourth adder 370. It is a signal to be input (or input to the first processing unit 120).

Now, the operation of the controller 300 will be described in more detail with reference to the timing diagram of FIG. 2.

Assuming that the period of the clock signal is as shown in FIG. 3A, the length signal output from the decoder 200 is shown in FIG. In other words, length signals such as 3 bits, 5 bits, 2 bits, 7 bits, 3 bits, 5 bits, 6 bits, 7 bits, etc. are sequentially output for each cycle of the clock signal.

The first and second latches 310 and 320 latch the length signal output from the decoder 200 in response to the falling edge and the rising edge of the clock signal, respectively. In more detail, the first latch 310 receives the length signal of 3 bits, 2 bits, 3 bits, and 6 bits from the decoder 200 in response to the falling edge of the clock signal. Latch as shown in the figure. On the other hand, the second latch 320 in response to the rising edge of the clock signal, the length signal 5 bits, 7 bits, 5 bits, 7 bits output from the decoder 200 shown in the second (D) Latch as shown. As a result, the length signal output from the decoder 200 is alternately latched to the first latch 310 and the second latch 320 at every half period of the clock signal.

Subsequently, the length signal latched to the first latch 310 is provided to the first adder 330, the selector 340, and the first accumulator 350, and the length signal latched to the second latch 310. Is provided to the first adder 330 and the second accumulator 360.

In FIG. 2E, the first adder 330 adds and outputs the length signals provided from the first and second latches 310 and 320, 8 bits (3 + 5), 8 bits, and (5). +2) 7 bits, (2 + 7) 9 bits, (7 + 3) 10 bits, (3 + 5) 8 bits, (5 + 6) 11 bits, (6 + 7) 13 The bit is shown.

FIG. 2 (F) also shows the signal output from the selection unit 340 at the falling edge and rising edge of every clock signal. More specifically, the selector 340 receives a signal provided from the first latch 310 and the first adder 330. The selector 340 attempts to output the length signal provided from the first latch 310 in response to the falling edge of the clock signal, while the signal provided from the first adder 330 in response to the rising edge of the clock signal. Outputs At this time, since the signal output from the selector 340 is provided to the second processor 140 as a length signal, the second (F) diagram is sequentially output from the selector 340 or the second processor 140. 3 bits, 8 bits, 2 bits, 9 bits, 3 bits, 8 bits, 6 bits, and 13 bits are sequentially shown.

Subsequently, the second adder 352 of the first accumulator 350 adds and outputs the length signal currently provided from the first latch 310 and the signal output from the third latch 354. The signal output from the adder 352 is shown in FIG. At this time, the third latch 354 sequentially latches the signal provided from the second adder 352 in response to the falling edge of the clock signal, as shown in FIG. The signal latched to the third latch 354 is provided to the second adder 352 as a preceding length signal and added to the currently provided length signal.

On the other hand, the third adder 362 of the second accumulator 360 adds and outputs the length signal provided from the second latch 320 and the signal provided from the fourth latch 364. The signal output from 362 is shown in FIG. 2 (I). At this time, the fourth latch 364 sequentially latches the signal provided from the third adder 352 in response to the rising edge of the clock signal. The signal latched to the fourth latch 364 is provided to the third adder 362 as the preceding length signal and added to the currently provided length signal.

In this manner, the signals output from the second and third adders 352 and 362 are input to the fourth adder 370. FIG. 2 (K) shows signals added and output from the fourth adder 370, that is, accumulated signals 3 bits, 8 bits, 10 bits, 17 bits, 20 bits, 25 bits, 31 bits, and 38 bits. have. At this time, the first processor 120 outputs a 48-bit variable length code starting from the shifted bit position in response to the accumulated signal output from the fourth adder 370.

As a result, the fast variable length code decoding apparatus according to the present invention has a great advantage that the operation speed of the decoding apparatus can be further improved by decoding the code word every half cycle of the clock signal by improving the structure.

Claims (1)

Latching a bit stream of an input variable length code, and relocating from a bit position shifted in response to a first length signal of the latched bit stream data. Latching a first processor 120 for outputting variable length code data of a set number of bits and variable length code data of a predetermined number of bits provided from the first processor 120, and among the latched variable length codes. An interface unit 100 having a second processor 140 for outputting variable length code data of a predetermined number of bits from a bit position shifted in response to a second length signal, and provided from the interface unit 100. Decoded word (Dec) by detecting a code word which is a meaningful variable length code section among variable length code data of a predetermined number of bits and decoding the detected code word odd word), and outputs the number of bits of the detected code word as a length signal, and latches the length signal provided from the decoder 200, in response to a clock signal. In the fast variable length code decoding apparatus having a control unit 300 for outputting the length signal to the interface unit 100, the control unit 300 in response to the falling edge of the clock signal, the decoding unit A first latching unit 310 for latching a length signal provided from 200; A second latch unit 320 for latching a length signal provided from the decoder 200 in response to a rising edge of a clock signal; A first adder 330 for adding and outputting length signals provided from the first and second latch units 310 and 320; The signal is input from the first latch unit 310 and the first adder 330, and the length signal provided from the first latch unit 310 is increased in response to the falling edge of the clock signal. A selector 340 for outputting a signal provided from the first adder 330 to the second processor 140 as a second length signal in response to an edge; A first accumulator 350 accumulating and outputting a length signal provided from the first latch unit 310; A second accumulator 360 accumulating and outputting the length signal provided from the second latch unit 320; And a second adder 370 that adds signals provided from the first and second accumulators 350 and 360 and outputs the first length signal to the first processor 100 as a first length signal. Length code decoder.