KR950002251A - Variable length code decoding device - Google Patents
Variable length code decoding device Download PDFInfo
- Publication number
- KR950002251A KR950002251A KR1019930012112A KR930012112A KR950002251A KR 950002251 A KR950002251 A KR 950002251A KR 1019930012112 A KR1019930012112 A KR 1019930012112A KR 930012112 A KR930012112 A KR 930012112A KR 950002251 A KR950002251 A KR 950002251A
- Authority
- KR
- South Korea
- Prior art keywords
- variable length
- code
- signal
- value
- length
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3084—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction using adaptive string matching, e.g. the Lempel-Ziv method
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
본 발명은 가변길이 부호화된 영상신호를 가변길이 복호화 하는데 있어서 그 처리속도를 증진시킴과 동시에 데이타를 처리하는 장치를 간소화하기 위한 것으로, 버퍼에 저장된 가변길이 부호화된 데이타신호를 독취신호 발생수단으로부터의 제어신호에 따라 출력하여 신호처리수단을 통해 처리한 다음 복호테이블 수단을 통해 가변길이 복호화하는 가변길이 복호화장치에 있어서, 신호처리수단은, 클럭신호에 동기되어 버퍼로부터 출력되는 가변길이부호 데이타신호를 래치하는 제1래치수단과, 버퍼로부터 출력되는 가변길이부호 데이타신호를 하위비트로 하고, 제1래치수단으로부터의 래치된 가변길이부호 데이타 신호를 상위비트로 하여, 일측에 접속된 제2래치수단으로부터의 시프트값에 의거하여 시프트되는 가변길이부호 데이타신호를 복호 테이블에 출력하는 베렐시프트부와, 복수의 비트라인을 통해 부호길이 테이블로부터 입력된 부호길이값과 이전의 부호길이값에 따라 다음 가변길이부호에 대한 시프트값을 할당하고, 갱신된 부호길이값이 가변길이 부호의 부호길이값 이상일때 독취신호 발생수단으로 캐리를 출력하는 가산수단과, 가산수단의 갱신된 부호 길이값을 클럭신호에 동기되어 베렐시프터부에 시프트값으로 출력하는 제2래치수단으로 구성한 것이다.The present invention aims to increase the processing speed in variable length decoding of a variable length coded video signal and to simplify an apparatus for processing data, wherein the variable length coded data signal stored in a buffer is read from the read signal generating means. A variable length decoding apparatus for outputting in accordance with a control signal, processing the signal through a signal processing means, and then performing variable length decoding using a decoding table means, wherein the signal processing means is configured to output a variable length code data signal output from a buffer in synchronization with a clock signal. The first latch means for latching and the variable length code data signal output from the buffer are the lower bits, and the latched variable length code data signal from the first latch means is the upper bit, and the second latch means connected to one side is connected. Decode the variable length code data signal shifted based on the shift value And a shift value for the next variable length code according to the code length value and the previous code length value inputted from the code length table through a plurality of bit lines and a plurality of bit lines. Addition means for outputting a carry to the read signal generating means when the code length value of the variable length code is equal to or greater than the code length value; and second latch means for outputting the updated code length value of the addition means as a shift value to the bevel shifter in synchronization with a clock signal. It is made up.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 따른 가변길이부호 복호화장치의 블럭 구성도, 제2 및 제3도는 제1도에 도시된 본 발명의 가변길이부호 복호화장치에 채용되는 베렐시프터의 흐름도와 타이밍도.1 is a block diagram of a variable length code decoding apparatus according to the present invention, and FIGs. 2 and 3 are flowcharts and timing diagrams of a berel shifter employed in the variable length code decoding apparatus of the present invention shown in FIG.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930012112A KR960011111B1 (en) | 1993-06-30 | 1993-06-30 | Variable length decoder of digital image signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930012112A KR960011111B1 (en) | 1993-06-30 | 1993-06-30 | Variable length decoder of digital image signal |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950002251A true KR950002251A (en) | 1995-01-04 |
KR960011111B1 KR960011111B1 (en) | 1996-08-20 |
Family
ID=19358346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930012112A KR960011111B1 (en) | 1993-06-30 | 1993-06-30 | Variable length decoder of digital image signal |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960011111B1 (en) |
-
1993
- 1993-06-30 KR KR1019930012112A patent/KR960011111B1/en not_active IP Right Cessation
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Publication number | Publication date |
---|---|
KR960011111B1 (en) | 1996-08-20 |
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