KR970019260A

KR970019260A - A high-speed parallel block encoder

Info

Publication number: KR970019260A
Application number: KR1019950032590A
Authority: KR
Inventors: 권오상
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1995-09-29
Filing date: 1995-09-29
Publication date: 1997-04-30

Abstract

본 발명은 블록 부호에 있어서, 블록 단위로 병렬화수 M 만큼 스위칭하는 입력스위칭부(401); 해당 스위치로부터 블록을 입력받아 속도를 낮추어 선입선출식으로 출력하는 입력 버퍼메모리부(402); 해당 버퍼에서 입력받은 데이터를 블록보호화하여 순차적으로 출력하는 M개의 병렬 블록복호기부(403); 해당 복호기로부터 입력받은 복호화된 데이터를 감속하여 선입선출식으로 출력하는 출력 버퍼메모리부(404)로 구성되어 기존의 비교적 저속의 복수개의 블록복호기를 병렬로 연결하여 고속화된 병렬 블록복호기를 제공할 수 있어 기존의 설계 자원을 사용할 수 있고 고속소자를 사용하지 않아도 되며, 병렬 및 파이프라인 방식과 같이 많은 하드웨어 자원을 사용하지 않고도 고속화할 수 있는 효과가 있다.The present invention provides a block code, comprising: an input switching unit 401 for switching by the parallelization number M in units of blocks; An input buffer memory unit 402 for receiving a block from the switch and lowering the speed to output a first-in, first-out type; M parallel block decoders 403 for block-protecting the data input from the buffer and sequentially outputting the data; It consists of an output buffer memory unit 404 that decelerates the decoded data received from the decoder and outputs it on a first-in, first-out basis, thereby providing a parallel block decoder that has been speeded up by connecting a plurality of existing relatively low speed block decoders in parallel. Therefore, existing design resources can be used, high speed devices can be used, and high speed can be achieved without using many hardware resources such as parallel and pipeline methods.

대표도면 : 제5도Representative drawing: 5th

Description

A high-speed parallel block encoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 고속 병렬복호기를 도시한 블록도.5 is a block diagram showing a high speed parallel decoder according to the present invention.

제6도는 무궁화위성의 통신에 쓰이는 RS부호의 구성을 도시한 블록도.6 is a block diagram showing the configuration of the RS code used for communication of the Mugunghwa satellite.

제7도는 본 발명의 실시예에 따른 고속 병렬 블록복호기의 타이밍 관계를 도시한 타이밍도이다.7 is a timing diagram showing a timing relationship of a high speed parallel block decoder according to an embodiment of the present invention.

Claims

A decoder of a natural number n.k (n.k) block code, encoded at high speed, comprising: an input switching unit 401 for switching by a serialized number M in units of blocks; An input buffer memory unit 402 consisting of M FIFO buffers which receive one block of data from the corresponding input switch and decelerate and output the data; Receiving a data from the input buffer and performing block decoding, the parallel block decoder 403 including M block encoders; An output buffer memory unit 404 consisting of M FIFO buffers for restoring data decoded from the block decoder at an original speed and outputting the same; A high speed parallel block decoder, comprising: an output switching unit (405) for repeatedly outputting the decoded data in the order of the original input block by sequentially and repeatedly switching in units of blocks in synchronization with the corresponding output FIFO buffer.

The input FIFO buffers 402-1, 402-2, ..., 402- having the size of n * (M-1) / M symbols and an input / output speed ratio M: 1. A high speed parallel block decoder, characterized in that consisting of M).

2. The parallel block decoder of claim 1, wherein the parallel block decoder comprises block decoders 403-1, 403-2, ..., 403-M that receive data from an input FIFO buffer, block decode, and sequentially output every block time. A high speed parallel block decoder, characterized in that.

2. The output FIFO buffers 404-1, 404-2, ..., 404-, according to claim 1, wherein the output buffer memory section has a size of k * (M-1) / M symbols and an input / output speed ratio of 1: M. A high speed parallel block decoder, characterized in that consisting of M).

※ Note: The disclosure is based on the initial application.