KR970013793A - Device for decoding fixed length code - Google Patents

Device for decoding fixed length code Download PDF

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Publication number
KR970013793A
KR970013793A KR1019950028097A KR19950028097A KR970013793A KR 970013793 A KR970013793 A KR 970013793A KR 1019950028097 A KR1019950028097 A KR 1019950028097A KR 19950028097 A KR19950028097 A KR 19950028097A KR 970013793 A KR970013793 A KR 970013793A
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KR
South Korea
Prior art keywords
output
code
pointer
latch
outputting
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KR1019950028097A
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Korean (ko)
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KR0159654B1 (en
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김규석
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배순훈
대우전자 주식회사
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Priority to KR1019950028097A priority Critical patent/KR0159654B1/en
Publication of KR970013793A publication Critical patent/KR970013793A/en
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Publication of KR0159654B1 publication Critical patent/KR0159654B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

본 발명은 부호화된 고정길이부호를 역 부호화할 수 있는 고정길이부호를 디코딩하는 장치에 관한 것으로서, 부호화되어 전송되는 데이타 스트림을 인가받아 일시적으로 저장했다가 출력하는 버터(12)와, 버퍼(12)의 출력을 래치시켰다가 출력하는 제2래치(16)와 제2래치(16)의 출력을 래치시켰다가 출력하는 제1래치(14)와, 디코딩된 데이타에 대한 정보를 인가받아 디코딩할 부호의 비트수 신호를 출력하는 제어부(24)와, 제어부(24)로 부터 디코딩할 부호의 비트수 신호를 인가받아 디코딩할 부호의 길이를 결정하는 길이 결정부(26)와, 캐리 신호를 인가받아 데이타를 차례로 출력하는 포인터(30)와, 길이 결정부(26)의 출력과 포인터(30)의 출력을 가산해서 이에 따른 캐리를 포인터(30)에 인가하는 가산기(28)와, 포인터(30)의 출력에 의해 제1, 제2 래치(14,16)의 출력을 맨 처음으로 쉬프트시키는 쉬프터(18)와, 쉬프터(18)의 출력을 인가받아 이중에서 길이 결정부(26)에서 결정한 비트수만큼 출력하는 출력 제어부(20)와, 출력 제어부(20)의 출력을 인가받아 디코딩된 데이타를 출력하여, 그 디코딩된 데이타에 대한 정보를 제어부(24)에 인가하는 출력부(22)를 포함하여 이루어져서, 부호화된 고정길이부호를 역 부호화한다.The present invention relates to a device for decoding a fixed length code capable of inversely encoding an encoded fixed length code, comprising: a butter (12) and a buffer (12) for temporarily storing and outputting a data stream to be encoded and transmitted; The second latch 16 for latching and outputting the output of the second latch 16, the first latch 14 for latching and outputting the output of the second latch 16, and a code to receive and decode information about the decoded data. A control unit 24 for outputting a bit number signal of the signal, a length determining unit 26 for determining the length of the code to be decoded by receiving the bit number signal of the code to be decoded from the control unit 24, and a carry signal A pointer 30 for sequentially outputting data, an adder 28 for adding the output of the length determining unit 26 and the output of the pointer 30 and applying a carry to the pointer 30 accordingly, and the pointer 30. Output of the first and second latches 14 and 16 by the output of A shifter 18 for shifting the force for the first time, an output controller 20 that receives the output of the shifter 18 and outputs the number of bits determined by the length determiner 26, and the output controller 20 The output unit 22 receives the output, outputs decoded data, and applies information about the decoded data to the control unit 24 to decode the encoded fixed length code.

Description

고정길이 부호를 디코딩하는 장치Device for decoding fixed length code

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 고정길이부호를 디코딩하는 장치의 일 실시예를 나타낸 블럭도,1 is a block diagram showing an embodiment of an apparatus for decoding a fixed length code according to the present invention;

제2도는 제1도에 따른 각 부의 신호를 나타낸 파형도.2 is a waveform diagram showing signals of respective parts according to FIG. 1;

Claims (1)

부호화되어 전송되는 데이타 스트림을 인가받아 일시적으로 저장했다가 출력하는 버퍼(12)와; 상기 버퍼(12)의 출력을 래치시켰다가 출력하는 제2래치(16)와; 상기 제2래치(16)의 출력을 래치시켰다가 출력하는 제1래치(14)와; 디코딩된 데이타에 대한 정보를 인가받아 디코딩할 부호의 비트수 신호를 출력하는 제어부(24)와; 상기 제어부(24)로 부터 디코딩할 부호의 비트수 신호를 인가받아 디코딩할 부호의 길이를 결정하는 길이 결정부(26)와; 캐리 신호를 인가받아 데이타를 차례로 출력하는 포인터(30)와; 상기 길이 결정부(26)의 출력과 포인터(30)의 출력을 가산해서 이에 따른 캐리를 상기 포인터(30)에 인가하는 가산기(28)와; 상기 포인터(30)의 출력에 의해 상기 제1, 제2 래치(14,16)의 출력을 맨 처음으로 쉬프트시키는 쉬프터(18)와; 상기 쉬프터(18)의 출력을 인가받아 이중에서 상기 길이 결정부(26)에서 결정한 비트수만큼 출력하는 출력 제어부(20)와; 상기 출력 제어부(20)의 출력을 인가받아 디코딩된 데이타를 출력하며, 그 디코딩된 데이타에 대한 정보를 상기 제어부(24)에 인가하는 출력부(22)를 포함하여 이루어지는 고정길이부호를 디코딩하는 장치.A buffer 12 which temporarily receives a coded and transmitted data stream and stores the same; A second latch (16) for latching and outputting the output of the buffer (12); A first latch 14 for latching and outputting the output of the second latch 16; A control unit 24 which receives information on the decoded data and outputs a bit number signal of a code to decode; A length determining unit 26 receiving a bit number signal of a code to be decoded from the controller 24 and determining a length of a code to be decoded; A pointer 30 which receives a carry signal and sequentially outputs data; An adder (28) for adding the output of the length determining section (26) and the output of the pointer (30) and applying a carry accordingly to the pointer (30); A shifter (18) for first shifting the outputs of the first and second latches (14, 16) by the output of the pointer (30); An output control unit 20 which receives the output of the shifter 18 and outputs the number of bits determined by the length determining unit 26 among them; Apparatus for decoding fixed-length code comprising the output unit 22 receives the output of the output control unit 20 outputs decoded data, and applies information about the decoded data to the control unit 24 . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950028097A 1995-08-31 1995-08-31 Vlc KR0159654B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950028097A KR0159654B1 (en) 1995-08-31 1995-08-31 Vlc

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950028097A KR0159654B1 (en) 1995-08-31 1995-08-31 Vlc

Publications (2)

Publication Number Publication Date
KR970013793A true KR970013793A (en) 1997-03-29
KR0159654B1 KR0159654B1 (en) 1999-03-20

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KR1019950028097A KR0159654B1 (en) 1995-08-31 1995-08-31 Vlc

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