KR950023012A - CBP Processing Circuit of Digital Compressed Video Signal - Google Patents

CBP Processing Circuit of Digital Compressed Video Signal Download PDF

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Publication number
KR950023012A
KR950023012A KR1019930032050A KR930032050A KR950023012A KR 950023012 A KR950023012 A KR 950023012A KR 1019930032050 A KR1019930032050 A KR 1019930032050A KR 930032050 A KR930032050 A KR 930032050A KR 950023012 A KR950023012 A KR 950023012A
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South Korea
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run
level
cbp
signal
block
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KR1019930032050A
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Korean (ko)
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KR970003803B1 (en
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김영목
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이헌조
엘지전자 주식회사
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명은 디지탈 압축 영상신호의 코드화된 불록패턴 처리기술에 관한 것으로, 종래의 CBP처리기술에 있어서는 스킵된 블록에 대한 정보를 생성하는 동안 디코딩 동작을 중지하고 있어야 하므로 전체적인 평균 디코딩속도가 저하되게 되며, 일시저장소인 버퍼에 있어서도 디코딩을 빈번히 멈추게 되어 버퍼에 부담을 주게 되는 결함이 있었는 바, 본 발명은 이를 해결하기 위하여 CBP를 디코딩한 후 즉각적으로 한 매크로블록내의 스킵된 블록들에 대해 한번에 63.0의 런, 레벨 쌍을 발생시키고, 나머지 정보가 있는 블록들만을 순서대로 디코딩하게 되므로 디코딩이 연속적으로 이루어져 전체적인 처리속도가 그대로 유지되고, 앞의 버퍼에도 부담을 주지않게 되어 결과적으로 안정된 디코딩을 수행할 수 있다.The present invention relates to a coded block pattern processing technique of a digital compressed video signal. In the conventional CBP processing technique, since the decoding operation must be stopped while generating information on a skipped block, the overall average decoding speed is reduced. In order to solve this problem, the present invention solves the problem of skipping blocks in a macroblock immediately after decoding CBP. Run and level pairs are generated, and only the blocks with the rest of the information are decoded in order, so that the decoding is continuously performed so that the overall processing speed is maintained as it is. have.

Description

디지탈 압축 영상신호의 씨비피 처리 회로CBP Processing Circuit of Digital Compressed Video Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명 디지탈 압축 영상신호의 씨비피 처리 회로도.1 is a CBP processing circuit diagram of a digital compressed video signal of the present invention.

제2도는 제1도에서 전치디코더의 입출력 설명도.2 is an explanatory diagram of input and output of the predecoder in FIG.

Claims (1)

인에이블신호(CBP-EN)의 제어를 받아 매크로블록내의 각 블록들의 계수정보 유,무를 알리는 데이타(CBPO-CBP5)를 블록수단만큼의 비트수로 출력하는 씨비피 디코더(1)와, 상기 씨비피 디코더(1)에서 출력되는 데이타(CBP-CBP5)를 래치하는 래치부(2)와 상기 래치부(2)의 출력데이타를 공급받아 순서상 다음에 오는 계수정보가 해당하는 블록에 대해서만 "1"을 출력하고, 나머지 블록에 대해서는 "0"을 출력하는 전치 디코더(3)와, 상기 전치 디코더(3)의 출력데이타를 래치하는 래치부(4)와, 상기 전치 디코더(3)를 통하기 이전의 신호(CBP_L[0...5])를 반전출력하는 인버터(8)와, 상기 인버터(8)를 통해 반전된 신호와 한 클럭 지연된 인에이블신호(CBP-EN)를 앤드조합하여 인에이블신호(B_EN[0...5])를 출력하는 앤드게이트(9)와, 상기 앤드게이트(9)에서 출력되는 인에이블신호(B_EN[0...5])와 상기 래치부(4)에서 출력되는 신호(PO-P5)를 오아연산하여 선입선출기(6)의 라이트인에이블신호(WE)로 공급하는 오아연산부(5)와, 계수정보임을 알리는 계수정보신호(COEF_EN)를 공급받아 다음에 입력되는 코드들을 런,레벨 쌍으로 디코딩하고, 블록내에 전송해야할 런,레벨 쌍은 끝나고 나머지 계수정보는 모두 "0"이라는 것을 나타내는 EOB 코드를 디코딩하는 계수디코더(11)와, 매 블록마다 런,레벨(RUN, LEVEL)쌍과 EOB 코드를 공급받아 그 블록의 런,레벨(RUN, LEVEL)쌍의 총합이 전체 갯수에 이르지 못하고 EOB 코드가 입력되면 나머지 갯수만큼의 런,레벨(RUN,LEVEL)쌍을 강제로 생성하는 엑스트라 런/레벨 발생기(12)와, 인에이블신호(CBP_EN_L)에 따라 스위칭되어 상기 엑스트라 런/레벨 발생기(12)의 출력이나 기 설정된 런,레벨값(63,0)을 선택적으로 출력하는 멀티플렉서(13)와, 상기 오아연산부(5)로 부터 공급되는 라이트인에이블신호(WE)의 제어에 따라 상기 멀티플렉서(13)의 출력데이타를 해당 블록에 저장하는 선입선출부(6)로 구성한 것을 특징으로 하는 디지탈 압축 영상신호의 씨비피 처리 회로.CB decoder 1 for outputting data CBPO-CBP5 indicating the presence / absence of coefficient information of each block in the macroblock under the control of the enable signal CBP-EN in the same number of bits as the block means; The latch unit 2 for latching the data CBP-CBP5 outputted from the decoder 1 and the output data of the latch unit 2 are supplied to the block corresponding to the corresponding coefficient information in sequence. ", And outputs" 0 "for the remaining blocks, the latch unit 4 for latching the output data of the predecoder 3, and the predecoder 3 before passing through the predecoder 3; The inverter 8 which inverts and outputs the signal CBP_L [0 ... 5] and the signal inverted by the inverter 8 and the enable signal CBP-EN delayed by one clock are AND-combined and enabled. An AND gate 9 which outputs a signal B_EN [0 ... 5], and an enable signal B_EN which is output from the AND gate 9. [0 ... 5]) and an OR operation unit 5 for supplying the signal PO-P5 output from the latch unit 4 to the write enable signal WE of the first-in-first-out-outer 6. And decodes the next input codes into run and level pairs by receiving the coefficient information signal COEF_EN indicating the coefficient information and indicates that the run and level pairs to be transmitted in the block are over and the remaining coefficient information is all "0". The coefficient decoder 11, which decodes the EOB code, receives run, level (RUN, LEVEL) pairs and EOB codes for each block, and the sum of the run and level (RUN, LEVEL) pairs of the block does not reach the total number. When the EOB code is input, the extra run / level generator 12 forcibly generating the remaining number of run and level pairs and the enable signal CBP_EN_L are switched to switch the extra run / level generator ( 12) or a mult that selectively outputs the preset run and level values (63,0). And a first-in, first-out unit (6) for storing output data of the multiplexer (13) in the corresponding block under the control of the write enable signal (WE) supplied from the oar unit (5). CBP processing circuit of a digital compressed video signal, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930032050A 1993-12-31 1993-12-31 Cbp processing circuit for digital coding imagery KR970003803B1 (en)

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Application Number Priority Date Filing Date Title
KR1019930032050A KR970003803B1 (en) 1993-12-31 1993-12-31 Cbp processing circuit for digital coding imagery

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Application Number Priority Date Filing Date Title
KR1019930032050A KR970003803B1 (en) 1993-12-31 1993-12-31 Cbp processing circuit for digital coding imagery

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KR950023012A true KR950023012A (en) 1995-07-28
KR970003803B1 KR970003803B1 (en) 1997-03-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100478293B1 (en) * 2002-01-02 2005-03-24 (주)씨앤에스 테크놀로지 Video Signal Encoding/Decoding Method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100478293B1 (en) * 2002-01-02 2005-03-24 (주)씨앤에스 테크놀로지 Video Signal Encoding/Decoding Method

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