JPS58170280A - Decoding system of mh code - Google Patents

Abstract

PURPOSE:To perform speed-up of the system with one access time of an ROM, by storing not only a run length (RL) code but also the number of code bits in the ROM, in a decoding circuit of modified Haffmann (MH) code having the ROM. CONSTITUTION:The code length of the RL and MH codes are stored in the respective addresses of the two ROMs 12, 13 as data. When a clock is given from a shift circuit 18 to a shift register 11 at first and the 1st EOL code of the MH code train is set to the register, a gate 16 detects it and outputs (0) then stops the clock of a circuit 18, and since the head 4-bit is (0), a gate 15 is (0), the ROM 12 is accessed, the RL=(0) and the EOL code length 12 are outputted as outputs, the shift circuit 18 generates 12 pieces of clock for shift control. When the white run 25 is set, since (1) is included in the head 4-bit, (1) is outputted from the gate 15, the ROM 13 is selected and RL=(25) and the bit length are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a device for converting compressed data band-compressed by the MH (four-difference Huffman) encoding method back to image data, in which an MH code is decoded. The method relates to a method for determining the run length of the code, and in particular, it is an M method that enables high-speed code decoding and simplifies the circuit configuration and circuit operation.
Regarding the HH code decoding method.

(2) Prior Art and Problems MH codes are widely used to compress and transmit image signals. Since this MH code does not have information indicating the code length or code breaks, a ROM (Read 0nl) that stores the information and RL (run length) essential for code deciphering is used.
y Memory ) from this I'tOM to RL
A common method is to calculate Methods for using this ROM include a hash method, a linear search method, a tree search method, etc., but the hash method will be explained here.

FIG. 1 shows an example of a circuit for the HATSH method. Here, 1 is a 12-bit shift register into which the code bit is input, 2 is a ROM, and a confirmation bit indicating that RL and RL are stored at an address equal to the bit pattern of the code (here, for the sake of explanation) ``1'') is stored.

3 is a latch that temporarily stores the output of ROM 2; 4 is a shift circuit that generates one clock when the confirmation bit "1" is not output; and shifts the sign bit of shift register l; 5 is a shift circuit; This is a flip-flop (hereinafter referred to as FF) that indicates whether the code being decoded is a white run or a black run.

The operation of FIG. 1 is as follows. First shift register 1
As shown in FIG.
The first 1 bit of the code (in this case, it is "0")
) to access the ROM2t. At this time, the ROM
If the confirmation bit "1" is not output from the shift register 2, one clock is generated by the shift I circuit 4, the next transmission code is read into the shift register, and "0.0" is input. As a result, when the confirmation bit "1" is not output even if ROM2 is accessed, 1, /7) ayu4. ,Beauty,. 5, 5, 5, (/ Input the next sign bit into the register. EOL
' code, the first 11 bits are all rO
J, so the confirmation bit "1" is not output in ROM2,
When such a process is repeated and the 12th bit "1" is input, that is, when the EOL code is input to the shift register, the ROM 2 outputs a confirmation bit "1". In the case of this EOL code, the latch 3 does not output RL. The confirmation bit "1" sets the FF 5 to a constant state, and the shift circuit 4 clears the shift register 1 accordingly.

Therefore, the shift circuit 4 writes one bit of the next code into the shift register 1 again and accesses the ROM 2 seven times, but as shown in FIG. The confirmation bit "1" is not output until the white run 25 code (referred to as run 25) is set in shift register 1, and when this white run 25 code is set, the 7 bit r 010101 set in shift register 1
1 ROM2 is RL r21 according to the output of J and FFs
sJ, thereby causing the latch 3 to output RLr25J and also output a confirmation bit "1". Since the next color after this RL 2 B11EOL is white, it can be seen that this is white run 25. and shift circuit 4
&1 As a result, shift register 1 is cleared again and latch FF5 is inverted. This process is repeated and the RL is output, but at this time, on the receiving side,
RL is 6x more powerful than white, so
Images can be reproduced using only the RL.

In this way, in the 71-tshu method, the number of times the ROM 2 is accessed is equal to the number of code bits, so it is difficult to perform high-speed decoding processing (for example, in 1fEOL, the output card can only be obtained after 12 accesses). Furthermore, each time the ROM 2 is accessed, it is necessary to confirm the presence or absence of an output from the ROM using a confirmation bit, which has the disadvantage that the circuit configuration and circuit operation become complicated.

Note that the linear search method and the tree search method also have similar drawbacks.

(3) Purpose of the invention The purpose of the present invention is to improve the above drawbacks by
It is an object of the present invention to provide an MH code Nm method that performs H code decoding processing at high speed and has a simple circuit configuration and circuit operation.

(4) Structure of the Invention In order to achieve this object, the MH code decoding method of the present invention includes a shift register for inputting coded bits and a code RO (RO that uses the turn as the address and stores the run length indicated by the code and the number of code bits)
M, and a shift circuit that generates a shift clock equal to the number of code bits in the ROM to shift the code bits of the shift register, and when a run length is obtained from the ROM, the shift circuit shifts the shift register to the code bit of the shift register. The feature is that the number of bits is shifted by 5 depending on the bit.

(5) Embodiment of the Invention Before going into detail based on an embodiment of the present invention, an outline of the present invention will be explained.

Since the MH code does not include information indicating the code length and breaks between codes, the R of the code to be decoded from the ROM is
It takes many Japanese patent publications to search for L. Therefore, in the present invention, the code bit pattern is used as a ROM address, and not only the RL but also the number of code bits is stored in the memory corresponding to the address. Then, the address bits of the ROM of the shift register, that is, the code bits, are shifted by the number of bits of the code that has been decoded, and the code is set at the next ROM address to obtain RL. By repeating this operation, you can quickly decode the code (compressed data) j! The longest MH code is 12 bits, and the total of this code and 1 bit of FF indicating black and white is 1.
21 to use 31t as the ROM address.
Three words of Meminesu are required. However, in the MH code, the first 4 bits of all codes of 10 bits or more are rOJ, so by identifying this and converting it to 1 bit,
The memory capacity of the ROM can be reduced to 216 words x2.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 3 shows a configuration diagram of an embodiment of the present invention, and FIG. 4 shows an RO
It is an explanatory diagram of the address of M.

In the figure, 11 is a shift register, and 12 is a first ROM.

13 is a second ROM, 14 is an FF, 15 and 16 are OR gates, 17 is a latch, 18 is a shift circuit, and 19.20 is an inverter.

Shift register 11 is a 12-bit shift register into which an MH code, which is a variable length code, is input, and corresponds to shift register 1 in FIG.

The first ROM 12 is a ROM that is accessed when the MH code is 10 bits or more, and the bit length of the accessed code is also stored outside the RLO. Also the second
The ROM 13 is a ROM that is accessed when the MH code is a code of 9 bits or less, and like the first ROM 12, the R
In addition to L, the bit length of the accessed code is also stored.

Since these first ROM 12 and second ROM 13 are the characteristics of the present invention, they will be described in more detail. As described above, each of these ROMs stores the code lengths of the RL and MH codes as data.

For example, when the EOL (12-bit) code shown at the beginning of FIG. 20 becomes “1” @IROMI 2 chip select terminal CS, Iln
When rlJ is applied, this first ROM 12 is selected. And the next 8 bits are the 1st ROMI! The address terminals Ao-AyK are transmitted.

At this time, $, FF14 outputs "1" and address terminal A
8. However, as shown in Figure 4,
When the first ROM 12 is accessed with this EOL code, it is treated as FLOM data, CRL = "0", bit length =
412J is output and set in latch 17. Next, as in the second group in FIG.
Since the voltage is applied to the chip select terminal C8 of M13, this second ROM 13 is selected. At this time, the FF14 is inverted by the bit length signal of the previous EOL code, and "0" is input to A8. The 7-bit address r0101011J is the AO of the second ROM13.
~ When applied to A6, the second ROM 13 outputs RL=r25J, bit length=“7” as data, regardless of whether rob or rlJ is applied to A1, and this bit length is “7”. Q18 is applied.

In the shift register 11, a 12-bit code indicating black run 28 as the third group r 000011001100 J
When is set, the FF 14 is inverted by the second group's access and outputs "1" indicating black, so the first ROM 12 is accessed by these 12 bits. That is, the first 4 bits r 00
00 J, the OR gate 15 outputs rOJ and the inverter 20 outputs "1", so the first ROM
12 is selected. and the remaining 8 bits r 11
001100J is applied to Ao-Ay, and when the FF
14 is applied to A8, so the first ROM12
As the output data, RL=r28J, bit length - "1
2" is output.

Then, as the fourth group, a 4-bit code r indicating a white run.
When 1111 J is set at the beginning of the shift register 11, no matter what is being transmitted to A4 to A7 of the second ROM 13 at this time, the second ROM 13 outputs RL = r.
7J, bit length = "4" is output. In this way, the first ROM 12 and the second ROM 13 are each accessed according to the MH code, and output the RL and the bit length of the accessed M)I code.

Incidentally, the MH code is a variable length code of 2 to 12 bits, and in actual data, these codes are randomly consecutive. Then, no matter what code comes after the code that is 1 when trying to decode it, the correct data must be output from the ROM. For this purpose, as shown in FIG. 4, a redundant bit is added to the bit pattern of the code to configure the ROM address. For example, in the case of EOL, A8 is a redundant bit, and for white ramp,
4-At is a redundant bit. All combinations of redundant bits, that is, when the number of redundant bits is m, 27''rn combinations are possible, and the same length and bit length (number of code bits) are stored for all addresses.

FF14 determines whether the code being decoded is black or white and corresponds to the FFs in FIG.
The signal is inverted when an output is generated from either the second ROM 13 or the second ROM 13. Mo and EOL
is set to output "0" when detected.

The OR gate 15 determines that when the MH code is 10 bits or more, the next 1j4 bits are all "0" □□L,?
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The OR gate 16 detects the EOL code, outputs "0" only when the EOL code is set in the shift register 11, detects the EOL that appears every line, and synchronizes the circuit operation with the code. I'm checking to see if it's working.

The latch 17 is the first ROMI 2 or the second I'L
RL and bit length (number of code bits) output from OM13
This is a latch that temporarily holds the .

The shift circuit 18 inputs the pin) & of the latch 17, generates the same number of clocks, and operates the shift register 1.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to FIG. 4, taking as an example the case where the code string shown in FIG. 2 is decoded.

■ First, the shift circuit 18 sends a clock to the shift register 11, and when the first EOL code of the M)I code string is set in the shift register 11, the OR gate 1
6 detects this and outputs "0" to stop the clock of shift n path 18. And this EOL and the first ROM
12 addresses. At this time, the first 4 of EOL
Since the bits are all "0", the OR gate 15 is "0".
” and the inverter 20 outputs “1”, so
The first ROM+2 will be accessed. Mote E
5th bit to 12th bit of OL r 0000000
1 J is transmitted to A (1 to A) of the first ROM 12, and as shown in FIG.
L=zero and a bit length "12" indicating the EOL code length are output and set in the latch 17. And this bit length '
12'' is transmitted to the shift circuit 18, whereby the shift circuit 18 generates 12 clocks [shift register 1
1 to shift control.

■ This shift control allows the EO in the shift register 11 to
L is shifted, and the white run 25 (0101011) of the second group is set at the beginning of the shift register 11 this time. Since this code includes "1" in the first 4 bits, "1" is output from the OR gate 15 and the second f'
LOM13 is selected. And this second ROM
The above (0101011) is transmitted to AO to A6 of 13, and as shown in FIG. 4, no matter what is applied to Ay, the 2R
RL=r25J and bit length=“7” are output from OM13, and the fist RL=r25J is set in latch 17.
is sent to the next stage processing circuit (not shown). Further, the bit length "7" is sent to the shift circuit 18, and the bit length "7" is sent to the shift circuit 18.
8, the code (0101011) is the same as in the case of EOL.
Generate 7 clocks equal to the bit length of , shift this code (0101011) in the shift register 11,
Next 3rd group black run 28 (000011001100)
is set at the beginning of the shift register 11. In this way, similarly to the above case, from the first ROM 12, RL=r
28J, bit length=r12J is output, and this is set to 2×17. Thereafter, similar control is performed, and code decoding is performed sequentially in the order of white run, black run 9, white run 10, and so on.

, 1 At this time, the FF 14 is inverted every time data is output from the rear chip 17, and judges whether the code being decoded is a white run or a dot run.

Needless to say, it can also be used to decode a -dimensional code (MH code).

(6) Effect of the invention When the MH code is decoded using this method, like the conventional method,
There is no need to check the ROM output every time one bit is shifted. Therefore, the circuit can operate at high speed and the circuit configuration can be simplified. Also, the number of code bits (bit length) of the MH code
Since the ROM data contains ROM data, the ROM only needs to be accessed once for one code, which simplifies the configuration of the code decoding circuit and enables high-speed processing.

[Brief explanation of the drawing]

FIG. 1 is a conventional configuration diagram, FIG. 2 is a MH code string, FIG. 3 is an embodiment configuration of the present invention, and FIG. 4 is a configuration diagram of a ROM of the present invention. In the figure, 11 is a shift register, 12 is the first rtOM, 1
3 is a second ROM, 14 is an FF, 15 and 16 are OR gates, 17 is a latch, 18 is a shift circuit, and 19.20 is an inverter. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Yamatani 1m Tz! 1 fOL 69>21, @5>U
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000100 00111'2-4 Figure Director of the Patent Office Blind Waka # Kazuo Trial 1, Incident tal&$ 188B1 year 41tWIIIA
No. 52191 vsoa name MH code decoding method TM correction case and ○- Patent applicant address Mr. 4, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa (s22) Representative of Fujitsu Kinsha Takashi Yamamoto 4. Agent amendment O Contents 1. Described on page 7, line 14 of the specification 9 "Kari issue printing"
Correct X to be a "code string". 2 Insert the following sentence between the black line and the 4th line on page 1114 of Okaj. "-11 Raniman I ROM12. III 2 ROM
Instead of 1 l. By using ζ7 using multipletana, it is possible to combine ROM into one. Shift register 1 may be output 1, 110th M12, 2nd
Instead of leading the 2-channel OFF signal led to ROMIN to these two ROMs 12 and 11, it is input to the multi-brake/l not shown, and the output signal of the OR get 15 is used to switch and control the O multiplex. Yoshi upper le2 system O
One of the signals O and O is outputted from the multiplex converter. ”The output signal of Yk Tigre It is stored in a single ROM0 (not shown).
(By leading the output signal of the O-gate 15 to the signal input terminal of eOROMol as well as the No. 1 input terminal, the RL and bit length corresponding to each of the two signal systems are outputted from this ROM. You can obtain it as . All you have to do is temporarily hold the RL and bit length in two pieces. In this way, you can use only one ROM.''That's all.

Claims (2)

[Claims] (1) In the MHH code decoding circuit that decodes the modified Huffman code, which is equipped with a ROM, there is a shift register that inputs encoded bits, and an R register that uses the code pattern as an address and stores the run length and number of code bits indicated by the code.
OM, and a shift circuit that generates a shift clock equal to the number of code bits in the ROM to shift the code bits of the shift register, and when a run length is obtained from the ROM, the shift circuit shifts the shift register to the code bit of the shift register. An MHH code decoding method characterized by shifting only the corresponding bits. (2) The MHH according to claim (1), characterized in that, in creating the address of the ROM, a converting means for converting the first 4 bits of the MH code into 1 bit is provided.
Code deciphering method.