JP2614927B2 - Image decoding processing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing method for decoding a run-length coded image signal such as a facsimile image into an image, and more particularly to a parallel operation in image decoding processing. Things.

(Prior Art) With regard to compression of digital images in facsimile, a conventional MN coding method (one of G3 facsimile for telephone networks) has been used.
Standardization (dimensional standard coding system) has been made and is widely used. In communication via a telephone line, a speed corresponding to the line speed or the printing speed after decoding may be realized. Even if encoding / decoding processing is conventionally performed by a program of a general-purpose microcomputer, it is practically sufficient.

(Problems to be Solved by the Invention) However, it is difficult to keep up with the improvement of the compression density, the speed of the transmission, and the increase in the size of the communication paper, and the encoding / decoding processing has to be left to the additional hardware. There were no shortcomings.
In addition, in order to realize image compression / expansion, it is necessary to configure a bit-based cyst unit or the like exclusively for specific compression / expansion, and it is inevitable that additional hardware will be an individual component, thus miniaturizing the device. However, there was a drawback that hindered economic realization.

On the other hand, there is a use for directly processing a compressed image of facsimile communication on a personal computer or the like. If the image can be compressed / expanded by the same encoding / decoding processing as that of the facsimile, the storage area for storing the image is economical and the input / output speed is high. Is possible. However, in order to achieve this with the processor of the personal computer itself and coexist with other programs, the burden on the processor is too large, and special additional hardware is also required. Was.

By the way, general-purpose computers such as personal computers use 16 or 32
It sequentially processes data of short word length such as bits.
When handling images, high-speed processing in units of 1 bit is necessary. A method of pipeline processing in which the flow of data in units of bits is input to a plurality of processing units and the operation result is received, and a bit processing processor is arranged in multiple ways. There is a method based on parallel processing in which the results of processing are output simultaneously. The former method has a problem that the processing is dedicated and it is difficult to coexist with the architecture of a general-purpose computer.

(Object of the Invention) The present invention realizes a processing method capable of efficiently decoding a compressed image by utilizing the architecture of a parallel processing computer that can efficiently realize the latter method and is compatible with sequential processing. It is intended for.

(Means for Solving the Problems) To achieve the above object, the present invention provides a processing method for decoding a run-length encoded image signal into an image,
Means having at least as many decoding arithmetic units as the number of types of run-length code bit strings, and holding on each arithmetic unit bit strings of different run-length codes, their effective bit lengths, and run-length lengths represented by the bit strings. Means for simultaneously copying an input bit string equal to or more than the maximum value of the effective length to all decoding arithmetic units, operating the decoding arithmetic unit group in parallel, and executing a run-length code bit string and an input bit string to be decoded. The main feature of the present invention is to determine the run length length represented by the input bit sequence and the start of the subsequent input bit sequence from the output of the decoding arithmetic unit group.

(Operation) According to the present invention, when a compressed image of facsimile communication is directly image-processed by a personal computer or the like by the above means, the image can be compressed / decompressed by the same encoding / decoding processing as that of the facsimile, and the image is stored. The economy of the area and the speed of input / output can be improved.

(Embodiment) FIG. 1 is an explanatory diagram showing the correspondence between coded data / decoded data of the MH coding method which is widely applied as an image compression method and is the basis of various compression methods. In decoding, the input bit string is collated with the MH code to determine a white or black length length (hereinafter referred to as a run length), and the number of pixels corresponding to the run length is arranged in a bit string and output. The MH codes are distinguished from each other by the MH effective bit length.

FIG. 2 is a configuration diagram of an M-bit memory for explaining the method of the present invention. 2 in FIG. 2 is a memory having a word length of M bits. 20, 21, and 22 are collation table data, each having a meaning in the N word direction (vertical direction) in FIG.
An MH code group table, 21 is used as an MH effective length table, and 22 is used as a run length table, and corresponds to the contents in FIG.

24 is an input MH code, 23 is an MH code group table 20 and input.
This is the result of the collation operation with the MH code 24. On the other hand, 25 is a white run table and 26 is a black run table, which are arranged in the M-bit direction (horizontal direction) in FIG. Similarly, reference numeral 27 denotes image data after decoding, which is folded and stored in the word length M. All of the tables 20 to 27 and data are stored in the same M-bit memory 2.

In the following description, the word length direction of the M-bit memory 2 is horizontal,
The description proceeds with the address direction defined as vertical.

Prior to the processing, the bit patterns of the MH code, MH code effective length, and run length shown in FIG. 1 are rotated in the vertical direction, that is, by 90 degrees with respect to the normal data holding method, as described above. They are stored in advance as indicated by 20, 21, and 22.

The MH code input at the start of the process is copied vertically and M times as shown in the input MH code 24 in FIG. The method of performing the resynchronization with the input will be described later.

With the MH encoding method, run-length codes up to the A3 size of paper can be represented by about 200 types of bit patterns.
If word lengths (M bits in FIG. 2) of the number or more of the types are prepared, they can be stored in a set of tables occupying addresses corresponding to the effective length of the MH coding.

Therefore, first, the tables 20 and 21 are arranged in another space of a memory having the same size (N words in FIG. 2). Table 2
At 0 and 21, a part of both tables is shown for simplicity of description, and corresponds to the contents of the table corresponding to the run lengths 0, 1, 2,... The symbols [1,
[0] is the content of the MH code table, and the symbol [x] may be undefined (0 or 1).

Further, in the MH code effective length table 21, the portion described as [1] indicates valid, and the portion described as [0] indicates invalid. A data group of such a collation table and a group of arithmetic units for performing independent vertical operations for each element of the word length M are prepared. The run length is extracted by performing a parallel operation. T shown in the input MH code 24 represents the head of the next input MH code and can be obtained in the collation processing in run length extraction.

To determine the run length, the M-bit memory 2 in which the table and data are arranged as described above, M pieces of N or more bit strings to be decoded are copied, and M types of matching tables having a maximum effective length of N bits are used. The collation operation is performed at a stretch with the contents 20, 21 of.

As a result, as shown in FIG. 23, only one run length code (white run length = 8 in this example) matches the input bit string. The run length value of the input code is obtained from the content 22 of the run length table at the matched bit position. Similarly, the start address (shown by T in FIG. 2) of the next input code required for the subsequent run length extraction processing is obtained from the contents 21 of the MH code effective length table at the matching bit position.

On the other hand, to assemble the decoded data, the operation units are used as a single long word length processor having the same word length M, and M
A method of writing white and black run length data in the image data folded bit by bit is used. 3, FIG. 3, and FIG. 4 are explanatory diagrams showing specific processing procedures, and all show the contents of the M-bit memory 2. FIG. In the figure, 31, 41, 43, and 45 indicate the contents of the image data 27 being written, 32 and 42 indicate the contents of the white run table 25, and 44 indicates the contents of the black run table 26.

The processing here is to calculate the addresses of the black and white run tables 25 and 26 from the run length, perform a logical operation on the contents and the write destination, and assemble the image data as the processing result.

If the current state in which the immediately preceding run length has been written is the beginning of each M bit of the image data 27 divided into word length M bits, the run length table indicated by [1] of the collation operation result 23 The contents of the address of the white / black run table 25 or 26 directly calculated from the contents of 22 are converted into image data 27
Just write to FIG. 3 shows this state, and the contents 32 of the white or black run table are overwritten on the image data 31 before processing. Here, the run length table 22 indicated by [1] of the collation operation result 32 is a white run and the length = 8
Therefore, the contents of the address 8 of the white run table shown in FIG.

On the other hand, in the normal case where it is not the head of each M bit, the sum of the black and white run lengths assembled from the left end of the word length M bits to the present is calculated in the course of processing, and the collation which is to be written to this is obtained. Run length of calculation result 23 (here =
The value obtained by adding 8) points to the address of the white or black run table, performs a logical operation on the contents and the image data to be written, and updates the image data.

FIG. 4 shows this state. In writing a white run, the assembly proceeds up to B bits alternately in black and white.
Finally, the fourth black run has been written up to B bits.
The result 43 of the exclusive OR of the image data 41 shown in the figure and the white run length 42 to be written now becomes the processing result image data.

Here, the white run length 42 is the content of the address = B + 8 + 1 of the white run table 25 in FIG. The next C (= B + 8 +
2) In writing black run data from bits, the address of the black run table 26 (here, C + 7 +
Refers to 1), its contents 44 and image data 43 of interest
The image data may be updated with the result 45 of the AND of the image data.

The image restoration is realized by alternately repeating the above-described run length extraction processing and decoding image assembling processing.

In a general-purpose processor, the processing based on bit operation becomes extremely redundant and high-speed processing is difficult. According to the MH run-length decoding method shown in FIGS. 2 to 4, the present invention constitutes a logical operation processor having a long word length,
Bit operation is executed at high speed by using the arithmetic unit without waste.

The requirements for the processor architecture also do not require extremely special arithmetic capabilities, except that they are simply long words, and the configuration may be simple.Run length extraction from MH codes, The assembling of decoded data from the run length is a processing module in which the properties of the operations are different from each other. Both require a bit-wise flexible and high-speed operation, but by providing a single processor architecture of word length, two types of long word lengths will be described in detail in the following example of a computer architecture. It can be easily realized by calculation.

FIG. 5 is a block diagram of one embodiment of a parallel processor for realizing the method of the present invention. 5 is a parallel processor, 51 is an operation unit, 52 is a program sequencer, 53 is an operation memory, 54 is a buffer memory, and 55 is a microcontroller. Program memory. 510 of the operation unit 51 is an operation unit group, 511 is an operation register, 512 is a musk register, and 513 is a carry register.

The operation unit 51 is composed of M independent processor elements (hereinafter referred to as PEs). Each of the registers 510, 511,
It has 512,513 components. The word length of the arithmetic unit 51 and the arithmetic memory 53 is M bits (M = 256 in this embodiment), which is much larger than 16 bits in an ordinary computer, and the arithmetic unit 51 and the arithmetic memory 53 have the same M-bit bus. And can read and write M-bit data by one access. Similarly, the number of PEs, each register 51
The number of components of 1,512,513, that is, the word length is also M bits.

For speeding up, the operation register 511 prepares a plurality of words and has a function of a cache memory in a normal computer. The word length of the buffer memory 54 is 16 bits. The reason is that the memory plays a role as a data memory of the program sequencer 52 having a word length of 16 bits. This is because it is also suitable for data input / output.

In the general-purpose computer, the program sequencer 52 of this embodiment is used.
In the same way as with, operations with word lengths of 16 bits or 32 bits are performed.
An M-bit operation is performed by controlling a program contained in the program 55 by the program sequencer 52. Specifically, the data stored in the operation register 511 and the operation memory 53
In the operation between the data and the data, the overflow of each one-bit operation is added to the contents of the carry register 513 to carry and carry, so that an ordinary M-bit calculator for arithmetic and logical operations is realized. Are equivalent.

On the other hand, in this architecture, three registers 511, 512,
Since 513 is provided, the following processing effective for bit processing can be performed. According to the bit pattern held by the mask register 512, whether or not the operation between the two data is possible is controlled in bit units. FIG. 6 is an explanatory view of the mask calculation showing this state. When the data 61 in the calculation register 511 and the data 62 in the calculation memory 53 are calculated, the data 63 of the mask register 512 is 1, that is, The operation is performed only in the hatched portion in FIG. 6, and the output data 64 is written to the operation register 511. In the part where the data 63 is 0, the original data 61 is held as it is.

In this example, a logical product between data having a word length of M bits is calculated. In other words, a vertical inter-bit parallel processing for M pieces of bit data is realized. The architecture is SIMD (Single Instruct
This is one of computer configuration methods known as an ion stream multiple data stream type.

By providing a processor having the SIMD-type parallel processing architecture described above, it becomes possible to decode a programmable and high-speed compressed image according to the method of the present invention on the processor. Hereinafter, a specific procedure for realizing the MH run-length decoding method shown in FIGS. 2 to 4 in the present embodiment will be described.

FIG. 7 shows a procedure for copying M input MH codes on the operation memory 53 in the decoding process of the present embodiment. The MH encoded data group input from the buffer memory 54 is shown in FIG.
The process of expanding 711 and 712 into the operation memory 53 as 721 and 722 is shown.

In FIG. 7, reference numeral 72 denotes data in which all M bits are 0, and reference numeral 73 denotes data in which all M bits are 1.
Prepare above. The symbols [0 to Z] in FIG. 7 represent 0 or 1 bit.

Prior to the start of the processing, the data 72 and the data 73 are separately loaded in the arithmetic register 511 in advance, and the MH code group for one image to be processed is prepared from the network or the storage device of each unit in preparation for the data to be processed. To buffer memory 54 71
Load like 1,712.

The contents of the processing are as follows. The bit components [0, 1, 2,..., Z,.
The process of copying each M pieces to 3 is repeated. To perform M copies, each bit component must be 0 or 1
Therefore, data 72 and data 73 are 721 or 72, respectively.
The process of copying to the predetermined address 2 may be repeated 16 times.

The condition that this copying is necessary is when the position of the address pointer indicated by P in FIG. 7, that is, when the MH code is specified in the processing described later, and the judgment is detected by the following procedure based on the break of the input MH code. is there. On the arithmetic memory 53, the seventh
As shown by R in the figure, this input MH code is used and referenced as a recursive lookup table from the beginning to the end of a series of 32 words composed of data 721, 722, and the MH code to be installed is specified.

In the process of specifying the MH code, since up to the maximum value (here, N bits) of the effective length of the MH code is observed backward from the break P of the code measured immediately before, N bits or more of the unprocessed data are processed after the break. If no data remains, load the next 16 bits. The loading destination is 722 when P is in the data 721, or 721 when P is in the 722.

The determination of whether the bit component inside each 16 bits of the buffer memory 54 is 1 or 0 can be determined by a well-known method, that is, a general-purpose bit extraction process using a shift or a mask. The reason is that the buffer memory 54 is a local memory of the program sequencer 52, and the program sequencer 52 and the buffer memory 54 can be regarded as one 16-bit processor.

Next, the MH code identification processing is performed in the MH effective length table 21 shown in FIG.
Is placed in the mask register 512, and the exclusive OR between the MH code group table 20 and the input MH code 24 is calculated. Here the seventh
The method shown in FIG. 6 can be used as it is while changing the address pointer such as R in the figure to correspond to the M-bit word. In principle, the collation operation result 23 in which only one bit is set to 1 is obtained. can get.

Further, the address of the break P of the input code shown in FIG. 7 is calculated by applying the same procedure as the following run length determination procedure to the collation operation result 23 and the MH effective length table 21.

FIG. 8 shows the input MH in the decoding process of this embodiment.
This shows the code run length determination procedure, where 81 is a run length calculation result storage area on the operation memory 52, 811 is the run length obtained in the same area, and 812 is the run length copied on the buffer memory 54. It is.

In the first half of the process, the logical product between the run length table 22 and the comparison operation result 23 is calculated, and all data other than the run length 811 is set to 0 and written to the storage area 81. It is checked whether the value of the M-bit word is 0 or not for N words.
This is an operation to set a bit at the corresponding position above.

In the example of FIG. 8, run length = 8 is obtained on the buffer memory 54 as a numerical value. The operation of this logical product may be used as it is with the mask removed from the method of FIG. The calculation of the run length numericalization may be performed by performing the reverse of the processing shown in FIG. 7 while involving the processing of the buffer memory 54 and the program sequencer 52.

Since the MH run code is handled in hexadecimal, data is not always stored alternately in black and white. Therefore, for a run length of 64 or more, the matching of the input MH code is repeated until a value of 64 or less comes, and the value of the run length of 65 or more is added by adding the obtained value to the data of 812. obtain.

Therefore, in the subsequent image data assembly process,
What is necessary is just to perform the process of alternately writing white or black. In addition, END_OF_LINE (EOL) detection is indispensable for detecting the end of an image. Since EOL is also one MH code, one set of data is allocated to the MH code group table 20 and the like, and the run length
It can be easily detected by the value of the data extracted on 812.

The final process of assembling the image data shown in FIG. 4 can be realized as it is by combining the operations described so far. Here, a method for realizing a higher speed using the architecture of the present embodiment is described in ninth embodiment. This will be described with reference to the drawings.

First, a word 92 having M bits of all 0s and a word 92 having all 1s are prepared in the operation memory 53. As shown in FIGS. 93, 95, and 97, the written bit pointers B, C, and D are stored in a mask register. Hold on 512.

As shown in FIGS. 94, 96 and 98, the image data being written is held in the operation register 511. Here, the set of data 93 and 94 is in a state where image data has been written up to the pointer B, including 2 bits of white, 3 bits of black, 2 bits of white, 2 bits of black, 3 bits of white, and 3 bits of black immediately before. The white run length = 5 is written in this, and a set of data 95 and 96 is obtained. Further, black run length = 3 is written, and data 97, 9
Get eight. The data 96 is the data 93 in the method of FIG.
Is used as a mask, and data 91 is written to data 94. Similarly, data 98 is obtained by writing data 92 to data 96 using data 95 as a mask.

(Effects of the Invention) As described above, flexible, high-speed, and high-performance image decoding can be realized by the method of the present invention and a single parallel processor architecture for realizing the same. This architecture extends the calculation word length of a general-purpose computer and adds functions useful for bit operations such as a mask register, and basically has no significant difference from the structure of an ordinary microcomputer system.

Also, in the processing of the general-purpose computer, the same processing as the word operation is required even for one-bit operation, and the remaining bits in the word are wasted, and the same operation time is required. On the other hand, according to the usage with the present architecture, the speed is increased by M word length in the 1-bit operation, and the M / W speed is increased even in the calculation of N bits having the word length W or less of the general-purpose computer. Further, a table search process required for collation of the input MH code and a bit write process required for assembling the image data can be executed by using the same operation mechanism with almost no M bits in the word being idle.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the correspondence between coded data / decoded data in an encoding system, FIG. 2 is a configuration diagram of a memory having a word length of M bits for explaining the system of the present invention, FIG. 4th
FIG. 5 is an explanatory diagram of a processing procedure of image data, FIG.
FIG. 6 is an explanatory diagram of a mask operation, FIG. 7 is an explanatory diagram showing a procedure for copying M input MH codes in a decoding process onto an operation memory, and FIG. 8 is an input MH code in a decoding process.
FIG. 9 is an explanatory diagram showing a code run length determining procedure, and FIG. 9 is an explanatory diagram showing an image data assembling operation. 2 ... M-bit memory, 5 ... Parallel processor, 20 ...
MH code group table, 21 MH effective length table, 22 Run length table, 23 Matching operation result, 24 Input MH code, 25 White run table, 26 Black run table, 27
…… Image data, 51… Calculator, 52… Program sequencer, 53… Calculator memory, 54… Buffer memory, 55… Microprogram memory, 510… Calculator group, 511… Calculator register, 512 …… Mask register, 51
3 Carry register.

Claims (2)

(57) [Claims] In a processing method for decoding a run-length coded image signal into an image, at least the same number or more of decoding operation units as the number of bit strings of the run-length code are provided. Means for holding a bit string and its effective bit length and a run length represented by the bit string on each arithmetic unit, means for simultaneously copying an input bit string equal to or more than the maximum value of the effective length to all decoding arithmetic units, The decoding operation unit group is operated in parallel, and a code collation unit for an input bit string by an operation of a bit string of a run-length code and an input bit string to be decoded is provided, and a run length represented by the input bit string and a subsequent input bit string A decoding processing method for an image, wherein a head is determined from an output of the decoding arithmetic unit group. 2. An image memory for storing an image by folding the image to the same bit width as the decoding arithmetic unit group, and the same number of decoding arithmetic unit groups as the number of consecutive 0s increases by 1 bit in ascending or descending order of the address. A white run table memory having an address space, and a black run table memory in which the number of continuations of one bit increases by one bit in ascending or descending order of the address.
The decoding operation group is a single long-word-length operation unit, and the contents of each memory are logically operated to generate a decoded image on the image memory from a run-length length. 1) An image decoding processing method described in the above.