JP3255808B2 - Compression / expansion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compression / expansion apparatus for handling image data or its code data, and more particularly to compression of a document image or halftone image data required for a facsimile apparatus, expansion of image code data, image data. The present invention relates to a compression / decompression device that combines conversion (enlargement / reduction) of image code and conversion of image code data into another code.

[0002]

2. Description of the Related Art This type of compression / decompression device is required in facsimile devices, other image communication devices, image file systems, and the like.

FIG. 23 shows a configuration of a conventional compression / decompression device. This compression / decompression device uses MH, MR,
It is equipped with MMR and is suitable mainly for compression and decompression of document images.

[0004] In recent facsimile apparatuses, a halftone image by error diffusion processing or the like as well as a document image is compressed and transmitted. For the compression of a halftone image, MH, MR, M
It is known that arithmetic codes have higher compression performance than MR codes.

[0005]

As a compression / decompression device for a binary image such as a facsimile image, an MH, MR, MMR system which is already widely used is combined with an arithmetic coding which is also suitable for compressing a halftone image. A compression and decompression device is ideal. However, to achieve this, MH, M
The mere combination of the R / MMR compression / decompression device and the dedicated arithmetic encoder causes a problem that the circuit scale increases and the cost increases. In addition, since only one of the hardware is required at a time, there are many problems, and there is a problem that the cost performance is low.

The present invention has been made in view of the above problems, and realizes both MH / MR / MMR encoding and arithmetic encoding / decompression processing while minimizing an increase in circuit scale, and achieves a high-speed operation. It is an object of the present invention to provide a compression / expansion apparatus in an image processing apparatus capable of realizing processing of a scanner and a printer in real time.

[0007]

In order to achieve the above object, the present invention provides a dedicated processing circuit for performing MH, MR, MMR encoding or decoding, and an encoding or decoding of the dedicated processing circuit. And a microprogram control unit for executing a Markov model arithmetic coding process.

In order to improve the speed of the Markov model arithmetic coding process, the present invention provides a dedicated processing circuit for performing MH, MR, MMR coding or decoding, and a coding or decoding of the dedicated processing circuit. A microprogram control unit for executing decoding and executing a Markov model arithmetic coding process, wherein the microprogram control unit stores a first memory for storing a predetermined number of lines of image data; A second memory having a capacity of at least twice the word width + a predetermined number of bits or more, and inputting image data from the first memory in word units;
Means for generating a state separation signal for encoding processing by shifting the image data in the memory left and right in bit units, and outputting probability estimation data at the time of encoding according to the state separation signal. And means for outputting code data using the probability estimation data.

In order to further improve the speed of the arithmetic coding process, the present invention further comprises control means for inputting image data and executing a Markov model arithmetic coding process on the image data. The context generation process in the encoding process is executed by a dedicated hardware circuit, and the subsequent process of calculating and outputting encoded data is executed by a microprogram. The present invention is not limited to only such a configuration. As will be understood from the description of the claims and the description throughout the present specification, the present invention includes various aspects, and each aspect has a characteristic configuration.

[0010]

According to the image processing apparatus of the present invention, the operation as a compression apparatus for executing the encoding processing or the combined processing of the image conversion and the encoding, the decoding processing or the combined processing of the decoding and the image conversion is performed by the above configuration. Any of the operation as a decompression device to execute, and the operation as a code conversion device to execute a combination process of decoding and encoding or a combination of decoding, image conversion, and encoding is possible. M
The H, MR, and MMR coding and arithmetic coding and decoding functions enable efficient processing of various images ranging from a document image to a halftone image.

Further, in executing the arithmetic coding process, the context generation process, which requires a lot of time in software processing, is executed by a dedicated hardware circuit, so that a further improvement in speed can be obtained.

[0012]

【Example】

FIG. 1 is a block diagram showing a schematic configuration of an example of a compression / expansion apparatus according to the present invention. The compression / decompression device includes a compression device, a decompression device, an image conversion (enlargement / reduction) device, and a code conversion device.
This is an image processing device combining a DMA transfer device. First,
The main components of FIG. 1 will be described.

In FIG. 1, reference numeral 100 denotes an image bus control unit for realizing an interface function with the image bus unit. A RAM 200 is used as a line memory and a parameter register for internal processing. This RAM 200 is an MPU 6 (FIG. 2) of a processor block.
0). 300 is the internal data bus 4
(BE data bus) Internal bus DMA controller 400 for controlling DMA transfer to RAM 200 by 1700, 400
Is a system bus control unit for interfacing with the MPU.

Reference numeral 500 denotes a register bank used as various registers, and a RAM is actually used. Reference numerals 600 to 800 denote FIFO buffers for temporarily storing changed pixel address information of 16-bit width data.
00 is an arithmetic and logic operation unit used in connection with execution of internal processing, 1300 is an MH / MR / MMR decoder, 1400
Denotes an image conversion unit for performing image conversion (enlargement / reduction) in the main scanning direction of an image; 1500, an MH / MR / MMR encoder;
Reference numeral 600 denotes a microprogram control unit for controlling the operation of the apparatus.

Reference numeral 1700 denotes a DMA control bus, which comprises a DMA transfer request signal from each section and a DMA transfer permission signal line to each section. Internal data bus (BE data bus) 180
0 is a 16-bit bus mainly used for transferring image data. 1900 is also a 16-bit internal data bus (BC data bus), which is mainly used for transferring encoded data.

Although not shown in FIG. 1, there is a microprogram control bus between the microprogram control unit 1600 and each unit in the apparatus.

Configuration of MH / MR / MMR Encoder FIG. 2 is a block diagram of the MH / MR / MMR encoder 1500. In FIG. 2, the changing pixel address control unit 150
2 receives the changed pixel address of the reference line from the FIFO buffer 900 and the changed pixel address of the coded line from the FIFO buffer 1100, and inputs them to the coding mode determination unit 1504.

The coding mode determination unit 1504 determines the coding mode (pass, vertical, horizontal) from the input changed pixel address information. Code table search unit 150
6 performs code allocation by searching an internal code table based on the determination result of the coding mode.

The packing processing unit 1508 outputs the variable-length 16 bits / byte output from the code table search unit 1506.
Conversion (word packing) of the word to coded data is performed, and the internal data bus 1900 or 18
Output to 00. Reference numeral 1510 denotes a main sequencer for controlling the entire encoder 1500. A request for DMA transfer with the internal RAM 200 is sent to the main sequencer 1510
Issued by 1512 to 1518 are corresponding functional blocks 1502 to 1 under the control of the main sequencer 1510.
508 is a sub-sequencer for controlling 508. The microprogram control unit 1600 can control the encoding mode for the encoder 1500, the designation of one line width (the number of words of one line of image data), the activation, and the like via the microprogram control bus 1602. The state of the encoder 1500 can be obtained. The encoder 1500 is a dedicated unit that executes MH, MR, and MMR coding in line units.

Configuration of MH / MR / MMR Decoder FIG. 3 is a block diagram of the decoder 1300. In FIG. 3, a code shift unit 1302 shifts the code data taken in from an internal data bus (BC data bus) 1900 by the code length for which decoding has been completed, and always supplies undecoded code data to a code analysis unit 1304. Code analysis unit 1304
Searches the internal decoding ROM according to the code data, and sends the decoded code to the drawing unit 1308. The a0 address calculation unit 1306 calculates the reference pixel changing pixel address information input from the FIFO buffer 900 and the code analysis unit 130.
A0 address which is a reference change pixel address of the reference line from the decoded code input from I.T.
4) is calculated. The drawing unit uses the a0 address and color (white /
Black) The image data is generated from the information, and the generated image data is output to the internal data bus (BE data bus) 1800 in word (16 bit) units.

Reference numeral 1310 denotes a main sequencer for performing overall control of the decoder 1300, and reference numerals 1312 to 1318 denote corresponding functional blocks 1 under the control of the main sequencer 1310.
A sub-sequencer that controls 302 to 1318. D
The MA transfer request is issued from the main sequencer 1310. The microprogram control unit 1600 can control the decoding mode for the decoder 1300, the designation of the restoration width of one line, the activation, and the like via the microprogram control bus 1602, and acquire the state of the decoder 1300. it can.

The decoder 1300 performs MH, M in line units.
This is a dedicated unit for performing R and MMR decoding. This decoding processing operation is as described in the above-mentioned document 1.

FIG. 4 is a block diagram of the image conversion unit 1400. In FIG. 4, a register 1402 stores the FIFO buffer 1000
The register 1404 holds the changed pixel address and the color information (B / W) input from the internal data bus (B / W).
The enlargement / reduction ratio is set through an E data bus (1800). The multiplier 1406 obtains a changed pixel address after scaling by multiplying the changed pixel address by the scaling ratio, and provides the drawing unit 1408 with the changed pixel address.

The drawing unit 1408 generates image data after scaling based on the given changed pixel address and the color information given from the register 1402. This image data is output to the internal data bus (BE data bus) 1800 via the register 1410 in word units. Reference numeral 1412 denotes a register for counting one line width (the number of words) before conversion via the internal data bus 1800. 141
Reference numeral 6 denotes a sequencer that controls each unit in the image conversion unit 1400, and also issues a DMA transfer request.

The processing operation of the image conversion unit 1400 is as described in the above reference 1. Configuration of Arithmetic Logic Operation Unit, Register Bank, etc. FIG.
0 and its peripheral configuration are shown. In FIG.
02 and 1204 are a 40-bit ALU and a shifter.

As is apparent from FIG.
00, etc., are loaded into the ALU / shifter unit 1200 to perform necessary calculations, and the calculation results are stored in registers in the register bank 500 or functional units connected to the BE data bus via the bus I / F 1206, for example, The data can be written in the data RAM 200 or the like. The arithmetic function of the arithmetic and logic unit 1200 is a logical operation such as addition, subtraction, bit shift, and logical AND / OR. The control signals required for these processes are provided by the microprogram controller 16.
Output from 00.

FIG. 6 shows the configuration of one register 502 in the register bank 500 and the bus I / F 1206. Register 502 has three parts, bit 0
To bit 15 (lower word), bit 16 to bit 31
(Upper word) and bit 32 to bit 39 (extended byte). In this configuration, the lower word and the upper word can be independently read / written from / to the BE data bus 1800. Selectors 504 and 506 and bus I / F
The selector in 1206 is for that. The read / write signals 508, 510, 512 of each section of the register and the register selection signal 514 are output from the address control section of FIG.

The microprogram control unit 1600, the system bus control unit 400, and the image bus control unit 100 are the same as those described in Reference 1.

FIG. 7 illustrates the internal configuration of the internal bus DMA controller 300, the address registers defined on the register bank 500, the memory areas defined on the data RAM 200, and the correspondence between them. FIG.

The data RAM 200 is used by being divided into n memory areas (MEM # 0 to MEM # (n-1)). The internal bus DMA controller 300 has n address pointers (ADP0 to ADP) corresponding to each memory area.
P (n-1)), and the register bank 500 has n
Address registers (ADREG0 to ADREG (n
-1)). The n address registers are defined as lower words or upper words of the register 502 (FIG. 6), which are shown in the figure as a continuous collection of 16-bit registers.

The i-th address register ADREGi
Are divided into an address portion for storing a head address of a memory area, and a flag portion for storing flag information associated with the memory area, for example, whether or not there is valid data in a line memory. In the address portion, the head address of the i-th memory area MEM # i is written as an initial value by the microprogram control unit 1600 when the compression / decompression device is initialized. The address pointer for accessing MEM # i is ADPi. As the initial value of ADPi, the value of ADREGi is written through the BE data bus 1800. Each address pointer is configured as an up / down counter, and after setting an initial value, one word R
Each time / W, the memory address is incremented or decremented.

Overview of Arithmetic Code Before describing an embodiment of an arithmetic code by the compression / decompression device of the present invention, an outline of Markov model arithmetic coding will be described.
The arithmetic coding according to the present embodiment conforms to the method described in ITU-T Recommendation T.82.

FIG. 8 shows an arrangement of reference pixels for constructing a Markov model. The Y line is an encoding line, and the preceding line and the line before the preceding line are respectively (Y-
1) Line and (Y-2) line. On the Y line
? "Is an encoding symbol (pixel) to be encoded, and 10 pixels A to I are reference pixels.

By arranging these reference pixels in an appropriate order,
For example, arrange them in ABC order

[0035] And Since each pixel takes two values of Sn, there are a total of 210 types of Sn. In the following, Sn, n = 0,.
(2 10-1) is called a state identification signal or context.

In the Markov model arithmetic coding, arithmetic coding is performed for each context. The arithmetic code has a binary point corresponding to the occurrence probability of the coded symbol sequence as a code.

FIG. 9 is a conceptual diagram of a Markov model arithmetic encoder. The entire encoder is composed of a context generator, a context table, a probability estimator, and an arithmetic encoder, and shows their interrelationships. The context generation unit performs state separation based on the value of the reference pixel as described above, and outputs a context identification number Sn indicating the state.

The context table is composed of a RAM, in which a symbol (dominant symbol: MPS) value (MPS value) which is likely to be generated for each context and a state number of a probability estimator (or Qe table) described later are written. I have. The MPS value is used as a predicted value of the encoded symbol “?”. The probability estimator is a state machine including 113 states, and is configured by a ROM or a RAM. In each state (ST), an estimated value Qe (ST) of the probability of occurrence of an inferior symbol (hereinafter, LPS), which is the reverse of the superior symbol, and a state transition destination after encoding are written. The arithmetic coder uses a coded symbol “?”, An MPS value, and Qe (ST) as input information and performs a process corresponding to a recursive division of a number line according to a prediction result based on the MPS value of the coded symbol “?”. And outputs the sign. The code is generated by a bit shift operation, and is successively concatenated to the previous code bit sequence. Here, this

[0039]

## EQU00002 ## Ci = Ci-1 + f {MPS predicted value, Qe (ST)} = Ci-1 + f {* Sn, * [* Sn]}. Here, + indicates the connection processing, and * X indicates the contents of the memory indicated by X. f represents arithmetic coding processing, and is a combination of addition, subtraction, bit shift, and logical operation. Decoding can be performed in the same manner as the inverse operation of encoding.

First Embodiment of Markov Model Arithmetic Encoder FIG. 10 shows a method of using the data RAM 200 at the time of arithmetic encoding processing in the compression / decompression apparatus of the present invention. The memory area is divided into a line memory area, a context table, a probability estimation table, and a code data buffer.

As shown in the above document 1, MEM # 0,
MEM # 1 is used as an input line memory and a pre-conversion line memory, respectively. The image data after the main scan conversion is sequentially stored in MEM # 1 to MEM # 4. MEM # 4
Is a coding line, MEM # 1 to MEM # 3 are reference lines, and a reference pixel is selected from this region.

Each context in the context table is represented by one word. For example, the context S is 2
As in 04, the lower 12 bits describe the address of the Qe table, and the upper 1 bit describes the MPS value in the context. This area is all in the initial state of encoding.
0 ”is written. In the probability estimation table, one state is set to 3
The configuration is described in words. As shown at 206, the first word is an estimated value Qe of the probability of occurrence of LPS, and the second and third words are coded symbols MPS and L, respectively.
This is the address indicating the next transition destination when encoded as PS. SW is a flag indicating whether or not to change the next MPS value when the encoded symbol is encoded as LPS. Such information is specified in ITU-T Recommendation T.82.

The code data buffer is an area for temporarily storing code data before outputting the code to the outside. FIG. 11 shows a memory area at the time of decoding. MEM # 0
.About.MEM # 2. MEM # 3 is M
The converted line of the restored line of EM # 2 (the converted line) is stored. MEM # 4 stores a line to be output to the outside. The method of generating the converted line and the output line can be realized in the same manner as the embodiment described in Reference 1. Other areas are common to those at the time of encoding.

Next, the arithmetic coding process will be described. FIG.
Indicates a context generation process. R1, R2, and R3 are registers defined in the register bank 500. The image data of the coding line is stored in R3,
MEM # 4 data is loaded. The reference line is
The (Y-1) line is loaded into R2, and the (Y-2) line is loaded into R1. In the figure, IMG (Y, i) represents the image data of the i-th word of the Y line.

Load IMG (Y, i) into the lower word of R3 and align the coded symbol with bit 15. Reference line data IMG (Y-1, i), IMG
When (Y-2, i) is loaded into the upper word of R2 and R1, the arrangement of the reference pixels A to J is as shown in FIG.
reference).

FIG. 13 shows the flow of the arithmetic coding process for one line. In processing 2001, R1, R2, and R3 are cleared. In process 2002, the image data IMG (Y, 0) is
IMG (Y-1, 0) and IMG (Y-
1, 1) as the upper and lower words of R2, and IMG (Y-
2, 0) and IMG (Y-2, 1) are loaded into the upper and lower words of R1. The above process is an initialization process of arithmetic coding of each line. When these two processes are executed,
The first word of the encoding line is in the lower word of R3, the first word of the previous line is in the upper word of R2, the first word of the line before the last is in the upper word of R1, and the other bits are "0". become.

Processes 2003 to 2010 are encoding processes of one-word image data. The process 2003 is a context generation process, which will be described later in detail. Processing 200
In step 4, it is checked whether the encoded symbol "?" Matches the predicted value MPS (S). At this time, the context is S. If the predictions match, the encoded symbol is encoded as MPS in operation 2005; otherwise, the LPS is encoded in operation 2006
Is encoded as

In processing 2007 to processing 2009, register R
1 to R3 are shifted left by one bit. By doing so,
As can be seen from FIG. 12, the encoded symbol and the reference pixel are updated.

In process 2010, it is determined whether encoding of 16 symbols has been completed. This subtracts the counter whose initial value is 16, and checks that it becomes zero. 1
Steps 2003 to 2010 are repeated until encoding of six symbols is completed.

When the encoding of the 16 symbols is completed, the data is shifted by 16 bits in steps 2007 to 2009, so that all the data of the lower words of the registers R1 to R3 move to the upper word. Processing 2011 to processing 201
At 3, the next image data is loaded into the lower words of R1 to R3. R1L represents the lower word of register R1. In process 2014, the end of the encoding process for one line is determined.
If not completed, the processes 2003 to 2013 are repeated.

FIG. 14 is a flowchart showing details of the processing 2003 (FIG. 13). In this figure, the context identification signal is generated in the register R0. R0 is
These registers are provided in the register bank 500 like R1 to R3. Process 2020 shifts register R1 right by 17 bits. As a result, R0 is 2 in FIG.
As shown in FIG. The process 2021 shifts R2 to the right by 13 bits and writes it to the upper word of R0. R0H represents the upper word of R0. as a result,
R0 becomes 2111 in FIG. The process 2022 is executed in R0
Is shifted right by 5 bits, and R0 becomes 2112 in FIG. The process 2023 writes the upper word of R3 to the upper word of R0. As a result, R0 is 2113 in FIG.
become. In step 2024, R0 is shifted to the left by 22 bits, and the reference pixel J is adjusted to the position of bit 39. Processing 2
025, R0 is shifted right by 30 bits and the reference pixel A
To the position of bit 0. At this time, the shifter 120
If it is configured so that "0" is entered from the upper 4 bits,
As a result of the process 2025, R0 becomes 2115 in FIG.
A context is created in the lower word. Process 2026
Then, this data is written to the address pointer ADP (n-3), and the context table can be accessed by the MPS encoding and the LPS encoding.

Assuming that this context is S, an address offset by S from the head address of the context table shown in FIG.
In step -3), by reading the address, the MPS (S) necessary for the encoding process and the address 204 of the Qe table are obtained. Next, by putting the address of this Qe table into the address pointer ADP (n-2) and reading out the address, as shown at 206 in FIG.
e value (Qe (ST)) and Q after encoding of one symbol
The state transition destination of the e table (here, the address of the Qe table) is obtained for each of the MPS and LPS.

FIG. 16 shows the MPS of the processing 2005 in FIG.
It is an encoding processing flow. As shown in Literatures 3 and 4, two registers, an A register and a C register, are used to execute arithmetic coding. In this compression / decompression device, A,
The C register is defined inside the register bank 500.

In process 2120, the A register value and Qe (S
T). In processing 2121, the value and A
X'8000 '(X which is 1/2 of the initial value of the register)
Is displayed in hexadecimal), and if it is larger than X'8000 ', the encoding is terminated. A register value is X'8000 '
If it is smaller, the value of the A register and Qe
(ST) is compared. In step 2123, addition to the C register and replacement of the A register value by Qe (ST) are performed.

In step 2124, the Qe of the context S
The table address 204 is replaced with the “next Qe table address (MPS)” in the area 206. Process 2125
Then, the A and C registers are shifted to the left until the A register value becomes larger than X'8000 '. In this process, the bit sequence output from the C register becomes an arithmetic code. This coded data is written to the memory area MEM # (n-1) of the data RAM every time 16 bits are stored, and output from this area to the outside of the compression / decompression device through the system bus control unit 400.

FIG. 17 shows the LPS of the processing 2006 in FIG.
It is an encoding processing flow. In step 2126, the A register value is subtracted from Qe (ST). In processing 2127, A
The register value is compared with Qe (ST). Process 212
8, the addition to the C register and the Qe (S
T). In process 2129,
The Qe table address 204 of the context S is set to the area 2
06 with the “next Qe table address (LPS)”. Step 2130 is the same as step 2125.

Next, a one-line arithmetic decoding process will be described. The decoding process generates a context using already decoded pixels A to J in the pixel arrangement shown in FIG.
The symbol "?" Is decoded for each context.
Also in the decoding process, the context generation unit, the context table, and the probability estimation unit in FIG. 9 are common to the encoding process. The procedure of symbol restoration is the reverse of encoding, but the necessary operations are addition, subtraction, and bit shift as in the encoding.

FIG. 16 shows how to use the registers R1 to R3 at the time of decoding. R1 and R2 are the same as the encoding. R
The symbol "?" Is decoded at the position of bit 15 of the lower word of No. 3. When the context is S, the restored symbol is MP
If S is determined, Has a context table MP
S (S) is written. Conversely, if it is determined to be LPS,
A symbol in which MPS (S) is inverted is written. When the decoding of one symbol is completed, the registers R1 to R3 are shifted left by one bit, the reference pixel arrangement is updated, and the next symbol is decoded in the context defined there. When this is repeated 16 times, restored image data is generated in the upper word of R3.

FIG. 19 is a flowchart of a one-line arithmetic decoding process. The process 3001 clears the registers R1 to R3. In a process 3002, the upper image data IMG of the reference line is added to the upper and lower words of R1 and R2, respectively.
(Y-2, 0), IMG (Y-2, 1) and IMG (Y-
1,0) and IMG (Y-1,1) are loaded. These image data are stored in the data RAM 200 (FIG. 11) as already decoded data. The above processing is the decryption initialization processing. Also, a predetermined number of bytes of encoded data to be decoded are written to the memory area MEM # (n-1) of the data RAM from outside the compression / decompression device through the system bus control unit 400 (FIG. 1). I have.

The process 3003 is a context generation process, which is the same as the content described in FIG. Process 300
In step 4, one symbol is decoded. Decoding symbol "
“0” or “1” is written in the position of bit 15 of R3.
R1, R2, and R3 are shifted one bit to the left by 5 to 3007. Until the decoding of 16 symbols is completed by the process 3008, the processes 3003 to 3008 are repeated. When the decoding of 16 symbols is completed, R1, R
Since the lower word of 2 is empty, processing 3009 and processing 301
With 0, new reference image data is input there.
Since the decoded image data can be used as the upper word of R3, it is stored in the memory area MEM # 2 of the data RAM (FIG. 1).
1 202). This is repeated until one line of image data is restored. The process 3012 is a determination for that.

FIG. 20 is a schematic flow of the one symbol decoding process, and corresponds to the process 3004 in FIG. Process 3020 includes: reading a context table;
Write the context data S to the address pointer. The process 3021 stores the Qe table address 204 (FIG. 11) in the address pointer ADP (n-2) to read the probability estimation table corresponding to the context.
Write to

The process 3022 is performed in the following manner: MPS (S), Qe value,
A decoding operation is performed using the A and C registers. MPS,
Although details of the LPS determination are omitted, the LPS determination can be executed as an inverse operation of the encoding by addition, subtraction, and bit shift.

As a result, it is determined whether the symbol to be decoded is MPS or LPS. When it is determined that the MPS is the MPS, the value of the MPS (S) written in the context table 204 is set as a restored symbol as shown in a process 3023. If it is determined to be LPS, the inverted value of MPS (S) (! MPS
Let (S)) be a restored symbol. MPS (S) is "0"
Or "1", these processes can be realized by writing X'0000 'or X'FFFF' in the lower word of R3.

Code conversion between MH, MR, MMR code and arithmetic code One line of arithmetically encoded data is restored (Y line, FIG. 11).
202), it is converted to an MH, MR, MMR encoder 150
Encoding with 0 can be easily realized. M
As the reference line for R and MMR, the (Y-1) line which is the preceding line is used. Reference 1 states that MH,
An example of code conversion between MR and MMR codes is shown in detail. Similarly, by repeating arithmetic decoding and MH, MR, and MMR encoding line by line,
Arithmetic encoded data for one page can be converted to another code.

The arithmetic encoding and arithmetic decoding processes of the present embodiment are microprogram processes, so that the processing speed is slower than that of a method of realization using dedicated hardware. However, MH,
If the MR / MMR encoder 1500 or the MH / MR / MMR decoder 1300 is fast, even if the arithmetic coding and arithmetic decoding processes are slow, the above-mentioned code conversion function enables real-time processing to a high-speed input / output device. Can be realized.

Second Embodiment of Markov Model Arithmetic Encoder In the above-described first embodiment, a circuit for Markov model arithmetic encoding is shared with a circuit for another purpose. The increase can be suppressed. On the other hand,
There is a problem that the processing speed is slow because everything is a program process. FIGS. 21 and 22 show configuration examples in which only a dedicated circuit for constructing a Markov model is provided to improve processing efficiency.

FIG. 21 is a block diagram showing a second embodiment of the compression / decompression device. The state separation processing unit 2000 is a dedicated circuit for generating a context. Other blocks are the same as the corresponding blocks in Reference 1. The algorithm of arithmetic coding is based on the ALU / shifter unit 1200.
Is executed by the microprogram control unit 1600.

FIG. 22 is a block diagram of the state separation processing unit 2000. Explaining in comparison with FIG. 12, the shift registers 2001 to 2003 correspond to R1 in FIG. 12, and the shift register 2001 corresponds to the lower word of R1. Similarly, the shift registers 2004 to 2006
2, the shift registers 2007 to 2009 correspond to R3. The context register 2010 is a 16-bit register. The lower 10 bits are fixed to reference pixels A to J, and the upper 6 bits are fixed to “0”. Reference pixels A to J
Are connected to corresponding bit positions of the context register 2010, respectively. For example, the reference pixel A is the second upper bit (bit position 3) of the shift register 2002.
0) to the least significant bit of the context register.

At the time of encoding, the encoding process is executed with reference to the encoded symbol 2011 and the context identification signal 2012 in the most significant bit of the shift register 2007.
Updating the context is performed by shifting all shift registers one bit to the left. 14 can be executed in one cycle. A necessary control signal such as a shift signal is output from the instruction decoder 2013.

At the time of decoding, a decoded symbol is written in the shift register 2007. At this time, the decoded symbol is "
0 ", X'0000 'and the decoded symbol is"
If the value is 1 ", X'FFFF 'is stored in the shift register 2007.
Write to. The restored image data is stored in the shift register 200.
8 is obtained. By writing it to a predetermined address of the data RAM 200, one line of image data is obtained. The configuration itself in FIG. 22 is not characteristic.

The present invention is not limited to the embodiment described above. According to the present invention, an arithmetic coding process can be implemented in a compression / decompression device that performs MH, MR, and MMR coding while suppressing an increase in circuits.

[0072]

As is apparent from the above description, the image processing apparatus according to the present invention includes a dedicated processing circuit for executing MH, MR, and MMR encoding or decoding, and an encoding or decoding of the dedicated processing circuit. By providing a microprogram control unit that executes decoding and performs a Markov model arithmetic encoding process, the circuit scale is reduced,
The MH, MR, MMR encoder and the arithmetic encoder (microprogram control unit) can be integrated. Further, in executing the arithmetic coding process, the context generation process, which requires a lot of time in software processing, is executed by a dedicated hardware circuit, so that a further improvement in speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a compression / decompression device of the present invention.

FIG. 2 is a block diagram of an MH, MR, and MMR encoder;

FIG. 3 is a block diagram of an MH, MR, and MMR decoder;

FIG. 4 is a block diagram of an image converter.

FIG. 5 is a block diagram around an ALU.

FIG. 6 is a configuration diagram of a register.

FIG. 7 is a block diagram showing the relationship among an internal bus DMA control unit, a data RAM, and a register bank;

FIG. 8 is a layout diagram of reference pixels.

FIG. 9 is a schematic diagram of a Markov model arithmetic encoder.

FIG. 10 is a configuration diagram of a memory area in a data RAM at the time of arithmetic coding;

FIG. 11 is a configuration diagram of a memory area in a data RAM at the time of arithmetic decoding.

FIG. 12 is a layout diagram of image data in a register.

FIG. 13 is a flowchart of a one-line arithmetic coding process;

FIG. 14 is a flowchart of context generation processing.

FIG. 15 is a diagram showing register contents during context generation processing;

FIG. 16 is a flowchart of MPS encoding.

FIG. 17 is a flowchart of LPS encoding.

FIG. 18 is a layout diagram of image data in a register.

FIG. 19 is a flowchart of a one-line arithmetic decoding process.

FIG. 20 is a symbol decoding flowchart.

FIG. 21 is a block diagram showing a second embodiment.

FIG. 22 is a block diagram of a state separation processing unit.

FIG. 23 is a block diagram showing a conventional image processing apparatus.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Image bus control unit 200 RAM 300 DMA control unit 400 System bus control unit 1300 MH / MR / MMR decoder 1400 Image conversion unit 1500 MH / MR / MMR encoder 1600 Microprogram control unit

Claims (1)

(57) [Claims] 1. A dedicated processing circuit for performing MH, MR, MMR encoding or decoding, and a Markov model arithmetic
A microprogram control unit for executing an encoding process , wherein the microprogram control unit and the dedicated processing circuit
, MH, MR, MMR
A micro-program controller for storing a predetermined number of lines of image data, at least twice the word width of said first memory + a predetermined number A second memory having a capacity of more than bits and inputting image data from the first memory in word units, and shifting the image data in the second memory to the left and right in bit units, Means for generating a state separation signal for encoding processing, means for outputting probability estimation data at the time of encoding according to the state separation signal, and means for outputting code data using the probability estimation data. A compression / expansion device characterized by having at least.