JP3286898B2 - Encoding device, decoding device, image encoding device, and image decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to encoding and decoding of image information and the like.

[0002]

2. Description of the Related Art For encoding a Markov information source, a symbol sequence is mapped (mapped) between 0.0 and 1.0 on a number line, and its coordinates are represented, for example, in binary, as a code word. A number line display coding method (arithmetic coding method) is known. FIG. 1 is a conceptual diagram.
Symbol "1" output from binary memory for simplicity
, The occurrence probability of “0” is represented by r, the occurrence probability of “0” is represented by 1−r, and the range for the symbol “1” is arranged at a lower position. Assuming that the output sequence length of the memoryless information source is 3, the coordinates of each of C (000) to C (111) at the right end are displayed in binary, and the coordinates are truncated to a distinguishable digit to obtain each codeword. The decoding can be performed on the side through the same process as the transmitting side. In such a sequence, A _i of the mapping range on the number line of the symbol sequence at the i-th time point, and the minimum coordinate C _i of the range is determined by the symbol a _i that appears.
0 ”

[0003]

(Equation 1)

[0004]

(Equation 2)

When the appearing symbol a _i is “1”

[0006]

(Equation 3)

[0007]

(Equation 4)

[0008] By the way, An overview
of the basic princes o
f the Q-coder-Adaptive b
inaryarithmatic corder (IB
M Journal of Research & D
development Vol. 32 No. 6 No
v. 1988), in order to reduce the number of calculations such as multiplications with a large calculation load, rA _i-1 is not calculated, but a plurality of fixed values are prepared as a set in a table. By adopting a method of selecting a value corresponding to, encoding and decoding can be realized with finite accuracy. Therefore, if the mapping is sequentially repeated, the range (area) A _i-1 becomes gradually smaller, so that it is necessary to perform a normalization process (for example, multiply A _i-1 by a power of 2) in order to maintain the calculation accuracy. In an actual code word, the fixed value is always the same, and is processed by performing a shift of a power of two, that is, a binary number at the time of calculation. Where r
When A _i-1 is approximated to S, the above-described equations are respectively as follows. When _ai is "0"

[0009]

(Equation 5)

[0010]

(Equation 6)

When a _i is "1"

[0012]

(Equation 7)

[0013]

(Equation 8)

## EQU1 ## Here, originally, the range (area) A _i-1 up to the previous symbol gradually decreases as the mapping is repeated, so that it is necessary to reduce S accordingly. The reduction of S is specifically realized by making the shift operation a power of two. However, when S is reduced, the higher bits only increase by 0 which is not directly related to the operation. Therefore, Ai _-1 is multiplied by a power of 2, and Ai _-1 is reduced to the minimum value (initial value of the initial value). It can be considered that a constant value of S is used by keeping the value at 1/2. This is called normalization processing. Hereinafter, the case where the symbol a _i is “0” is referred to as MPS (dominant symbol: a symbol having a higher appearance probability), and the case of “1” is referred to as LPS (inferior symbol: a symbol having a lower appearance probability). In other words, it is assumed that the prediction conversion process has been performed in advance, and the MPS is assumed to have a high appearance probability and is assumed to be low. Also, the symbols a _i described above
Range when is "1"

[0015]

(Equation 9)

Is the range (area) of the inferior symbol. FIG. 2 is a block diagram showing a conventional encoding device.
In the figure, 1 is a register for temporarily storing the value of a range (region) allocated to the previous symbol, 2 is a subtractor, 3 is a range (region) switch, 4 is a coordinate switch, and 5 is a normalization process. Is a shifter for determining the shift amount of the data, and 6 is a calculation unit for calculating an encoded output. Next, the operation will be described with reference to the drawings. S selected from a table having a plurality of values from the state of the Markov information source by a prediction estimating unit (not shown)
When (inferior symbol range (area)) is input, subtracter 2
Calculates the difference (A _i−1 −S) from the range (area) A _i−1 of the previous symbol stored in the register 1 and outputs the difference. The range (region) (A _i-1 -S) to be assigned to the superior symbol and the range (region) S to be assigned to the inferior symbol are input to the switch 3 and are switched depending on whether the symbol is the superior symbol or the inferior symbol. That is, if the symbol is a dominant symbol, the range (area) to be assigned to the symbol

[0017]

(Equation 10)

[0018] If the symbol is a less-probable symbol, the range (area) to be assigned to the symbol

[0019]

[Equation 11]

Is output. Further, the switching unit 4 assigns either the inferior symbol range (region) S or the fixed value 0, which is input according to the superior symbol or the inferior symbol, to the preceding symbol, the minimum coordinate C _{i− of} the range (region) A _{i−1. It} is output as the difference coordinate ΔC for ₁ . That is, if the symbol is a dominant symbol arranged at a higher position, the difference coordinates

[0021]

(Equation 12)

And outputs the difference coordinates if the symbols are inferiorly arranged at lower levels.

[0023]

(Equation 13)

Is output. The output A _i of the switch 3 is fed to the register 1 and the shifter 5. Symbol a range assigned for _i (region) A _i is stored in the register 1 a following range of symbols (region) calculated data. The shifter 5 reduces the input range (area) A _i by 1 /
Compared to 2, if smaller than 1/2, range (area) A
After doubling _i , comparing it with 再度 again, the range (area) A
Repeat the doubling until _i exceeds 1/2. Then, the number of expansions 1 until the range (area) A _i exceeds １ ／ is obtained, and is output to the register 1 and the arithmetic unit 6 as the coordinate shift amount l. The operation unit 6 receives the outputs of the switch 4 and the shifter 5 as inputs, performs an operation on the codeword, and outputs the result. The arithmetic unit 6 accumulates and stores difference coordinates from the past. That is, the accumulated value is the minimum coordinate C _{i-1 of} the range (area) assigned to the previous symbol.
be equivalent to. The input difference coordinate ΔC is the minimum coordinate C of the previous symbol.
It is added to _i-1 to obtain a minimum coordinate C _i of allocation range of the current symbol (region). The minimum coordinate C _{i is set} to the shift amount l
(Bit), and check whether there is a portion that matches the maximum coordinate within the effective range. If there is a matching part, the part is output as a fixed coordinate bit, that is, a code word.

Next, a general arithmetic coding device and a general arithmetic decoding device will be described in detail. Arithmetic decoding encoder (Encoder) / decoder (Decode)
r) is the ITU-T international standard recommendation T. 82 can be realized by the table and the processing flow. Hereinafter, this arithmetic coding is referred to as a QM-coder, the coding device is referred to as a QM encoding unit 7, and the decoding device is referred to as a QM decoding unit 8. The schematic configuration of the coding device and the decoding device is shown in FIG. As shown in FIG. In FIG. 3, 9 is an image memory for storing an input image, and 10 is a pixel value MPS having a high probability of appearing.
1-bit MPS table that stores (More Probable Symbolo dominant symbol) as a predicted value.
State number (0 to 11) classified into state 3 (State)
2) 7-bit ST table for storing 2), 12 is LP
An LSZ table in which the S area width is represented by 16 bits.
NMPS table indicating PS transition destination by 7 bits, 14
Is an NLPS table representing the LPS transition destination with 7 bits, 1
Reference numeral 5 denotes a SWTCH table representing 1-bit prediction value inversion determination, 16 denotes a pixel symbol converter that inputs a prediction value from the MPS table 10 and a pixel Pix from the image memory 9 and outputs a symbol, and 17 and 18 denote a pixel symbol converter. An update processor 19 for updating the values of the MPS table 10 and the ST table 11 is an encoder.

The LSZ table 12, NMPS
The table 13, the NLPS table 14, and the SWTCH table 15 are used as probability estimation tables. Next, the operation of the encoding device will be described with reference to FIG. In FIG. 3, there are two inputs to the QM encoding unit 7, a first input is a context, and a second input is a pixel to be encoded. The output is a sign. Image memory 9
Represents a pixel (Pixe) that stores an image and is to be encoded.
l) to the model template (Model Tem).
plate / encoded / decoded 1 in the neighborhood specified by
A context (10 bits; total number 1024), which is a reference pattern of 0 pixels, is generated. In addition, the encoding target pixel is output at the same time as the encoding. In the QM-coder, a standard model template of two lines and three lines shown in FIG. 5 for generating a context is prepared. In the QM-coder, the prediction coincidence probability of the pixel value is estimated for each context with respect to the encoding target pixel, and the encoding is advanced while learning according to the fluctuation. The learning is performed by rewriting two variable tables (MPS table 10 and ST table 11) each having a context as an index. In addition to the variable table, there is a constant table (probability estimation table) that refers to a state number (state) as an index during encoding.
Table 1 shows the set values. An LSZ table 12 representing the LPS area width by 16 bits, an NMPS table 13 representing the MPS transition destination by 7 bits, an NLPS table 14 representing the LPS transition destination by 7 bits, and a SWTCH table 15 representing the prediction value inversion determination by 1 bit. . (The alphabetic variable / constant table names shown here are array names used in the processing flow described later.) The LPS area width of the LSZ table 12 is referred to by an arithmetic unit in the arithmetic encoder 19 and is used for adaptive prediction. It is not directly related to learning. The arithmetic operation is performed inside the arithmetic encoder 19 using the LSZ. When the arithmetic precision is reduced, a normalization process (renormalization. Renormalization) is performed.
size). When this normalization process is performed, learning is performed at the same time. If the coded symbol at the time of the normalization processing is MPS, the NMPS value of the MPS state transition destination table 13 is written into the ST table 11 if it is an LPS, and if it is LPS, the state is changed. You. At the time of encoding, the pixel symbol converter 16 converts the symbol 14 into an arithmetic coder 19 and update processors 17 and 18.
Output to

When the normalization processing is based on LPS, if the predicted coincidence probability is １ ／, the MPS value is inverted (operation “1-MPS”) and the MPS table 10
Write to. Whether the coincidence probability is 1/2 can be determined by using the SWTCH value in the SWTCH table 15 of the predicted value inversion determination table SWTCH12 as a flag. As described above, the two variable tables ST11 and the MPS table 10 need to be updated and managed individually. In FIG. 3, each update processor 17 of the tables ST11 and MPS10,
18 determines an update value and updates the table value to perform the update process. FIG. 6 shows QM-
It is a state transition diagram of Coder (only a part was shown because the number of states is as many as 113). Each frame indicates one state, and the number inside the state indicates the state number (hexadecimal notation is shown in parentheses). The arrow with “MPS” is a state transition by MPS (when normalization processing is involved), and the arrow with “LPS” is a state transition by LPS. The state transition destination by the MPS and LPS depends on the values of the NMPS table 13 and the NLPS table 14. The underlined LPS state transition is SWT
The value of the CH table 15 is 1, accompanied by inversion of the predicted value. The example of a state transition is shown. At the start of the encoding process, "state = 0, predicted value = 0" is initialized for all contexts. Here, the state transition will be described assuming that only one context CX is taken. In the encoding process, the state number for the context CX is ST (C
X), the predicted value can be referenced from the variable table by MPS (CX). When the inferior symbol LPS appears as the first symbol, the state ST (CX) changes from 0 to 1. The transition destination by the actual LPS is

[0028]

[Equation 14]

The value of the ST table 11 is

[0030]

(Equation 15)

Is updated to At this time,

[0032]

(Equation 16)

If ("LPS" (underlined) in the figure), the predicted value is updated at the same time. That is, the MPS table 10
The MPS (CX) of 0 changes from 0 to 1 (inverted value). If the second symbol is also the inferior symbol LPS, the transition destination is

[0034]

[Equation 17]

In this case,

[0036]

(Equation 18)

Therefore, updating of the predicted value is unnecessary. Third
If the symbol is the dominant symbol MPS, the state is changed only when the normalization processing is performed. For the sake of explanation, assuming that there is a transition, the transition destination is

[0038]

[Equation 19]

## EQU1 ## The state transition described here is indicated by “***” in the figure. Note that the above-described state transition is the same in decoding. Before describing the encoding process flow, FIG. 7 shows the bit arrangement of the encoding register 20 and the area width register 22 provided in the encoder 19. In the encoding register 20, bit 15 and bit
A decimal point is set between 16 and "x" (16 bits) is L
An operation unit (Cx22) for the SZ table 12,
If there is a carry, it propagates to a higher level. "S" (3 bits) is a spacer bit portion (Cs23), "b" (8 bits) is a byte output portion (Cb24), and "c" (1 bit) is a carry determination portion (Cc25). In the course of the encoding, the register value of the encoding register 20 is updated so as to be the lower limit value of the area corresponding to the encoded symbol. The area width register A21 is an encoding register 20
Corresponding to the decimal point of "x"
a "(16 bits) is arranged as a decimal part, and the integer part (bit 16) becomes" 1 "only in the initial state value. The region width (region size) is A-LSZ (lower region width) or Bit updated to LSZ (upper area width) and indicating a weight of 1/2 except for the initial value (integer part = "1")
15 is normalized to be “1”, and by keeping it at １ ／ or more, any LSZ as the upper region width is set to LS.
Even if a selection is made from the Z table 12, the securing of the lower area is guaranteed. In the normalization processing, the area width register 21 and the encoding register 20 are simultaneously enlarged. In the QM-coder, the LSZ table 12 has a fixed size for the state.
Is normally assigned to LPS, but when the lower region is smaller than the upper region, M
"Conditional MPS / LPS exchange" assigned to PS is performed. A normalization process is performed when the LPS is coded and when the “conditional MPS / LPS exchange” is applied and the MPS is coded. An encoding process flow will be described based on the bit arrangement of this register. The term “layer” in the processing flow refers to “(resolution) layer” in the case of hierarchical coding, and “stripes” refers to “strips” obtained by dividing an image in units of N lines (only the last stripe is N lines or less). Here, the description will be made on the assumption that the number of layers is 1, but this does not prevent extension to coding of a plurality of layers. In order to explain the encoding processing flow, the following auxiliary variables CT26, BUFFER27, SC28, and TEMP29 in addition to the variables, tables, and registers described in FIGS.
Use The CT 26 is an auxiliary variable for counting the number of shifts of the encoding register 20 and the area width register 21 by the normalization processing, and outputting the next code byte when the value becomes 0. The BUFFER 27 is an auxiliary variable that stores the code byte value output from the encoding register 20. SC28 is an auxiliary variable used only for encoding and counting the number of consecutive bytes when the code byte value output from the encoding register 20 is 0xff. TEMP
An auxiliary variable 29 is used only for encoding, detects a carry to the BUFFER 27, and sets the lower 8 bits as a new BUFFER value 27 after carry processing. The BUFFER 27 set from the encoding register 20 via the TEMP 29 does not become 0xff without performing the carry process.
7 lower, ie BUFFER27 and SC 0x
Since ff is changed if it is carried higher than the encoding register 21, it cannot be determined as a code even if it is output from the encoding register 20.

FIG. 8 is a flow chart E showing the overall flow of the encoding process.
It is an NCODER processing flow. Recommendation T. 82, the TP (Typical Predictive) in this processing flow.
on) and DP (Deterministic Pr)
The processing relating to (ediction) is not directly related to the present invention and the conventional example, and will not be described. First, S101
Then, INITENC is called to initialize the encoding process. In S102, one set of the pixel PIX and the context CX is read one by one, and in S103, the encoder (ENCODE) is read.
Encoding is performed according to E). In S104, S102 and S103 until the stripe (or image) ends.
Is repeated, and at the end, FLUSH is called in S105 to perform post-processing of the encoding process.

FIG. 9 shows a pixel value to be encoded (PIX) and M
9 is an ENCODE processing flow for switching a process to be called based on a match / mismatch of an output value (predicted value) from the PS table 10. In step S111, it is determined whether or not the pixel value matches the predicted value. If the pixel value matches the predicted value, the MPS is encoded. In S113, CODEMPS is called and M
PS, and S112 calls CODELPS to LP
Encode S.

FIG. 10 shows a case where the encoding target pixel value (PIX) and the output value (predicted value) from the MPS table 10 do not match, that is, C which is called when encoding the LPS.
It is an ODELPS processing flow. First, in S121, the value of the area width register 21 is temporarily updated to the lower area width. In S122, if the determination in S122 for comparing the MPS area with the LPS area is Yes, the conditional MPS
/ LPS exchange is applied, the region width register 21 is left as it is to encode the lower region, and the coding register 20
A does not update. If the determination in S122 is No, the upper region is encoded, and the encoding register 20 which is the region lower bound value in S123, and the region width register 21 which is the region width in S124.
To update. SWTCH table 15 in the determination of S125
If the constant SWTCH value is 1, the predicted value (M
Invert / update the PS table 16). In the LPS encoding, a state transition is performed by referring to the NLPS table 14 in S127, and a normalization process is performed by calling RENORME in S128.

FIG. 11 shows the CO called when the pixel value to be coded (PIX) matches the output value (predicted value) from the MPS table 10, that is, when the MPS is coded.
It is a demps processing flow. First, in S131, the value of the area width register 21 is temporarily updated to the lower area width. If the determination in S132 is No, the CODEMP is left as it is.
The S processing ends. If the determination in S132 is Yes, the state transition by referring to the NMPS table 13 is always performed in S136, and the normalization process is performed by calling RENORME in S137. Before S136 and S137, S133
Is determined, the region width register 21 is left as it is to encode the lower region, and the encoding register 20 is not updated. If the determination in S133 is No, conditional M
A PS / LPS exchange is applied, encoding the upper region,
At 134, the encoding register 20 is updated, and at S135, the area width register 21 is updated.

FIG. 12 shows a RENORM for performing a normalization process.
It is an E processing flow. In S141, the area width register 2
1. In S142, an operation equivalent to double multiplication is performed by shifting the encoding register 20 one bit higher. In S143, 1 is subtracted from the variable CT26. In S144, it is determined whether the variable CT26 is 0 or not.
At 145, the BYTEOUT process is called to output a one-byte code from the encoding register 20. In the determination in S146, the end of the normalization processing is determined. If the area width register 21 is less than 0x8000, the processing in S141 to S145 is performed.
Is repeated, and if it becomes 0x8000 or more, the area becomes 以上 or more, and the process ends.

FIG. 13 is a BYTEOUT processing flow for outputting a code from the encoding register 20 one byte at a time. The output byte is the byte output part (Cb24) of the encoding register 20. The carry determination unit (Cc25) for determining carry is also processed at the same time. In S151, a total of 9 bits of the value (Cb24) of the encoding register 20 and the value (Cc25) of the encoding register are set to the variable TEMP29.
Set to. If there is a carry in S152,

[0046]

(Equation 20)

If there is no carry, 0xF in S159
If it is F, the byte output is processed separately for the case where it is less than 0xFF. If the determination in S152 is Yes, the code that has already been output from the encoding register 20 is the value obtained by adding the carry 1 to the value of BUFFER27 in S153, S1
The sum SC + 1 of the SC byte values 0 (the accumulated 0xFF has become 0x00 due to carry propagation) at 54
The byte determines the carry as the propagated code value.
The variable SC28 is set to 0 in S155, and the variable BU is set in S156.
The lower 8 bits of the variable TEMP are set in FFER27. In step S157, (Cc25) and (Cb24) of the encoding register 20 processed as the variable TEMP29 are cleared, and in step S158, 8 is set in the variable CT26 to process 8 bits until the next output. If the determination in S159 is Yes, the sign cannot be determined, and 1 is added to the variable value SC28 to accumulate 0xFF. If the determination in S159 is No, the code already output from the encoding register 20 is replaced by S
At 153, a BUFFER value is determined, and at S154, a total SC + 1 byte of SC byte values 0xFF is determined as a code value. In S163, the variable SC28 is set to 0, and in S164, the variable BUF29 is set to the variable TEMP29 (8 bits as it is because there is no carry).

FIG. 14 shows an ST table 1 at the start of encoding.
1. INITENC processing flow for setting the MPS table 10 and initial values of each variable. When the concept of layer and stripe is not introduced, the “first stripe of this layer” in S171 means “at the time of starting image coding”. For an image composed of a plurality of stripes, the variable table is initialized for each stripe. Processing can be continued without performing. In S171, the first pixel of this layer
Determine whether to stripe or force reset the table. If the determination in S171 is Yes, S172
Initializes the ST table 11 and the MPS table 10 which are variable tables for all contexts CX2. S173 is SC28, S174 is the value of the area width register 21, S175 is the encoding register 20, S17 is
6 initializes a variable CT26. The initial value of the variable CT26 is the number of bits of (Cb24) of the encoding register 20 and (Cb24).
s23) is the sum of the number of bits, and the first code output is performed when 11 bits are processed. If the determination in S171 is No, the variable table is not initialized in S177, and the table value at the end of the stripe immediately before the same layer is reset.

FIG. 15 shows an F which performs post-processing including a process of sweeping out the value remaining in the encoding register 20 at the end of encoding.
It is a LUSH processing flow. CLEARBI in S181
The TS is called to minimize the number of significant digits of the code remaining in the encoding register 20. S182 is FINAL WRITE
S is called to finally output the variables BUFFER 27 and SC 28 and the sign of the encoding register 20. S18
In step 3, the first byte of the code is removed because the variable BUFFER 27 is output (as an integer part) prior to the output of the value of the encoding register 20. In S184, since the code is a decimal coordinate in the final effective area, the byte 0x00 that is continuous at the end can be removed if necessary.

FIG. 16 is a CLEARBITS processing flow for performing processing for minimizing the number of significant digits of a code at the end of encoding. Thus, the code has a value in which 0x00 continues as far as possible at the end. S191 is a variable TEMP
29 is set to a value obtained by clearing the lower two bytes (Cx22) of the upper bound of the last valid area of the encoding register 20. In S192, the magnitude of the cleared value of the lower 2 bytes of the upper bound value is compared with the value of the encoding register 20. S1
If the determination in 92 is Yes, the variable value TEMP is set in S193.
29 is returned to the value of the encoding register 20 by returning the over-cleared value. If the determination in S192 is No, the variable value TEMP
29 is the value of the encoding register 20.

FIG. 17 shows a FINA in which the code determined at the end of encoding is written up to the value remaining in the encoding register 20.
It is an LWRITES processing flow. In step S201, the C register is shifted by the number of bits indicated by the variable value CT26 to enable code output and carry determination. At S202, the presence or absence of a carry is determined. If the determination in S202 is Yes, there is a carry, and if No, there is no carry. BY
As in the TEOUT processing flow, S203 and S204 output a code value with a carry, and S207 and S208 output a code value without a carry.
The code of the C + 1 byte is determined. In S205, the (Cb24) value (1 byte) of the encoding register is output, and in S206, the lower 1 byte is output, and the code output is completed.

Next, a decoding apparatus and a decoding processing method of the apparatus will be described. In FIG. 4, 9 is an image memory for storing an output image, and 10 is a pixel value MPS (More Probable Symbololo) having a high probability of appearing.
1-bit MPS table for storing a dominant symbol) as a predicted value; 11 for each 7-bit for storing a state number (0 to 112) in which the degree of the prediction match probability of the predicted value is classified into a state 113 of the statistics 113 ST table,
12 is an LSZ table indicating the LPS area width by 16 bits, 13 is an NMPS table indicating the MPS transition destination by 7 bits, and 14 is an NLPS indicating the LPS transition destination by 7 bits.
Table 15 is a SW that indicates the predicted value inversion determination by 1 bit
The TCH table 16 is a pixel symbol converter that inputs the predicted value from the MPS table 10 and the pixel PIX from the image memory 9 and outputs a symbol, and 17 and 18 are the values of the MPS table 10 and the ST table 11, respectively. An update processor 30 for updating is a decoder.

Note that the LSZ table 1
2, NMPS table 13, NLPS table 14, S
The WTCH table 15 is used as a probability estimation table. Next, the operation of the decoding device will be described with reference to FIG. In FIG. 4, there are two inputs to the QM decoding unit 8, a first input is a context, and a second input is a code. The output is the decoded pixel. The image memory 9
The image is accumulated, and the neighboring encoded / decoded 10 pixels specified in the model template for the pixel to be decoded are stored.
The context (10 bits, which is the reference pattern of the pixel).
1024) is generated. In addition, the QM-Coder is provided with two-line and three-line standard model templates common to encoding / decoding shown in FIG. 5 for generating a context. In the QM-coder, similarly to the encoding, the prediction coincidence probability of the pixel value is estimated for each context with respect to the decoding target pixel, and the decoding is advanced while learning according to the fluctuation. The learning is performed by rewriting two variable tables (MPS table 10 and ST table 11) each having a context as an index. In addition to the variable table, there is a constant table (probability estimation table) that refers to a state number (state) as an index when decoding. Table 1 shows the set values.

[0054]

[Table 1]

An LSZ table 12 representing the LPS area width by 16 bits, an NMPS table 13 representing the MPS transition destination by 7 bits, an NLPS table 14 representing the LPS transition destination by 7 bits, and a SWTC representing the prediction value inversion judgment by 1 bit
H table 15. (The alphabetic variable / constant table name shown here is the array name used in the processing flow described later.) The LPS area width of the LSZ table 12 is the arithmetic decoder 30
And is not directly related to adaptive prediction learning. The arithmetic operation is performed inside the arithmetic decoder 30 using the LSZ. When the arithmetic precision is reduced, a normalization process (Renormalize) is performed.
When this normalization process is performed, learning is performed at the same time. If the decoded symbol at the time of occurrence of the normalization processing is MPS, the NMPS value of the MPS state transition destination table 13 is set to L
If it is PS, the LPS state transition table 14 writes the NLPS value in the ST table 11 and the state is changed. When decoding, the decoder 30 converts the symbol into the symbol pixel converter 1
6. Output to the update processors 17 and 18. Also, when the normalization processing is based on LPS, if the predicted matching probability is １ ／, the MPS value is inverted (operation “1-MPS”).
Then, the data is written in the MPS table 10. Match probability is 1 /
2 is determined by the predicted value inversion determination table SWTC.
The SWTCH value in the SWTCH table 15 of H12 can be determined as a flag. As described above, the two variable tables ST11 and the MPS table 10 need to be updated and managed individually. In FIG. 4, table ST11 and MPS
The update processing is performed by each of the 10 update processors 17 and 18 determining the update value and rewriting the table value.

Next, FIG. 19 shows the bit arrangement of the decoding register 31 and the area width register 32 provided in the decoder before describing the decoding processing flow in the same manner as the description of the encoding processing. In the decoding register, the lower word CL
The OW 33 and the upper word CHIGH 35 can be realized as a 32-bit register, and a decimal point is set at the upper position of the MSB, bit 31, and “b” (8 bits) is the upper byte Cb 34, “” of the byte input unit (CLOW register 33).
x ″ (16 bits) is an operation unit Cx36 (CHIGR register 35) for the value of the LSZ table 12. In the decoding process, the C register value is calculated from the lower bound value of the area corresponding to the decoded symbol to the coordinates in the area. The area width register A32 is updated to be an offset value to the code 4. The area width register A32 corresponds to the decimal point of the decoding register 31, and is set to "a" (16 bits) in accordance with the "x" register section.
Are arranged as decimal parts, and the integer part (bit 16) becomes “1” only in the initial state value. The area width (also called area size) is A-LSZ (lower area width) or LSZ
(Upper area width), initial value (integer part = "1")
The bit 15 indicating the weight of 1/2 is normalized to be "1" except for the above, and by keeping it at 1/2 or more, the lower area is secured even if any LSZ is selected from the LSZ table 12 as the upper area width. Is guaranteed. In the normalization processing, the area width register 32 and the decoding register 31 are simultaneously enlarged.

In the QM-coder, the upper area LSZ provided from the LSZ table 12 having a fixed size with respect to the state is normally allocated to the LPS, but when the lower area is smaller than the upper area, the upper area LSZ is allocated to the MPS. Exchange ". When the LPS is decoded, and when the MPS is decoded by applying the “conditional MPS / LPS exchange”, a normalization process is performed. A decoding process flow will be described based on the bit arrangement of this register. The interpretation of the term “layer” in the processing flow is the same as that of the encoding, and the explanation is made assuming that the number of layers = 1, but this does not prevent extension to decoding of a plurality of layers. In order to explain the decryption processing flow, FIGS.
In addition to the variables, tables and registers described in Table 1, the following auxiliary variables CT26 and BUFFER27 are used. CT
Reference numeral 26 denotes an auxiliary variable BU which counts the number of shifts of the decoding register 31 and the area width register 32 by the normalization processing, and inputs the next code byte when the value becomes 0.
FFER 27 is an auxiliary variable that stores a code byte value input from the code to the Cb register 34 of the decoding register 31.

FIG. 18 is a diagram showing the entire flow of the decoding process.
It is an ECODER processing flow. Recommendation T. The processes related to TP and DP in the present process flow of 82 are not related to the present invention and the conventional example, and therefore will be omitted. First, S211
Then, INITDEC is called to initialize the decoding process. In S212, the set of contexts CX2 is read out one by one, and in S213, the pixel PIX is
Is decrypted. In S214, stripe (or image)
S212 and S213 are repeated until is completed.

FIG. 20 shows a DEC for decoding a pixel to be decoded.
It is an ODE processing flow. First, in S221, the value of the area width register 32 is temporarily updated to the lower area width. S2
If the determination at 22 is Yes, the lower area is decoded. S2
If the determination in Step 23 is Yes, MPS_EXC in S224
HANGE is called, and in S225, RENORMD is called to perform normalization processing. If the determination in S223 is No, the MPS is decoded without performing the normalization process, and the MPS
The predicted value in Table 10 is defined as a pixel value (PIX). If the determination in S222 is No, the upper area is decoded. In S227, LPS_EXCHANGE is called, and in S228, RENORMD is called to perform normalization processing. MPS_EXCHANGE, LPS_EXCH
In the path for calling the ANGE, the area to be decoded is determined, but if the size of the area is not compared, the decoding target is MP
S or LPS cannot be determined. Therefore, the pixel values to be decoded in the called processing flow are determined.

FIG. 21 shows LPS_E for decoding the upper region.
It is an XCHANGE processing flow. The determination in S231 is Y
If es, the MPS is decrypted. The decoding register 31 is updated in S232, and the area width register 32 is updated in S233. S
At 234, the prediction value from the MPS table 10 is used as it is as a pixel value (PIX). In S235, a state transition is performed by referring to the NMPS table 13. If the determination in S231 is No, the LPS is decoded. In S236, the decoding register 31 is updated, and in S237, the area width register 32 is updated.
In S238, the non-prediction value “1-prediction value” is set to the pixel value (PI
X). If the determination in S239 is Yes, S240
To invert / update the predicted value (MPS table) 10.
In S241, a state transition is performed by referring to the NLPS table 14.

FIG. 22 shows an MPS_E for decoding the lower region.
It is an XCHANGE processing flow. The determination in S251 is Y
If es, the LPS is decoded. In S252, the non-prediction value is set as a pixel value (PIX). If the determination in S253 is Yes, the inversion of the predicted value (MPS table) 10 is performed in S254.
Perform an update. In S255, a state transition is performed by referring to the NLPS table 14. If the determination in S251 is No, the LPS is decoded. In S256, the prediction value of the MPS table 10 is directly used as a pixel value (PIX). In S257, a state transition is performed by referring to the NMPS table 13.

FIG. 23 shows a RENORM for performing a normalization process.
It is a D process flow. In S261, it is determined whether or not the variable CT26 is 0. If the determination is Yes, BYTEIN is determined in S262.
And inputs a one-byte code to the decoding register 31. In S263, the area register 32 is shifted, and in S264, the decoding register 31 is shifted by one bit to perform an operation equivalent to double multiplication. In S265, 1 is subtracted from CT26. In the determination of S266, the end of the normalization process is determined, and if the area width register 22 is less than 0x8000, S261 to S265 are repeated. In S267, it is determined whether or not the variable CT26 is 0. If the determination is Yes, S is executed.
In 268, BYTEIN is called to input a one-byte code to the decoding register 31.

FIG. 24 is a BYTEIN processing flow for reading the code into the decoding register 31 byte by byte. SC
D (Stripe Coded Data) is a code for the stripe. If the determination is Yes in S271, there is no code to read in S272, so that the variable BUFFE
R27 is set to 0. In step S273, the variable BUFFER27 is read into the CLOW register 33 (Cb34).
Variable CT26 for processing 8 bits until the next input at 4
Is set to 8. If the determination is No in S271,
In step S275, the one-byte code is read into the variable BUFFER27.

FIG. 25 shows the ST table 1 at the start of decoding.
1. INITDEC processing flow for setting the initial values of the MPS table 10 and each variable. Regarding S281, S282, and S290 relating to the initial value setting of the table, S17 of the INITINC processing flow of the encoding processing is performed.
1, S172 and S177. Decryption register 3
The initial value of 1 is set in the Cx register 36 and the Cb register 3
4 is set by reading a code of 3 bytes. S28
3 to clear the decryption register 31, and S284: BYTE
IN is called and code 4 is read into the Cb register 37 by 1 byte. S285 is shifted by 8 bits, BYTEIN is called in S286, and the code is set to 1 in the Cb register 34.
Read bytes. In S287, the decoding register 31 is shifted by 8 bits, and in S288, BYTEIN is called to read the code into the Cb register 34 by 1 byte. Thus, a code of three bytes in total is set in the Cx register 36 and the Cb register 34. In S289, the initial value of the area width register 32 is set. In Table 1 and some processing flows, the prefix “0x” of “for example, 0x8000” indicates a hexadecimal number, and “0x8000” in the area width registers 22 and 32 determines whether or not the execution of the normalization processing is necessary. Value of the area width (1/2
Weight).

[0065]

In the encoding / decoding of the prior art, in the normalization processing performed to secure the arithmetic precision of arithmetic coding / decoding, every time the size of the area is doubled, Since the end determination is made and even if the determination is unnecessary, the determination is always made.
There is a problem that decoding cannot be performed at high speed. The present invention has been made in order to solve the above problems, and classifies normalization processing according to situations, and enables batch processing of expansion when the total number of bits of area expansion can be specified or limited. I do. In addition, the setting of the contents of the normalization processing by the minimum judgment is made independent, and when the enlargement processing can be performed collectively, the number of times of enlargement processing, the number of times of enlargement end judgment, the number of times of code byte input or output judgment, etc. are reduced. Aim.

[0066]

An encoding apparatus according to claim 1 performs a plurality of enlargement processes for a normalization process applied when an area (A _i ) for a current symbol is smaller than the set value. provided in advance, compared to the region (a _i) and setting value, when the area (a _i) is small, selects and executes normalization processing suitable for the circumstances from the enlargement process of the plurality of Things.

In the decoding apparatus according to the second aspect, a plurality of enlargement processes are provided in advance for a normalization process applied when the area (A _i ) for the current symbol is smaller than the set value, and If the area (A _i ) is smaller than (A _i ) and the set value, a normalization process suitable for the situation is selected from the plurality of enlargement processes and executed.

According to a third aspect of the present invention, in performing the normalization processing, a normalization processing is provided for expanding a region having a state-specific size in which the total number of bits of the region expansion is obvious in advance. It is.

In the decoding apparatus according to the fourth aspect, when performing the normalization processing, a normalization processing is provided for expanding a region having a state-specific size in which the total number of bits of the region expansion is obvious in advance. is there.

According to a fifth aspect of the present invention, in performing the normalization processing, the normalization processing is provided for enlarging an area excluding a state-specific size area from the current entire area.

In the decoding apparatus according to the sixth aspect, when performing the normalization processing, a normalization processing is provided for enlarging an area excluding a state-specific size area from the entire current area.

According to a seventh aspect of the present invention, when the normalizing process is performed, a normalizing process for enlarging a region of a dominant symbol is provided.

In the decoding apparatus according to the eighth aspect, when performing the normalization processing, a normalization processing for enlarging the area of the dominant symbol is provided.

According to a ninth aspect of the present invention, in performing the normalization processing, the normalization processing is provided for expanding the area in which the total number of bits of the area expansion can be limited by correcting the state-specific size. Things.

In the decoding apparatus according to the tenth aspect, when the normalization processing is performed, the normalization processing for expanding the area in which the total number of bits of the area expansion can be limited by correcting the state-specific size is provided. Things.

An image coding apparatus according to claim 11 is provided with the above coding apparatus in an electronic computer, a scanner, a facsimile, a printer, a semiconductor chip or the like.

According to a twelfth aspect of the present invention, there is provided an image decoding apparatus comprising the above decoding apparatus in an electronic computer, a scanner, a facsimile, a printer, a semiconductor chip, or the like.

[0078]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 26 is a configuration diagram of an image encoding processing device according to the present invention. The image decoding processing device according to the present invention also has the same configuration as the image coding processing device shown in FIG. The image encoding device 37 includes a display unit 38, a keyboard 39, a mouse 40, and a mouse pad 4.
1, system unit 42, compact disk device 4
3 is provided. For example, as shown in FIG. 26, the image encoding / decoding processing device of the present invention inputs and decodes an encoded image from a compact disk device 43, transfers the decoded image information to a system unit 42, 38. Alternatively, the image displayed on the display unit 38 is encoded and output to the compact disk device 43. Also,
It encodes image information and transmits the image information via a line (not shown). However, the image encoding / decoding processing device according to the present invention is not limited to the personal computer and the workstation shown in FIG. 26, and may be of any type. For example, instead of the compact disk device 43, a video player may be used as an input device, or image data from a network may be input. The input data may be analog data or digital data.

The image encoding / decoding processing device of the present invention may exist in a separate housing as shown in FIG. 26, but as shown in FIG. It may be housed in the housing of a peripheral device such as the facsimile device 46 or the like. In addition, the present invention may be a case where it exists as a part of a system board such as a television camera, a measuring machine, and a computer. Also,
Although not shown in FIG. 27, a case where the devices shown in FIG. 27 are connected via a local area network (LAN) and mutually encoded information is transmitted may be used. Further, the information may be transmitted and received using a wide area network such as an analog or digital public line (such as ISDN). In the present embodiment, the encoding unit in the image encoding processing device and the decoding unit in the image decoding processing device perform encoding / decoding described below. In arithmetic coding such as QM-coder, normalization is performed to ensure calculation accuracy. In the present embodiment, when performing normalization processing on the upper region (LSZ) or the lower region (A-LSZ), processing is performed not only by applying a single normalization processing flow, but even when the processing results are the same. It is characterized in that one of a plurality of processing flow candidates (stored in advance) having different processes is selected and applied, and a conventional processing flow may be one of the candidates. The arrangement of the upper and lower regions may be upside down.

RENOR already performed in the encoding process
Regarding the ME processing flow and the RENORMD processing flow performed in the decoding processing, the processing flow of always expanding one bit at a time has been described in the conventional example, but here, the conditions for performing the normalization processing are classified into two and dedicated processing is performed. Prepare a flow. (1) Normalization processing for expanding LSZ area (2) Normalization processing for expanding (A-LSZ) area The basis of the classification of the normalization processing is shown. The reason for classifying (1) is that if the LSZ value is determined, the number of bits to be shifted by the end of the normalization processing is uniquely determined, so it is not necessary to determine the end for each bit shift, and when byte input / output is required Can only be divided once, but basically it is possible to perform shift processing collectively. The basis for classifying (2) is L
Since the expansion of the non-SZ area (A-LSZ) has only one bit or two bits, the end determination is not required when the second expansion is performed. The reason that the number of shifts is limited is that the minimum value of the area width registers 21 and 32 is 0x800
0, since the maximum value of LSZ given in Table 1 is 0x5b12, the minimum value of (A-LSZ) is 0x24ee, which is always 0x8000 or more by a 2-bit shift (4 times). In classifying the normalization processing, a constant table LSZS37 indicating the number of enlargement shifts uniquely determined for the normalization processing of the LSZ area is introduced. State number S =
Regarding the state S indicated by 0 to 112,

[0081]

(Equation 21)

(“<<” indicates a left logical shift), and the minimum integer N is the expanded shift number LSZ of the area LSZ (S).
Set as S (S). Table 2 shows the table thus set.

[0083]

[Table 2]

[0102] The encoding and decoding processing flows in the present embodiment will be described. In the present embodiment, the processing flow ENCODER (FIG. 8) in the encoding processing, ENCODE
ER (FIG. 9), BYTEOUT (FIG. 13), INITE
NC (Fig. 14), FLUSH (Fig. 15), CLEARB
ITS (FIG. 16), FINALWRITES (FIG. 1)
7), processing flow DECODER in decryption (FIG. 1)
8), LPS_EXCHANGE (FIG. 21), MPS_
EXCHANGE (FIG. 22), BYTEIN (FIG. 2)
4), INITDEC (FIG. 25) is the same as the processing flow in the conventional example. In addition, the same processing elements as those already described in the processing flow with the same name have the same identifier.

FIG. 28 shows a CODELPS processing flow corresponding to FIG. 10 of the conventional example. If the determination is Yes in S122, the conditional MPS / LPS exchange is applied and the lower area (A
-LSZ), if the determination is No, the upper region LSZ is encoded. Normalization processing RNOR for exclusive use of LSZ area in S404
MELSZ, S408: The normalization process RNORME12 dedicated to 1 bit or 2 bits in the (A-LSZ) area in S408 is made independent, so that S125 to S1 of the conventional flow can be performed.
S401 to S403 also serve as the prediction value inversion determination (S125) and inversion processing (S126) performed in 27 and the state transition (S127) with reference to the NLPS table.
And S405 to S407.

FIG. 29 shows a CODEMPS processing flow corresponding to FIG. 11 of the conventional example. If the determination is Yes in S133, a conditional MPS / LPS exchange is applied and the upper area LS
If Z is No, the lower area (A-LSZ) is encoded. Normalization processing RNOR dedicated to LSZ area in S422
The state transitions performed in S136 of the conventional flow are applied as S421 and S423 by making the normalization processing RENORME12 dedicated to 1 bit or 2 bits in the (A-LSZ) area of MELSZ and S424 independent.

FIG. 30 shows a new RENORME12 processing flow, which is applied only to the (A-LSZ) area normalization processing. In S431, the area width register 21 is corrected to a lower area size. The number of shifts to be expanded in the updated (A-LSZ) region can be determined by the determination in S432, and the determination Ye
1 bit for s and 2 bits for No. When the number of shifts is 2 bits (No in S432), the area width register 21 is expanded by 2 bits in S433. S434
To determine whether or not there is a code byte output in the first shift of the encoding register 20, and if the determination is Yes, S435 and S4
In step 37, BYTEOUT is called in step S436. The variable CT is decremented by 1 in S438, but the same processing is not performed in S435.
This is because it is not necessary to determine whether to call the OUT processing. S
If the determination is No at 434, the encoding register 20 is determined at S439.
Are collectively enlarged by 2 bits, the variable CT is reduced by 2 in S440, and if the variable value CT is 0 in S441, the BYTEOUT process is called. If the shift number is 1 bit (S432 decision Ye
In the case of s), in S443, the area width register 21 and S444
Shifts the encoding register 20 by 1 bit, decrements the variable CT by 1, and executes BYTE in S441 and S442 described above.
Judge and execute the call of the OUT processing.

FIG. 31 shows a new RENORMELZZ processing flow, which is applied only to the normalization processing of the LSZ area. In step S451, the number of shifts to be expanded in the LSZ area is set in the new variable RNM from the LSZS table 37.
In step S452, the area width register 21 is collectively enlarged. S
At 453, comparing the two variable values RNM and CT,
The processing is divided into three types, such as small and the like. In the first case (>) where the variable value RNM is larger than the variable value CT (>), the coding register 20 is collectively expanded in CT bits in S454, the variable RNM is reduced by the variable CT in S455, and BYTEO is generated in S456.
Call the UT. If the variable value RNM is larger than the variable value CT, the batch enlargement from S454 to S456 is repeated. Even if the variable RNM becomes smaller than the variable CT, S45
If the variable value RNM is larger than 0 in the judgment of S8, S45
In step 9, the encoding register 20A is expanded collectively by the remaining RNM bits, and in step S460, the variable CT is reduced by the variable RNM. In step S453, the second variable value RNM is equal to the variable value CT.
In the case of (=), in S461, the encoding register 20A is set to C
The T bits are collectively enlarged, and BYTEOUT is called in S462. In the third case (<) where the variable value RNM is smaller than the variable value CT in S453, the CT bits are collectively enlarged in S463, and the variable CT is reduced by the variable RNM in S464. The reason why the subtraction processing of the variable CT is not performed in S454 and S461 is that it is not necessary to determine whether to call the BYTEOUT processing.

FIG. 32 is a DECODE processing flow corresponding to FIG. 20 of the conventional example. S225 calling the normalization processing RENORMD is set as S471 (A-LSZ)
Normalization processing RENOMD12, S2 dedicated to area enlargement
28 is changed to S472 as the normalization processing renormdlsz dedicated to enlargement of the LSZ area.

FIG. 33 shows a new RENORMD12 processing flow, which is applied only to the (A-LSZ) area normalization processing. The processing content is the encoding processing RENORM12.
Byte output processing BYTE described in the processing flow
This is basically the same except that OUT becomes the input processing BYTEIN.

FIG. 34 shows a new RENORMLSZZ processing flow, which is applied only to the LSZ area normalization processing. The processing content is the byte output processing BYTEO described in the RENORMELZZ processing flow of the encoding processing.
This is basically the same except that the UT becomes the input processing BYTEIN. In short, in the first embodiment, a plurality of normalization processing patterns for the normalization processing are provided at the time of the normalization processing, and the range corresponding to the range on the number line exceeds the predetermined range. The most appropriate enlargement processing pattern (normalization processing pattern) to be performed is determined from the above-described normalization processing pattern, and normalization is performed. Further, as the plurality of normalization processing patterns, (1) a process of normalization processing on an area having a state-specific size in which the total number of bits for area expansion is obvious in advance; and (2) a state-specific size area from the current entire area. , Processing steps such as normalization processing are provided for the region excluding.

Embodiment 2 In the present embodiment, encoding /
Decoded symbol and / or upper region (LSZ) /
When processing the lower region (A-LSZ), not only a single normalized processing flow is applied, but a plurality of processing flow candidates (stored in advance) having different processing steps even if the processing results are the same. It is characterized in that one of them is selected and applied, and the conventional processing flow may be one of the candidates. Further, the arrangement of the upper and lower regions may be upside down. Normalization processing by MPS encoding / decoding is further added to the two classifications of the normalization processing described in the first embodiment, and the classification is made into three classifications. (1) Normalization processing for expanding the LSZ area (by LPS encoding / decoding) (2) Normalization processing (LP for expanding the (A-LSZ) area
(By S encoding / decoding) (3) Normalization processing by MPS encoding / decoding Since (1) and (2) have already been described in the first embodiment, the classification of the normalization processing of (3) Only the grounds for are shown. The basis for classifying (3) is that normalization processing by MPS encoding / decoding always shifts 1 bit (enlarged twice) in any of the areas, so that it is not necessary to determine the end. M with conditional MPS / LPS exchange applied
Since a large area is always allocated to the PS, the minimum value of the area width register 21 value of 0x8000 or more is ensured, and is always 0x8000 or more by one bit shift (double). In the present embodiment, processing flows ENCODER (FIG. 28), ENCODE (FIG. 9), CODELPS (FIG. 10), and RENORM12 in the encoding process
(FIG. 30), RENORMELZZ (FIG. 31), BYT
EOUT (FIG. 13), INITENC (FIG. 14), FL
USH (FIG. 15), CLEARBITS (FIG. 16), F
INALWRITES (FIG. 17), processing flow DECODER in decoding processing (FIG. 18), RENORME1
2 (FIG. 33), RENORMELZZ (FIG. 34), BY
TEIN (FIG. 24) and INITDEC (FIG. 25) are the same as the processing flow in the first embodiment. In addition, the same processing elements as those already described in the processing flow with the same name have the same identifier.

FIG. 35 is a CODEMPS processing flow corresponding to FIG. 29 of the first embodiment. In the MPS coding, regardless of the presence or absence of the conditional MPS / LPS exchange, in S601, the normalization process RENORMEPMS is called and one bit is enlarged.

FIG. 36 is a flowchart of a new RENORMEMPS process, which is applied to normalization by MPS coding. The processing flow is basically the same as that of the conventional example shown in FIG. 12, but since the normalization processing is performed only for one bit, the step S146 for determining the end is unnecessary. Since the processing flow names are different, S141 to S145 are indicated by S611 to S615.

FIG. 37 is a DECODE processing flow and corresponds to FIG. 32 of the first embodiment. Call normalization processing S
471 is MPS_EXCHANGE, S472 is LPS
The processing flow is moved to the processing flow of _EXCHANGE, and a normalization processing flow to be applied by a decoded symbol is called in each of the moved processing flows.

FIG. 38 is an LPS_EXCHANGE processing flow corresponding to FIG. 21 of the conventional example. The normalization processing is called at the end of the processing in the path branched in the determination of S231. In the judgment Yes, after S235, in S621, the normalization processing RENORMDMPS dedicated to the MPS is performed. In the judgment No, S241 is performed.
Is followed by S622 in the LSZ area-specific normalization processing RENO
A call to RMDLSZ was added.

FIG. 39 is an MPS_EXCHANGE processing flow corresponding to FIG. 22 of the conventional example. The normalization process is called at the end of the process in the path branched in the determination of S251. In the judgment Yes, after S255, in S622 (A-LSZ)
The normalization process RENORMD12 dedicated to the area, and in the determination No, after S257, the normalization process R dedicated to the MPS is performed in S621 in S621.
A call to ENORMDMPS was added.

FIG. 40 is a flowchart of a new RENORM DMPS process, which is applied to normalization by MPS decoding. The normalization process flow in the decoding of FIG. 23 of the conventional example is basically the same as the normalization process flow in the encoding process of FIG. 12 in which the code byte output process BYTEOUT is changed to the input process BYTEIN. Since the processing is the normalization processing, the end determination (corresponding to S266) becomes unnecessary. That is, RENORMEMPS shown in FIG.
This is a processing flow in which the code byte output processing BYTEOUT of the processing flow is changed to the input processing BYTEIN.

Table 3 shows the introduction effect of the second embodiment using the evaluation image.

[0100]

[Table 3]

In the RENORMELZZ processing, the variable RN
Although the number of processes for referring to the LSZS table 37 when setting M is newly increased compared to the related art, the reduction of other processes has the effect of eliminating the increase in the number of processes. The error diffusion image has a large number of normalization processes compared to the character image.
Since the processing is performed once for each pixel, the introduction effect is increased even if the ratio of the number of reductions in each processing does not change significantly between the two images. In short, the second embodiment is different from the first embodiment in that a normalization process for a dominant symbol (MPS) is provided.

Embodiment 3 FIG. In the present embodiment, as in Embodiment 2, when encoding / decoding symbols and / or upper / lower regions are processed, processing is performed not by applying only a single normalization processing flow but by performing processing. It is characterized in that one is selected and applied from a plurality of processing flow candidates having the same processing result but different processing steps, and that a dedicated normalization processing flow is prepared for a region whose size has been corrected, Conventional processing flow is one of the candidates
It may be one. Further, the arrangement of the upper and lower regions may be upside down. The QM-coder, which is an example of the arithmetic coding described in the prior art and the first and second embodiments, uses a fixed region called LSZ as LP
S, allocate the remaining area A-LSZ to MPS,
When the condition of SZ> A-LSZ is satisfied, “conditional MPS / LPS exchange” for exchanging the correspondence between MPS and LPS is applied, and encoding is performed by preventing the magnitude of the appearance probability and the magnitude of the region from being reversed. The decrease in efficiency is suppressed. In the third embodiment, in arithmetic coding, QM-C
without applying conditional MPS / LPS exchanges like order

[0103]

(Equation 22)

Or

[0105]

(Equation 23)

[0106]

[0107]

(Equation 24)

Variable value

[0109]

(Equation 25)

Adjusted by the MPS area (A-LSZ)
+ Α), and the case of reallocation to the LPS area (LSZ-α) will be described. According to this method, below the MPS and LPS,
The correspondence with the upper region is always fixed. Further, the MPS area (A-LSZ + α) is set to a half of the minimum value A of 0x8000.
(= 0x4000) or more,
Expansion up to 0x8000 or more is always one bit as in the past. The LPS region (LSZ-α) is the same as the conventional LSZ
Is smaller than the area by α, the normalized shift number is LS
It may be larger than ZS. here,

[0111]

(Equation 26)

At the time

[0113]

[Equation 27]

Next, a method of reallocation will be described. α
Is the maximum LSZ / 2, so the LPS region (LSZ-
α) is a normalized shift number of LSZS or (LSZS +
1). In this case, the normalized shift number of the area (LSZ-α) is 2 by correcting the conventional LPS area width.
Can be limited to one. The description will be made on the assumption that the LPS region is fixedly arranged above and the MPS region is fixedly arranged below. If the width of the lower region (MPS region) before correction is X (<0x8000),

[0115]

[Equation 28]

Thus, the area width after correction is

[0117]

(Equation 29)

Is obtained. Upper area before correction (LPS area)
Since the width is LSZ, the area width after correction is

[0119]

[Equation 30]

Is obtained. In the present embodiment, the processing flow ENCODER (FIG. 8) in the encoding processing, ENC
ODE (FIG. 9), RENORM12 (FIG. 30), RE
NORMELSZ (FIG. 31), RENORMEMPS
(FIG. 36), BYTEOUT (FIG. 13), INITEN
C (FIG. 14), FLUSH (FIG. 15), CLEARBI
TS (FIG. 16), FINALWRITES (FIG. 17),
Processing flow DECODER in decoding processing (FIG. 1)
8), RENORMD12 (FIG. 33), RENORME
LSZ (FIG. 34), RENORMDMPS (FIG. 40),
BYTEIN (FIG. 24), INITDEC (FIG. 25)
Is the same as the processing flow in the second embodiment. In addition, the same processing elements as those already described in the processing flow with the same name have the same identifier.

FIG. 41 is a CODELPS processing flow corresponding to FIG. 28 of the first embodiment, and encodes the upper region.
In S121, the lower area, that is, the MPS area width is calculated. If the determination is Yes in S651, the correction of the area is unnecessary, and S123 to S404 described in FIG. 29 are executed as they are. If the determination is No, the area is corrected, and the encoding register 20 is updated in S652, and the area width register 21 which is the MPS area width is updated in S653. S654, S65
In steps S656 and S656, similarly to the processing in steps S401, S402, and S403, the determination of the predicted value inversion, the inversion, and the state transition by the LPS are performed. In step S657, a normalization process RENORMEALPH dedicated to LPS encoding with area correction
Call A.

FIG. 42 shows a CODEMPS processing flow corresponding to FIG. 35 of the second embodiment, and encodes the lower region.
In S131, the lower region, that is, the MPS region width is calculated. If the determination is No in S132, the encoding is terminated. If the determination is Yes, the area is corrected, and the area width register 21 is updated in S661. Normalization processing is required only when the area is corrected. In S136, state transition by MPS is performed, and in S601, normalization processing RENORMEMPS dedicated to MPS encoding is called.

FIG. 43 is a flow chart of the new RENORMALPH
In the processing flow A, the processing is applied to the normalization processing by the LPS encoding accompanied by the area correction. The processing flow is basically the same as the RENORMELZZ processing flow of FIG. 31 of the first embodiment, but between S452 and S453, S671-S67.
3 has been added. LSZ by area correction in S671
Area width register 21 expanded by S-bit shift processing
Is not greater than or equal to 0x8000. Judgment Y
In the case of es, RNM which is the total shift number of the normalization processing is increased by 1 in S672, and the area width register 21 is further expanded by 1 bit in S673. The remaining processing has already been described with reference to FIG.

FIG. 44 is a DECODE processing flow and corresponds to FIG. 37 of the second embodiment. In S221, the lower region, that is, the MPS region width is calculated. If the determination is No in S681, the area is not corrected, and if the determination is Yes, the area is corrected. When the determination is No in S681, the determination in S222 is Yes.
If so, the lower region, that is, the MPS is decoded, and the decoded pixel value is set as a predicted value in S226. If No in S222, the upper area (LSZ), that is, the LPS is decoded. S6
Steps 82 to S688 are the same as the steps S236 to S622 in the LPS_EXCHANGE of FIG. S68
If the judgment of 1 is Yes, the area correction processing DECODEALP
Call HA.

FIG. 45 shows the new DECODEALPHA
In the processing flow, a decoding process with region correction is performed. S69
In step 1, the lower area after the area correction, that is, the MPS area width is calculated. If the determination is Yes in S692, the lower region, that is, the MPS is decoded. If the determination is No, the upper region, that is, the LPS is decoded. If Yes in S692, M in S693
A state transition is performed by the PS, and in S694, a normalization process RENORM DMPS dedicated to MPS decoding is called, and S69 is performed.
In 5, the prediction value is set as a decoded pixel value. If the determination is No in S692, the decoding register 31B is updated in S696, the area width register 32 is updated in S697, and the non-prediction value is set as the decoded pixel value in S698. In S699, S700, and S701, the determination of the inversion of the predicted value, the inversion, and the state transition by the LPS are performed. In step S702, a normalization process RENORMALPHA dedicated to LPS decoding accompanied by area correction is called.

FIG. 46 shows the new RENORMALPH
In the processing flow A, the processing is applied to the normalization processing by the LPS encoding accompanied by the area correction. The processing flow is basically the same as the RENORMELZZ processing flow of FIG. 34 of the first embodiment, but between S502 and S503, S711-S71.
3 has been added. LSZ by area correction in S711
Area width register 32 enlarged by S-bit shift processing
Is not greater than or equal to 0x8000. Judgment Y
In the case of es, RNM which is the total shift number of the normalization processing is increased by 1 in S712, and the area width register 32 is further expanded by 1 bit in S713. The remaining processing has already been described with reference to FIG. In short, the third embodiment is provided with a process of normalization processing for an area in which the total number of bits for area expansion can be limited by correcting the state-specific size.

The first, second, and third embodiments show an example of arithmetic coding. In the QM-coder described above, the carry propagation range is not limited and pure coordinate values are used. Is output / input as a code,
A method of adding a control signal to a code when the carry propagation range to the upper part of the code is limited (for example, a bit stuff method)
Even if code output / input is performed using
UT processing, FINALWRITES processing, BYTEIN
Only the contents of the processing, the INITENC processing, and the INITDEC processing are changed.
And it does not essentially hinder the introduction of the third embodiment.

[0128]

As described above, according to the present invention, the normalization processing of arithmetic coding is performed by selecting a normalization processing suitable for the situation. The reduction enables selection of an optimal normalization process.
In particular, in the encoding and decoding processes, speeding up can be realized by integrating or omitting a part of the normalization process.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating encoding of a conventional Markov information source.

FIG. 2 is a diagram illustrating a conventional encoder.

FIG. 3 is a diagram showing a schematic configuration diagram of a conventional encoder.

FIG. 4 is a diagram showing a schematic configuration diagram of a conventional decoder.

FIG. 5 is a diagram showing a conventional model template.

FIG. 6 is a diagram showing a conventional state transition.

FIG. 7 is a diagram illustrating a conventional encoding operation register.

FIG. 8 is a diagram showing a conventional ENCODER processing flow.

FIG. 9 is a diagram showing a conventional ENCODE processing flow.

FIG. 10 is a diagram showing a conventional CODELPS processing flow.

FIG. 11 is a diagram showing a conventional CODEMPS processing flow.

FIG. 12 is a diagram showing a conventional RENOMEME processing flow.

FIG. 13 is a diagram showing a conventional BYTEOUT processing flow.

FIG. 14 is a diagram showing a conventional INITENC processing flow.

FIG. 15 is a diagram showing a conventional FLUSH processing flow.

FIG. 16 is a diagram showing a conventional CLEARBITS processing flow.

FIG. 17 is a diagram showing a conventional FINALWRITES processing flow.

FIG. 18 is a diagram showing a conventional DECODER processing flow.

FIG. 19 is a diagram showing a conventional register for decoding operation.

FIG. 20 is a diagram showing a conventional DECODE processing flow.

FIG. 21 is a diagram showing a conventional LPS_EXCHANGE processing flow.

FIG. 22 is a diagram showing a conventional MPS_EXCHANGE processing flow.

FIG. 23 is a diagram showing a conventional RENORMD processing flow.

FIG. 24 is a diagram showing a conventional BYTEIN processing flow.

FIG. 25 is a diagram showing a conventional INITDEC processing flow.

FIG. 26 is a diagram illustrating an overall configuration of an image encoding / decoding device according to the present invention.

FIG. 27 is a diagram illustrating an overall configuration of an image encoding / decoding device according to the present invention.

FIG. 28 is a diagram showing a CODELPS processing flow of the present invention.

FIG. 29 is a diagram showing a CODEMPS processing flow of the present invention.

FIG. 30 is a diagram showing a flow of a RENOME 12 process of the present invention.

FIG. 31 is a diagram showing a RENORMELZZ processing flow of the present invention.

FIG. 32 is a diagram showing a DECODE processing flow of the present invention.

FIG. 33 is a diagram showing a RENORMD12 processing flow of the present invention.

FIG. 34 is a diagram showing a RENORMDLSZ processing flow of the present invention.

FIG. 35 is a flowchart showing a CODEMPS processing flow of the present invention.

FIG. 36 is a diagram showing a RENORMEMPS processing flow of the present invention.

FIG. 37 is a diagram showing a DECODE processing flow of the present invention.

FIG. 38 is a diagram showing an LPS EXCHANGE processing flow of the present invention.

FIG. 39 is a diagram showing an MPS EXCHANGE processing flow of the present invention.

FIG. 40 is a diagram showing a RENORM DMPS processing flow of the present invention.

FIG. 41 is a diagram showing a CODELPS processing flow of the present invention.

FIG. 42 is a diagram showing a CODEMPS processing flow of the present invention.

FIG. 43 is a diagram showing a flow of a RENORMAL APAH process of the present invention.

FIG. 44 is a diagram showing a DECODE processing flow of the present invention.

FIG. 45 is a diagram showing a DECODEALPH processing flow of the present invention.

FIG. 46 is a diagram showing a RENORMALPH processing flow of the present invention.

[Explanation of symbols]

7 QM encoder, 8 QM decoder, 9 image memory, 1
0 Predicted value table MPS, 11 State table S
T, 12 LPS area width table LSZ, 13 MPS state transition destination table NMPS, 14 LPS state transition destination table NLPS, 15 predicted value inversion determination table SWT
CH, 16 pixel symbol converter, symbol pixel converter, 17 predicted value update processor, 18 state update processor, 19 arithmetic encoder, 30 arithmetic decoder.

Continuation of the front page (56) References JP-A-58-85629 (JP, A) JP-A-6-85684 (JP, A) JP-A-5-37391 (JP, A) JP-A-6-311046 (JP, A) JP-A-10-79938 (JP, A) JP-A-63-76525 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/40

Claims (12)

(57) [Claims] When encoding a digital signal, a fixed-size area (S _i ) in which an area (A _i−1 ) on a number line with respect to the immediately preceding symbol corresponds to a less probable symbol having a lower appearance probability than the current symbol. ) And a region (A
_i−1 −S) and an area selected by the appearance value of the current symbol is defined as an area (A _i ) on a new number line,
When the size of the area (A _i ) is smaller than a predetermined set value, the coordinates on the number line are maintained by performing a normalization process for enlarging the area so that it becomes equal to or larger than the set value and maintaining the calculation accuracy on the number line. In an encoding device that outputs a code, a plurality of enlargement processes are provided in advance for a normalization process applied when the area (A _i ) for the current symbol is smaller than the set value, and the area (A _i ) An encoding apparatus characterized in that, when the area (A _i ) is smaller than the set value, a normalization process suitable for a situation is selected and executed from the plurality of enlargement processes. 2. When decoding a digital signal, a fixed-size area (S _i ) in which an area (A _i-1 ) on the number line with respect to the immediately preceding symbol is made to correspond to an inferior symbol having a low appearance probability with respect to the current symbol. ) And a region (A
_i−1 −S) and an area selected by the appearance value of the current symbol is defined as an area (A _i ) on a new number line,
When the size of the area (A _i ) is smaller than a predetermined set value, the coordinates on the number line are maintained by performing a normalization process for enlarging the area so that it becomes equal to or larger than the set value and maintaining the calculation accuracy on the number line. In the decoding apparatus for inputting a code, a plurality of enlargement processes are provided in advance for the normalization process applied when the area (A _i ) for the current symbol is smaller than the set value, and the area (A _i ) And when the area (A _i ) is smaller than the set value, a normalization process suitable for the situation is selected and executed from the plurality of enlargement processes. 3. The normalization process according to claim 1, wherein, when performing the normalization process, a normalization process is provided for expanding a region having a state-specific size in which the total number of bits of the region expansion is obvious in advance. Encoding device. 4. The normalization process according to claim 2, wherein, when performing the normalization process, a normalization process for expanding a region having a size specific to a state in which the total number of bits of the region expansion is self-evident is provided. Decryption device. 5. The code according to claim 1, wherein, when the normalization processing is performed, a normalization processing for enlarging an area excluding a state-specific size area from the entire current area is provided. Device. 6. The decoding according to claim 2, wherein, when performing the normalization processing, a normalization processing for enlarging an area excluding a state-specific size area from the entire current area is provided. Device. 7. The encoding apparatus according to claim 1, wherein when performing the normalization processing, a normalization processing for enlarging a region of a dominant symbol is provided. 8. The decoding apparatus according to claim 2, wherein when performing the normalization processing, a normalization processing for expanding a region of a dominant symbol is provided. 9. The normalization process according to claim 1, further comprising the step of: correcting a size specific to a state to expand a region in which the total number of bits of the region expansion can be limited. An encoding device according to claim 1. 10. The normalizing process according to claim 2, wherein a normalizing process is provided for enlarging an area in which the total number of bits of the area expansion can be limited by correcting a state-specific size. 3. The decoding device according to claim 1. 11. An image coding processing apparatus according to claim 1, wherein said coding apparatus is provided in an electronic computer, a scanner, a facsimile, a printer, a semiconductor chip, or the like. 12. An image decoding processing apparatus according to claim 2, wherein the decoding apparatus is provided in an electronic computer, a scanner, a facsimile, a printer, a semiconductor chip, or the like.