JP3115117B2 - Binary image compression processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to an encoder / decoder (codec) for compressing and expanding binary image data. More specifically, the present invention relates to an encoding system (MH) conforming to CCITT recommendations. , An MR method, an MMR method, etc.).

[0002]

2. Description of the Related Art MH conforming to 4
(Modified Huffman) / MR (Modified READ) method and A number of binary image encoding / decoding devices (CODEC: codec) using the MMR (Modified MR) system conforming to J.6 have already been created. As a codec for this binary image, the present applicant has previously filed Japanese Patent Application No. 62-59.
No. 990, "binary data compression / decompression processing device".

Generally, encoding of a binary image, that is, compression processing is performed according to a flowchart of CCITT recommendation shown in FIG. If encoding is performed according to this flowchart, the bit pattern of the compressed coded data generated for a given image is also uniquely determined.

However, when encoding is performed on a binary image as shown in FIG. 12A, for example, according to this flowchart, as shown in FIG. 12B, "Pass" in the pass mode and "Pass" in the vertical mode VL (2) "expresses a white run of a coding line in the vertical and horizontal directions of two codes. On the other hand, obviously, in this example, FIG.
As shown in (c), it can be expressed by one code of "VR (3)" in the vertical mode.

[0005] The encoding lines in FIG.
L (2) ”instead of cascaded,
(3) Even if it is expressed by one code of ",
Obviously, it can be decoded with an MR or MMR decoder according to the ITT recommendations. In fact, the standard for MR coding is
In addition to the above, there are a plurality of encoding schemes for a given image, and it is allowed to select and output an appropriate one from among them according to the application.

[0006] For example, a paper "International Facsimile Standards" discussing the design concept of the MH / MR coding method.
”Proceedings of IEEE, vol 68, No. 7 July 1980,
(By RoyHunter & A. Harry Robinson). 864-
P. 865 generally describes the following contents.

"It is possible to change the encoding procedure shown in the flowchart of FIG. 11 without contradicting between the encoder and the decoder. To make such a change, a detailed study is required. For example, if a number of passcodes continue, the coding efficiency is reduced, so that it is possible to limit the passcodes so that they do not continue.If (absolute value of a ₁ b ₁ ) ≦ 3, Since the coding can be performed in either the vertical (V) mode or the horizontal (H) mode, the shorter coding may be used. "

In the flowchart of FIG. 11, encoding in the horizontal mode even in the case where the mode should be the vertical mode has been frequently used in order to facilitate the design of an encoder other than the above. For example, since a large amount of reference line data is to be divided into blocks for internal processing and managed, when encoding a point a ₁ near the block boundary, a point b ₁ in the next block is used. Is performed in the horizontal mode without performing the vertical mode coding based on.

Since the code data encoded by the MR method is not uniquely determined, the code data is generally decompressed by decompressing the code data even when testing the encoder by the MR method. It is common to make data before comparing.

[0010]

As described above, FIG.
If the encoding is realized according to the flowchart shown in (1), an unnecessary passcode may be entered, so that the code data becomes longer than necessary.

In order to realize an encoder as shown in the flow chart of FIG. 11 as a "binary data compression / expansion processing apparatus" described in Japanese Patent Application No. 62-59990, b
A two-point detection circuit was required (see Japanese Patent Application No. 62-5 / 1987).
No. 9990 "Binary data compression / decompression processing apparatus" is not related to the claims, so that the description of the b2 point detection circuit is omitted. ).

In this case, it is necessary to confirm that the point b ₂ does not exist on the left side of the point a ₁ in the encoding in the vertical mode having the highest appearance frequency. For this purpose, the b _{2 point} detection circuit is provided as hardware, and a ₁ point, b
_It is necessary to detect ₁ point and b ₂ point in parallel. This b ₂
Main part of the point detection circuit are the same circuits as b ₁ point detection circuit disclosed in FIG. 5 of Japanese Patent Application Sho 62-59990. This b _{2 point} detection circuit is a circuit that is used only at the time of encoding and cannot be used at all for decompression processing.

However, after it is determined that the vertical mode coding can be performed without the b _{2 point} detection circuit, the b ₂ point is checked in parallel with the coding, and the coding is canceled if the condition is not met. Is also conceivable. However, in a pipeline type process generally used for an encoder for the purpose of high-speed processing, control becomes difficult if a canceling procedure is included.

[0014] The present invention has been made in view of the points mentioned above, b ₂ point detection while eliminating the need for circuit, unnecessary paths eliminates code binary image that can increase the data compression ratio An object of the present invention is to provide a compression / decompression processing method.

[0015]

According to the present invention, there is provided a binary image compression processing apparatus for compressing a binary image by a two-dimensional encoding system which handles a vertical mode code, a pass mode code and a horizontal mode code. A first method of detecting a predetermined color change point from an image of a target coding line
Change point detection means, second change point detection means for detecting a predetermined color change point from an image of a reference line corresponding to the encoding line, and color change to be detected by the first change point detection means A first control means for controlling the direction of the color change, and a second control means for controlling the direction of the color change to be detected by the second change point detection means, wherein the first and second change point detection means are provided. When a change point is detected in at least one of the above, the relative positional relationship between the change point of the coding line and the change point of the reference line is | (change point of the coding line) × (reference
(Change point of line) |
If the above conditions are not satisfied, it is determined that a code in the horizontal mode can be generated, and a first step of generating a code in the vertical mode or the horizontal mode, and the code cannot be generated in the first step If the state of the first control means maintaining the same state as the first step, the state of the second control means performs the first step and the opposite state to the to the change point detection, change point If detected, a compression process is performed according to a second step of generating a code in a pass mode or a horizontal mode.

[0016]

According to such a configuration, unnecessary pass codes can be eliminated by checking the coding in the vertical mode in preference to the check in the coding in the pass mode. That is, usually, for example, by giving priority to the encoding in the vertical mode, which accounts for approximately 90% of the MMR code data, the encoding process can be simplified and generally speeded up.
Further, when performing the compression processing according to the configuration described in Japanese Patent Application No. 62-59990, the b ₂ point detection circuit can be omitted since the b ₂ point need not be considered when encoding can be performed in the vertical mode. . The vertical mode encoding cannot be performed and b ₁
Only when a point has been detected, the point b ₂ is detected again. In that case, as it is to use the circuit for the b ₁ out inspection.

[0017]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a binary data compression / decompression processing apparatus according to the embodiment. As shown in FIG. 1, the binary data compression / decompression processing device includes a decoding unit 2, a processing unit 4, a generation unit 6, a buffer unit 7, an illumination line image buffer memory 8, a control unit 1 for controlling these, and a decoding unit. It has a sub-sequencer 5 and has a pipeline type configuration.

The decoding section 2 decodes the code word data obtained through the input bus 9 at the time of decompression, detects a change point from the image data of the coded line obtained through the input bus 9 at the time of compression, and detects a line change. Get the length.

The processing section 4 detects a change point from the image data of the reference line in the two-dimensional compression / expansion processing.
The processing unit 4 calculates the difference between the positions of the points a ₁ and b ₁ based on the detection result of the change point during compression and the detection result of the decoding unit 2, determines a codeword to be generated, and determines the result. Generator 6
And calculates the position of the next point a ₀ and sends it to the decoding unit 2. That is, the processing unit 4 determines the vertical mode / pass mode / horizontal mode. For example, the processing unit 4 sends to the generation unit 6 the information to be encoded in the vertical mode and the calculation result of a ₁ −b ₁ . At the time of decompression, the processing unit 4 determines the following a based on the detection result of the change point and the decoding result
The position of the _zero point is calculated and sent to the generation unit 6, and a
The difference between the positions of the ₀ point and the a ₁ point is calculated, and the control unit 1 is notified of whether or not the run processing has been completed. The generation unit 6 includes a processing unit 4
Based on the data from, a code word is generated at the time of compression and image data is generated at the time of decompression.

The reference line image buffer memory 8
At the time of compression, the image data input to the decoding unit 2 is held for use as a reference line for the image data of the next line. At the time of decompression, the image data generated by the generation unit 6 is decoded by the code word of the next line. In this case, it is a memory that is held to be used as a reference line. The input bus 9 is connected to the decoding unit 2 and inputs binary data, and the output bus 10
Is connected to the generator 6 to output compressed and decompressed binary data.

The decoding unit sub-sequencer 3 is activated by the control unit 1 when decompressing, and controls the decoding unit 2. The generating unit sub-sequencer 3 is activated by the control unit 1 during compression,
It controls the generation unit 6. The control unit 1 controls the processing unit 4,
The decompression unit 2 is directly controlled together with the generation unit 6 during decompression and the decryption unit 2 during compression. That is, the blocks that handle image data are collectively controlled by the control unit 1, the blocks that handle codewords are independently controlled by dedicated subsequences, and each block operates in parallel. Next, the configuration and operation of each unit will be described in detail with reference to FIGS. Since the operation of each unit is different between the decompression process and the compression process, the two-dimensional decompression process and the two-dimensional compression process will be described separately. (1) Two-dimensional expansion processing

First, the decoding section 2 will be described with reference to FIG. Reference numeral 21 denotes registers RDTI0-23 in which codeword data is set. The register 21 inputs the code word data as data A one byte at a time. Each time code word data is input, the data RDTI16-23 becomes RDTI8
At -15, the data RDTI8-15 moves to RDTI0-7. That is, the register 21 is configured to move to the left 8 bits (in byte units) in one clock. Reference numeral 22 denotes a barrel shifter that inputs data RDTI 9-23 and outputs data SHTD0-7 obtained by shifting (left shifting) RDTI 9-23 in the reverse direction by the value indicated by the register 32. Data RB from register 32
PP2-0 indicates the last (leftmost) bit number of already decoded data among the codeword data input to the barrel shifter 22. For example, RBPP2-10 is "011"
In the case of, RDETI out of the input data RDTI9-23
12-19 is the output data SHTD0-7. Reference numeral 23 denotes an inverting circuit that performs an exclusive OR operation on the control signal b sent from the control circuit 11 (FIG. 8) of the control unit 1 and each bit of SHTD0-7. However, in the case of expansion, the control signal b is always "0", and this inverting circuit 23 does not substantially operate.

Reference numeral 31 denotes a selector.
The output data ABPP2-0 from the adder 33 is selected. Numeral 25 is a register in which data DTIS0-7 from the inverting circuit 23 is set. The data RPAT0-7 set in this register 25 is stored in the non-compression mode (in the decompression process, after decoding the non-compression mode codeword, (The image data following the code word is output as it is). Reference numeral 24 denotes a mask circuit for masking a specific bit of the data DTIS0-7. Data DTIS
0-7 are gates 2 directly or through a mask circuit 24.
6 given. The gate 26 receives the 3-bit data E (RDSQ4-2) from the control unit 1 and the data DTIS0-7.
And the address data DR of the decoder ROM 27 based on
MA10-0 is supplied to the decoder ROM 27. RDSQ
4-2 becomes DRMA10-8, and DDIS0-7 becomes DMA.
RMA7-0. When expanded, the decoder ROM 27 decodes the compressed codeword data. (Compressed, to detect a run length of a _1-point and the image data.) Decoder R
The address configuration of the OM 27 is as shown in Table 1.

[0024]

[Table 1]

The decoding unit subsequencer 3 is one-dimensionally expanded,
2D decompression, non-compression mode decompression, special type (uncompressed final, E
Data RDSQ4 according to processing conditions such as OL search).
Set a different value to -2.

In the one-dimensional expansion, when decoding the code word data indicating the white run, the control unit 1 firstly reads the DRMA 10-8.
= “000” (white A) and if the code word is 9 bits or more, it cannot be decoded at a time, so white B (DR
MA10-8 = “001”).

When decoding code word data indicating a black run, the decoding sub-sequencer 3 first sets the DRMA 10-8 =
When it is set to “010” (black A) and the decoder ROM 27 decodes six consecutive “0” from the beginning of the code word data, black A is followed by black B (DRMA10-8 = “011”).

If four "0" s are decoded consecutively from the beginning of the code word data in the decoder ROM 27, black A is followed by black C (DRMA10-8 = "100"). 2
In dimension expansion, DRMA10-8 = "101", and in uncompressed mode expansion, DRMA10-8 = "110". In the case of the final decompression in the non-compression mode and the EOL code search, DRMA10-8 = “111”.

In the DRMA 7-0 of Table 1, the underlined portions indicate bits to be masked by the mask circuit 24. The masking conditions are shown below. When decoding with black A, if (D ₀ , D ₁ ) is not (0, 0), D _{3 to} D
₆ is all "1". When decoding by two-dimensional expansion, (0
When (0,01) is not (0,0), all of 0 _{3 to} 0 ₅ are set to “1”. When decoding in uncompressed mode, (D ₃ , D
_{If 4} ) is not (0, 0), D ₀ and D ₂ are all “1”.
And When decoding with special, (D ₀ , D ₁ ) is (0,
If not 0), and all 0 _{3-0 7} "1". With this mask circuit 24, the storage area of the decoder ROM 27 can be reduced. Also, the same result can be obtained even if the mask circuit 24 is omitted and the same data is written in the corresponding address area of the decoder ROM 27 instead.

Next, the output data D of the decoder ROM 27
The configuration of the ROM 11-0 will be described. DROM1 1
Data -9 indicating a transition condition to the next state is sent to the decryption unit serve sequencer 3. The decryption unit serve sequencer 3 determines the next processing condition DRMA10-8 based on the data DROM11-9. The DROM 8-5 is data indicating a value obtained by subtracting -1 from the code word length (code word length -1) and sent to the adder 33. DROM5-0
Is as shown in Table 2.

[0031]

[Table 2] In Table 2, δ-4 is data indicating the position of point a ₁ with reference to point b ₁ , and δ-4 corresponding to each code word in the vertical mode is as shown in Table 3.

[0032]

[Table 3] DROM 5-0 is sent to selector 28. Selector 2
The selection of data in 8 is based on an instruction from the control unit 1. Table 4 shows selection conditions corresponding to each data.

[0033]

[Table 4]

In Table 4, while continuously generating runs of 2 bytes or more, "ANLC8-0 RNLC2-
0 ”is selected, and in the step of generating the last byte of the run, in order to receive the run length of the next run from the decoding unit 2,
“000000 DROM5-0” or “DROM
5-000000 "is selected, and" 100111111100 "is selected at the start of the compression processing.The selection based on these three conditions is determined by the control unit 1, and" 000000 DROM5-1 "or" DR
The selection of OM5-000000 "is determined by the decryption unit 2.

The selected data DNLC11-0 is set in the register 29. The adder 30 subtracts 1 from the data RNLC 11-3 from the register 29 until the coincidence signal e from the comparator 34 becomes valid during the one-dimensional expansion processing. (In addition, during the compression process, the adder 30 subtracts 1 from the data RMLC11-3 from the register 29 every time one byte of image data is processed.) The data ANLC8-0 from the adder 30 is sent to the selector 28. , Is selected by the selector 28 and set in the register 29. Further, the data ANLC8-
0 is also sent to the generation unit 6 as data J. Data J
Is used in the compression process.

Data RMLC set in register 29
3-0 is sent as data K to the gate 51 and the selector 53 shown in FIG. The RNLC 11-4 is sent to the comparator 34. The comparator 34 is provided to indicate the end of the generation of the run during the one-dimensional expansion processing.
11-4 and “00000000” are compared, and if they match, a match signal e is sent to the control unit 1. The control unit 1 instructs the generation unit 6 to generate image data based on the coincidence signal e and the value of the RNLC 3-0 so that an image of a predetermined length is generated.

On the other hand, the adder 33 adds the data RBPP2-0 set in the register 32 and the data DROM8-6 from the decoder ROM 27, and adds 1 to the addition result. That is, the data ABPP2-0 output by the adder 33 is expressed by the following equation. ABPP2-0 = RBPP2-0 + DROM8-6 + 1 The ABPP2-0 is selected by the selector 31 and set in the register 32. For example, if RBPP2-0 is 01
1 "(= 3), and the decryption result DROM 8-6 (code length -1) by the decoder ROM 27 is" 110 "(= 6).
In the case of ABPP2-0 = “011” + “110” + “001” = “(1) 010”

## EQU4 ## This 4-bit information is
−0 is output as ABPP2-0, and bit 3 is output to the control unit 1 as a control signal COABPP (not shown). The control unit 1 determines a value based on the value of the control signal COABPP,
When COABPP is “1”, it is determined that a one-byte codeword has been processed, and the next one-byte codeword data is input to the register 21. When COABPP is “0”, the next processing is continued without changing the register 21. In the case of the above example, since ABPP2-0 is “010” (= 2) and COABPP is “1”, the register 21 is set to 1
The byte is advanced, and the next code word data is transferred to the barrel shifter 22.
Is shifted by 2 bits.

Next, the processing section 4 will be described with reference to FIG. 41 is a register RREF0-27 in which image data of the reference line is set. Register 41
Inputs image data as data N one byte at a time. Each time image data is input, data RREF20
-27 is RREF12-19, RREF12-19 is RREF4-11, RREF8-11 is RREF0-
Go to 3.

42 inputs data RREF0-21,
This is a barrel shifter that outputs data SHTP0-14 obtained by shifting RREF0-21 in the reverse direction by the value indicated by the register 46. Data RBPA2 from register 46
−0 is data indicating a value obtained by subtracting 4 from the bit number at the position of the point a ₀ corresponding to the image data input to the barrel shifter 42. Therefore, in the data SHTP0-14 shifted by the barrel shifter 42, a ₀
The position of the point is SHTP4 (bit 4). By shifting in this way, a change point can be detected from the position of the point a ₀ to a range in the 3-bit non-processing direction. For example, when RBPA2-0 is “011” (= 3),
Data RREF0-21 is shifted by 3 bits by barrel shifter 42, and RREF3-17 is shifted to SHTP0-14.
Becomes

Reference numeral 43 denotes a control signal a (FBLKC) sent from the control circuit 11 (FIG. 8) of the control unit 1 and SHTP0-1.
4 is an inverting circuit that performs an exclusive OR operation with each of the four bits.
This inverting circuit 43 is for unifying the direction of color change of the pixel. In this embodiment, the direction of the color change is unified from white to black.
The configuration is such that only the black change point is detected. Therefore, when the change point to be detected is white, the change point detection circuit 45 can detect an appropriate change point by inverting the image data in advance by the inversion circuit 43. When the change point to be detected is black, the inverting circuit 43 outputs SHTP0-1.
Pass through 4.

[0042] 44 is the change point detection circuit for detecting a b ₁ point or b ₂ points from data DREN0-14 output from the inverting circuit 43. The change point detection circuit 44 sets the bit that is a change point candidate to “0” and sets the other bits to “1”.
REC 1-14 is output. The detailed configuration of the change point detection circuit 44 will be described later. 45 inputs data DREC1-14 indicating a change point candidates to detect the leftmost candidate from the changing point candidates, a priority encoder to convert the data indicating the position of the point (b ₁ point). Output data B1D of the priority encoder 45
T3-0 is as shown in Table 5 according to the value of DREC1-14.

[0043]

[Table 5]

In Table 5, "0" indicates a change point,
“*” Indicates that any data may be used. For example, when B1DT3-0 is “0111” (= 7), DR
It indicates that the leftmost transition point exists in bit 7 of EC1-14.

Also, bit numbers 1 to 1 of DREC1-14
14 is compared with the image data of the coding line,
It corresponds to bit numbers -3 to 10. That is,
This means that the change point detection circuit 44 performs change point detection on the image data of the encoded line with a bit width that is expanded by 3 bits each in the processing direction and the non-processing direction. The value of B1DT3-0 is DREC1
-14 to indicate the bit number,
Table 6 shows which bit numbers of C1-14 represent the bit numbers as compared with the coding lines.

[0046]

[Table 6]

From Table 6, it can be understood that B1DT3-0 indicates a value obtained by adding 4 to the original bit number when compared with the image data of the encoding line.
For example, when B1DT3-0 is “0011” (= 3),
The original bit number is "-1".

When B1DT3-0 is viewed from the bit position of RREF0-26, since RREF0-21 has been shifted by the value indicated by RBPA2-0 by barrel shifter 42, B1DT3-0 has 4 bits as the original bit number. can be seen that shows the value obtained by subtracting the RBPA2-0 from plus (position of a ₀ point).

The B1DT detected as described above
In 3-0, an operation is performed according to processing such as expansion and compression. 47, 48, 53, 54, 59 are selectors, 50,
51 and 55 are gates, 49, 52, 56 and 58 are adders, and 57 is an inverting circuit.

First, the case of the two-dimensional expansion processing will be described. In the case of the two-dimensional decompression process, the data S input to the gate 51 and the selector 53 is the data RNLC3-0 given from the decoding unit 2 as data K, and is 1-bit data indicating whether the process is the two-dimensional decompression process or the one-dimensional decompression process. And sent from the control unit 1.

In the case of two-dimensional decompression processing, it becomes "1" and 1
In the case of the dimension extension processing, it is “0”. The selector 51 is 2
In the case of the dimension expansion processing, the data S (“1”) and RNLC2
The data constituted by −0 is sent to the adder 52. Adder 5
2, data from the selector 50 composed of “0” and RBPA2-0 is further input. For example, decryption unit 2
When the vertical mode code word is decoded,
Sum A0PL3-0 by the, A0PL3-0 = "0" RBPA2-0 + "1" RNLC2-0 = a 0 + (δ-4) = δ - 4 + a 0

Is as follows. The addition result A0PL3-0 is further extended by one bit into five-bit data by a gate 55 to be sent to an adder 56. Adder 5
To the other input 6, data obtained by sign-extending B1DT3-0 to 5 bits is input from the selector 54. For example, when the decoding unit 2 decodes a vertical mode codeword,
The addition result AB1A4-0 by the adder 56 is: ABIA4-1 = “0” B1DT3-0 + “1” A0PL3-0 = (b ₁ + 4-a ₀ ) + (δ−4 + a ₀ ) = b ₁ + δ = _{b 1 + (a 1 -b 1} ) = a 1

Is as follows. AB1A2-0 of the addition result AB1A2-0 is sent to the selector 59. The selector 59 selects AB1A2-0, and selects the data DBPA2
It is sent to the generation unit 6 as −0. Further, the data DBPA2-
0 is set in the register 46 and indicates the next _a0 point.

On the other hand, the data RNLC3-0 selected by the selector 53 and the data B1DT3-0 passed through the inverting circuit 57 are input to the adder 58. The example decoding unit 2, when decrypting the vertical mode code words, the addition result ADLT3-0 by the adder 58, ADLT3-0 = B1DT3-0 + RNLC3-0 = (b 1 + 4-a 0) + (δ- 4) = b ₁ + δ−a ₀ = a ₁ −a ₀ Then, this data is sent to the control unit 1. When this value is 8 or less, the control unit 1 recognizes that the run processing has been completed.

Next, the case of one-dimensional expansion will be described. In the case of one-dimensional expansion, the data RNLC2-0 from the register 29 of the decoding unit 2
Is input to RNLC2-0 represents a run length of less than 1 byte, and is provided in order to calculate the position of the next a ₀ point. The data S is set to “0” in the one-dimensional expansion processing. This data S (“0”) and RNL
The data from the selector 51 composed of C2-0 is sent to the adder 52. The data from the selector 50 composed of “0” and RBPA2-0 is further input to the adder 52. Addition result A0PL3 by adder 52
-0 A0PL3-0 = "0" RBPA2-0 + "0" RNLC2-0 = a 0 + RL

Is as follows. Here, “a ₀ ” indicates the position of the a ₀ point, and “RL” indicates a run length of 1 byte or less.
This A0PL3-0 is sent to the selector 55. The data T input to the selector 55 is “0” in the case of the one-dimensional expansion processing. Data from the selector 55 composed of the data T (“0”) and A0PL3-0 is sent to the adder 56. The data “11111” selected by the selector 54 is further input to the adder 56. Adder 5
At 6, after adding the selector 54 and the selector 55, 1 is further added. Therefore, the addition result AB1A4-0 is AB1A4-0 = “11111” + “0” A0PL3-0 + 1 = 1 = “0” A0PL3-0 = a ₀ + RL

Is as follows. AB1A2-0 of the addition result AB1A4-0 is sent to the selector 59. The selector 59 selects this ABPA2-0 and outputs the data DBPA2
It is sent to the generation unit 6 as −0. In addition, this DBPA2-0
Is set in the register 45.

Next, the generator 6 will be described with reference to FIG. Here, only the configuration used in the case of the decompression process will be described, and the configuration used in the case of the compression process will be described later.

Reference numeral 70 denotes a selector.
“1111111” according to the color of the image data to be generated
Selector 1 ”(black) or“ 00000000 ”(white) The selector 70 outputs the data DREN4-11 from the processing unit 4 when an error occurs during the two-dimensional expansion processing and an image cannot be generated. This is because, when an error occurs, the data of the reference line is replaced as it is, and the selector 70 selects the output data EROM7-0 of the encoder ROM 66 during the compression processing. In the case of the mode, the data RPAT0-7 is selected from the decoding unit 2. This is because, when the non-compression mode code is decoded in the decompression processing, the subsequent uncompressed image is output as it is.

Reference numeral 71 denotes a rotate shifter, which shifts the data ECDP0-7 from the selector 70 to the right by the value indicated by the data RBPQ2-0 from the register 68, and inputs the overflowed data from the left. For example,
ECDP when RBPQ2-0 is "010" (= 2)
0-7 are shifted right by 2 bits, and bits 6 and 7 of ECDP0-7 overflow and are input from the left. Therefore, the output data SHT of the rotate shifter 71
G0-7 becomes ECDP6, 7, 0-5. In the decompression processing, ECDP0-7 is set to “11111111” or “0
00000000 ", the contents do not change even through the rotation shifter 71.

Data SHTG0-7 output from rotate shifter 71 is output to selector 72 and selector 73. Data EPSL0-7 generated halfway has already been input to the selector 72. In accordance with the value indicated by data RBPQ2-0 from register 68, selector 72 selects data on the left side of the indicated value from EPSL0-7, and selects data on the right side of the indicated value including the indicated value as SHTG0.
Select from -7. The selected data EPCK0-7 is output to the register 73.

EPC is set in RODT0-7 of the register 73.
K0-7 is set, and SHTG0 is set in RODT8-15.
-7 is set. Data RODT0-7 is in register 7
5 and the selector 74. Selector 74 is RO
If image data generation is completed in DT0-7, RODT8-15 is selected. If image data generation is incomplete in RODT0-7, RODT0-7 is selected.
Select Whether or not the image data generation is completed in RODT0-7 is determined when the bit 1 of the addition result of the adder 58 becomes "1".
In step 7, the completion of image data generation is recognized. Thus, the control unit 1 sends a selection signal to the selector 74. The data EPSL0-7 from the selector 74 is supplied to the selector 72.
And then combined with the output SHTG0-7. The register 75 is a register in which RODT0-7 is set, and when the image data generation is completed in RODT0-7, it is read out as data ROUT0-7S.

In the case of one-dimensional expansion processing, ROUT0-7 is output to the outside as data C, and in the case of two-dimensional expansion processing, it is output to the outside and used as a reference line in the expansion of the next line. The data C is also sent to the buffer unit 8. The decompression process proceeds as described above. (2) Two-dimensional compression processing Next, the configuration and operation of each unit in the compression processing will be described.

First, the decoding section 2 will be described with reference to FIG. In the case of compression processing, the register 21 is set with image data. The register 21 inputs the image data one byte at a time. Each time image data is input, the data RDTI 16-23 is shifted to RDTI 8-15, and the data RDTI 8-15 is shifted to RDTI 0-7.
Since RDTI0-7 is used as image data of a reference line when processing the next encoding line, data B
Is sent to the buffer unit 8. RDT of register 21
I9-23 is input to the barrel shifter 22. The barrel shifter 22 stores only the value indicated by the register 32 in the RDTI 9-2.
3 in the anti-processing direction. For example, as an initial value R
Since BPP2-0 is "111" (= 7), the barrel shifter 22 shifts by 7 bits. Therefore RDTI16
-23 will be processed first as SHTD0-7. In the case of the compression process, the selector 31 selects the output data DBPA2-0 from the processing unit 4.

Output data SHT from barrel shifter 22
D0-7 is input to the inverting circuit 23. Inverting circuit 23
Is provided to unify the direction of color change of a pixel when detecting a change point. In this embodiment, the direction of color change of pixels is unified from white to black, and only black pixels are detected as change points. Therefore, the inverting circuit 2
3 inverts image data when it is desired to detect a white pixel as a change point. The inverting circuit 23 outputs a control signal b (FB
LKB) and each bit of SHTD0-7 is exclusive-ORed. The control signal b (FBLKB) is valid ("1") when it is desired to detect a white pixel as a change point.

Data DTI0-7 from inverting circuit 23
Is supplied to the selector 26 via the mask circuit 24.
Data D (DNDP0-7) is input to the selector 26. This data DNDP0-7 is data for supplementing a virtual change point one bit to the right of the end point of the line. Normally, each bit of the data DNDP0-7 is "0", and when processing the last data of the line, only the bit position of the data DNDP0-7 on the right side of the end point is "1". Data obtained by calculating the logical sum of the data DNDP0-7 and the data DTIS0-7 is selected by the selector 26 and becomes DRMA7-0. Also,
In the case of compression processing, the mask circuit 24 masks data in accordance with the above-described condition because the processing condition is "special" as shown in Table 1. The selector 26 is supplied with “111” as data E from the control unit 1. Selector 2
6 is given “111” as data E from the control unit 1. Therefore, the data DRMA10 from the selector 26
-8 becomes "111".

The address data DRMA10-0 is supplied to a decoder ROM 27, which decodes the data and outputs a decoding result DROM11-0.
In the case of compression processing, DRMA10-8 is “111”, and bits 11, 10, and
9 and 5 are not used, so that each address data DRMA
Table 7 shows the decoding results DROM8-6, 4-0 corresponding to 7-0.

[0068]

[Table 7]

In Table 7, address data DRAM 7
An “M” mark of −0 indicates a bit masked by the mask circuit 24 (all bits are “1”). This mask circuit 2
4, the storage area of the decoder ROM 27 is reduced. The “x” mark indicates that it may be “0” or “1”. The DROM 8-6 indicates a value obtained by subtracting 1 from the length of the decoded image (run length-1). DROM 4 is a run length counter (selector 2) for counting the run length.
8, a register 29 and an adder 30) are used as information for determining whether or not to count. When the point a ₁ is detected, the DROM 4 becomes “0”, and when the point a ₁ is not detected, the DROM 4 becomes “1”. The control unit 1 determines the value of the DROM 4
Is "1", the run length counter is counted. DROM 3-0 indicates the length (run length) of the decoded image. D of decryption result DROM8-6,4-0
The ROM 3-0 is sent to the processing unit 4, and the DROM 8-6 is sent to the adder 3
3 and the processing unit 4, and the DROM 4 is output to the control unit 1.

The adder 33 adds the data RBPP2-0 set in the register 32 and the data DROM8-6 from the decoder ROM 27 in the same manner as in the decompression process.
Unless the first processing of a line starting with black is being performed, one is added to this result. At the start of the black start line, the run length is white 0, and in this case, 1 is not added in the first step. The addition result ABPP2-0 is expressed by the following equation. ABPP2-0 = RBPP2-0 + DROM8
-6 + inversion (FBLKST)

Here, FBLKST is a control signal indicating black start, and at the time of black start, FBLKST becomes valid ("1"). For example, if the RBPP is "111" (=
7) and the DROM 8-6 (run length -1) is "01
0 ”(= 2), then ABPP2−0 =“ 111 ”+“ 001 ”=“ (1) 010 ”

Is obtained. This 4-bit information is
−0 is output as ABPP2-0, and bit 3 (the numerical value in parentheses) is output to the control unit 1 as the control signal COABPP. Based on the value of the control signal COABPP, the control unit 1 determines that one-byte image data has been processed when COABPP is “1”, and causes the register 21 to input new one-byte image data. Also, COABP
If P is "0", the process is continued. Adder 33
Is added to the generation unit 6 and the selector 31.
Sent to In the case of the compression process, the selector 31 selects the data from the processing unit 4, and thus the ABPP2-0 is not used.

At the start of the compression process, the run-length counter first sets the selector 28 to 2556 (= “10
0111111100 "). This value is set in a register 29. Data R from this register 29
The RNLC 11-3 of the NLC 11-0 is sent to the adder 30. In the adder 30, when the decoding result of the decoder ROM 27 indicates that the DROM 4 is "1", the adder 30 subtracts 1 from the RNLC 11-3. This value is sent to the generator 6 and the selector 28 as data ANLC8-0. Selector 28
Selects data composed of ANLC8-0 and RNLC2-0 and sends it to register 29. In this way,
The run length counter counts down in units of 1 byte until a change point is detected.

Next, the processing section 4 will be described with reference to FIG. Omitted because b ₁ Point Detection processing process from the reference line register 41 to the priority encoder 45 is similar to that of decompression. Output data B1DT3-0 of the priority encoder 45 is sent to the adder 58 via the inverting circuit 57. Inverting circuit 57 provided in order to determine in adder 58 the difference in the position of _one point and b ₁ point a, exclusive of the bits of the control signal g and B1 DT3-0 sent from the control unit 1 Perform a logical OR. In the case of the compression processing, the control signal g is valid (“1”),
Each bit of DT3-0 is inverted. Also, the selector 53
Is the data DROM3-0 (data I) from the decryption unit 2.
Is entered. The selector 53 uses the data DROM
3-0 is selected and sent to the adder 58. In the adder 58, an operation is performed as in the following equation. ADLT3-0 = inversion (B1DT3-0) + D
ROM3-0 + 1 = inversion _{(b 1 + 4-a 0} ) +
(A ₁ −a ₀ ) + 1 = a ₁ −b ₁ −4 =
δ-4 Of the output data ADLT3-0 from the adder 58, ADLT2-0 is sent to the generation unit 6 and used for generating a vertical mode codeword.

[0075] Also, data RBPA2-0 from the register 46 indicating the position of a ₀ point is selected by the selector 47 and sent to the adder 49. The selector 48 selects the data DROM 8-6 (data R) from the decoding unit 2 and sends it to the adder 49. The adder 49 performs an operation as in the following equation. A1CM3-0 = RBPA2-0 + DROM8-6 + 1 = a 0 + (a 1 -a 0 -1) + 1 = a 1

As shown in this equation, the adder 49 selects the selector 4
The data from 7 and the data from the selector 48 are added, and 1 is added to the result. The output data A1CM3-0 of the adder 49 is selected by the selector 59,
DBPA2-0 is set in the register 46 and sent to the decoding unit 2. Thus, during the compression process,
Updating position of a ₀ point is performed by the processing unit 4 side. As described above, in the decompression process, the position of the point a ₀ is updated on the decoding unit 2 side.

Next, the generator 6 will be described with reference to FIG. Reference numeral 60 denotes a selector, which inputs data ANLC8-0 (data J) and ABPP2-0 (data M) from the decryption unit 2, and outputs the ANLC8-0 and the ABPP2-0.
Is sent to the register 61.
Of the data RNLG 11-0 held in the register 61, the data RNLG 11-6 of the upper 6 bits is the comparator 6
Sent to 2.

The comparator 62 is used for one-dimensional compression processing.
This is to determine whether the codeword to be generated is a Make-up code or a Terminate code. RNLG11−
6 is compared with “100111”. “100111”
Are the upper 6 bits of “100111111100” (= 2556). If they match in the comparator 62, Te
rminate Indicates the generation of a code. When they match in the comparator 62, the control signal d becomes valid, and this control signal d is sent to the control unit 1. When generating the one-dimensional codeword, the control unit 1
Based on this control signal d, the selector 65
It is determined whether to select LG5-0 or RNLG11-6.

A selector 63 receives data ADLT2-0 (data W) from the processing unit 4 and data EGCD3-0 (data Y) from the control unit 1. In the case of generating a vertical mode codeword, the selector 63 outputs “01” ADL
When T2-0 is selected and a horizontal mode codeword, a pass mode codeword, or the like is generated, "1" EGCD3-0 is selected. The data DGCD4 selected by the selector 63
0 is set in the register 64. EGCD3-0 is, for example, "0001" for horizontal mode codeword generation, and "0010" for pass mode codeword generation.

The selector 65 receives the data RNLG11-0 from the register 61 and the data RGCD from the register 64.
4-0 is input. The selector 65 further includes the control unit 1
, And data L (control signal F2NG) and data Z (control signal DBUG).

The control signal DBUG is a signal indicating whether to generate a code word of either white or black, and is used to distinguish colors when a one-dimensional code word is generated. This control signal D
BUG is "0" for white and "1" for black. When the code word to be generated has 9 bits or more, the control signal F2NG needs to access the encoder ROM 66 twice, and is provided for distinguishing between the first access and the second access.

The control signal F2NG becomes valid ("1") at the time of the second access. Control signal DBUG is bit 8 of address data ERMA8-0 from selector 65.
And the control signal F2NG is bit 0 of ERMA8-0.
Becomes The selection conditions in the selector 65 are as follows. In the case of Terminate code word generation, data composed of DBUG, “0”, RNLG5-0, and F2NG is selected. In the case of Make-up codeword generation, data composed of DBUG, "1", RNLG 11-6, and F2NG is selected. In the case of two-dimensional codeword and special codeword generation, DBUG, "11", RGCD4-0 and F2NG
Select the data consisting of

Output data EROM11- from encoder ROM 66 corresponding to address data ERMA8-0
0 has the following meaning. When the EROM 11 generates one code word of 9 bits or more by dividing it into two times,
It becomes “0” when the second codeword (first word) is generated.
This data EROM11 is sent to the control unit 1.

Thus, control unit 1 determines that a second codeword (second word) needs to be generated, and sets control signal F2NG of address data ERMA8-0 to "1".
Set to. The EROM 11 is “1” when the codeword can be generated by accessing the encoder ROM 66 only once (the codeword length is 8 bits or less) and when the codeword (second word) is generated for the second time. The EROM 10-8 indicates a value obtained by subtracting -1 from the code word length. EROM7-0 indicates a code word. Table 8 shows data EROM 11-0 for each codeword length.

[0085]

[Table 8]

In Table 8, "*" indicates a code word. If the codeword length is 8 bits or less, the codeword is EROM7-0
Is output left justified. If the codeword length is 9 bits or more, the data is output in two parts as shown in the table. For example, when the code word length is 10 bits, the upper 2 bits of the code word are output as the first word, and the remaining 8 bits are output as the second word.

When the address data ERMA8-0 that does not exist in the encoder ROM 66 is input (in the case of an error), the EROM 11-3 is set to "0000".
The control unit 1 checks the EROM 11-8 to determine whether or not an error has occurred.

The EROM 11- output as described above
0, the EROM 7-0 is provided to the rotate shifter 71 via the selector 70, the EROM 11-8 is provided to the adder 69,
The EROM 11 is sent to the control unit 1.

The data RBPQ2-0 from the register 68 is input to the adder 69 together with the EROM 10-8, and the operation result ABPQ2-0 by the adder 69 is as follows. ABPQ2-0 = EROM11-8 + RBPQ2-0 + 1

The operation result ABPQ2-0 is supplied to selector 6
7 In the case of compression processing, the selector 67
Select BPQ2-0 and send to register 68. Data RBPQ2-0 of register 68 is sent to rotate shifter 71 and selector 72.

The rotate shifter 71 receives the EROM 7-0 selected by the selector 70. Rotate shifter 71 sets ECDP0 by the value indicated by EBPQ2-0.
-7 is shifted right, and overflow data is input from the left. For example, ECDP0-7 is "00001"
11 ** ", and RBPQ2-0 is" 011 "(=
In case 3), ECDP0-7 are shifted right by 3 bits,
It becomes "1 ** 00001". This "1 ** 0000
1 "is sent to the selector 72 and the register 73 as data SHTG0-7. The selector 72 has already inputted the codeword EPSL0-7 generated halfway. The selector 72 follows the value indicated by RBPQ2-0 Data on the left side of the indicated value is selected from EPSL0-7, and data on the right side of the indicated value including the indicated value is selected from SHTG0-7, for example, EPSL0-7 is "011 ****".
When SHTG0-7 is “1 ** 00001” and RBPQ2-0 is “011” (= 3), the output data EPCK0-7 from the selector 72 is “0110”.
0001 ". EPCK0-7 is the register 7
3 and the data SHT from the rotate shifter 71.
16-bit data RODT0-15 together with G0-7
Is configured. In the above example, EPCK0-7 is "011
00001 ”and SHTG0-7 is“ 1 ** 000
01 ", RODT0-15 is" 011000
011 ** 00001 ".

[0092] Of the RODTs 0-15, the RODTs 0-7 and 8-15 are sent to the selector 74, respectively. The selector 74 selects RODT8-15 when the codeword data generation is completed in RODT0-7, and selects RODT0-7 when the codeword data generation is in progress in RODT0-7. Whether or not the code word data generation is completed in RODTs 0 to 7 is performed when the bit 3 of the addition result of the adder 69 becomes “1”, and the control unit 1 confirms the completion of the code word data generation.

The control section 1 sends a selection signal to the selector 74. In the above example, first, RBPQ2-0 is “011” (= 3), and the decryption result ECDP
Since 0-7 is “0000011 **” (code word length = “6”), the operation result ABPQ2-0 of the adder 69 is “(1) 001” (= 1). Bit 3 of the addition result
Has become “1”, the selector 74 sets the RODT 8-1.
Select 5. Data EPSL0- from selector 74
7 is sent to the selector 72, and the next output SHTG0
-7 is synthesized. The code words are synthesized in this way. In the register 75, RODT0-7 are set, and
When the codeword data generation is completed at T0-7, it is output to the outside as data ROUT0-7. The compression process proceeds as described above.

Next, the change point detecting circuit 44 of the processing unit 4 will be described.
Will be described in detail with reference to FIG. Basically, in order to find a transition point where white → black (0 → 1), each bit of the data DREN0-14 from the inversion circuit 43 and each bit of the DREN0-14 are inverted to the right one bit at a time. After taking the logical product with each shifted bit, in the processing of the end of the line, the negative sum with the data DNDP0-10 for supplementing the virtual change point is provided on the right side of the end point. . In addition to this basic configuration,
Special circuits have been added to accommodate the processing in the first step of the line and the processing in the first step of the run.
The processing in the first step of the line is the first one of the line.
Processing of bytes.

As shown in FIG. 6, the byte boundary may not coincide with the left end of the line depending on how the input data is given. Then, it may b ₁ point comes directly above the a ₀ point. In such a case, in order to b ₁ point is detected as a change point, the previous bit must become "0". This processing is performed by a NAND gate that takes the negative product of DREN2 and the control signal “inversion (first line)”. In the processing of the first step of the line, the control signal “inversion (first of the line)” becomes “0”. Therefore,
With this NAND gate, DREN2 is always treated as "0" in the processing in the first step of the line. In other words, it detects the DREC3 as ₁ point b.

The process in the first step of the run is a process of the first one byte after a change point is detected and a process of a new run is started. The process in the first step of the run, as shown in FIG. 7, since b ₁ points to the right from a _0-point, the left change point from a _0-point should not be detected. The control signal "inversion (first of run)" performs such processing. This control signal “inversion (first of run)”
Is "0" in the processing in the first step of the run. Therefore, this control signal is used as an inverted signal of DREN0 and DREN0.
The output data DREC1 always becomes "1" by inputting to the NAND gate which takes the negative product with "1". Similarly, by inputting this control signal to the NAND gate that takes the negative product of the inverted signal of DREN1 and DREN2, the output data DREC2 always becomes "1".

In the case of the processing in the first step of the line, it is also the processing in the first step of the run. In such a case, it must be detected DREC3 as ₁ point b. However, if the processing is not the processing in the first step of the line but simply the processing in the first step of the line, D
REC3 should not be detected as a change point. Such processing is performed by a NOT gate for inverting the control signal “inversion (first line)” and the logical sum of an output from the NOT gate and the control signal inversion “inversion (first run)”. O
R gate. The output of the OR gate is input to a NAND gate that outputs DREC3. In the case of the processing in the first step of the line and the processing in the first step of the run, the output of the OR gate becomes “1” and the DRE
It is possible to detect the C3 as ₁ point b. On the other hand, if the processing is not the processing in the first step of the line but simply the processing in the first step of the run, the output of the OR gate is “0”.
And DREC3 is not detected as a change point.

As described above, the data DNDP0-10 is data for supplementing a virtual change point one bit to the right of the end point. Normally, each bit of the DNDP0-10 is "0". When processing the last data of the line, the data DND
Of P0-10, only the bit located one bit to the right of the terminal point is "1". Therefore, when each bit data output from the AND gate and the respective bits of DNDP0-10 are calculated as a negative sum, a virtual change point is supplemented to the right of the end point by one bit.

In the data DREN0-14, a change point candidate is detected through such a circuit. DREC1-1
In 4, the change point candidate is “0”, and otherwise, it is “1”. Data DREC1-1 indicating a change point candidate
4 is input to the priority encoder 45. The priority encoder 45 detects a change point candidate existing on the leftmost side of the DREC 1-14, and outputs data B1DT3-0 indicating the bit position. FIG. 8 is a diagram showing a circuit that controls the inverting circuit 23 in the decoding unit 2 shown in FIG. 2 and the inverting circuit 43 in the processing unit 4 shown in FIG. In the figure, reference numeral 80 denotes a flip-flop indicating that black run processing is being performed. The Q output FBLKP signal is used in each unit as a signal indicating that black run processing is being performed.

[0100] flip-flop 81 is the same structure as the flip-flop 80, when encoding the passcode inverts after b ₁ out inspections, b ₁ point detection circuit b ₂
FBLKC to be used for point detection is output. AN
The D gate 82 receives a signal that becomes “0” at the time of decompression from k, and sends a signal that becomes “1” to the inverting circuit 23 of the decoding unit 2 only during the black run compression processing.

The AND gate 83 outputs a signal CSWBF which is output before finishing the processing of one line and before starting the processing of the next line.
A, the flip-flop 8 at the left end processing of each line.
Set 0 to 0.

The AND gates 84 to 86 are used for holding the state of the flip-flop 80, loading the FBLKD signal to the flip-flop 80, and inverting the state of the flip-flop 80, respectively. The load from the FBLKD by the AND gate 85 is used at the time of decompression, and at the time of compression, a signal is sent to i at the end of the run to invert the state.

When there is a possibility of encoding into a pass code, the AND gate 87 sets the flip-flop 81 in the opposite state to the flip-flop 80 in response to the signal j when the point b1 is detected. The output a of the flip-flop 81 is the processing unit 4
Because of being sent to the inverting circuit 43, thereby, b ₂
Point detection becomes possible. FIG. 9 is a diagram showing a state transition of the control unit 1 corresponding to the processing within the broken line in the flowchart of FIG.

The state 90 is a state in which the points a ₁ and b ₁ are detected. If none of the points a ₁ and b ₁ is found,
Shift in the register (RDTI) 21 of the decoding unit 2;
Then, the shift in the register (PREF) 41 of the processing unit 4 is performed, and the transition condition 100 is satisfied, and this state 90 is repeated. a _1-point, if any is detected b ₁ point goes to state 91.

The state 91 is a state in which the encoding mode is determined based on the correlation between the points a ₁ and b _1. First, when the encoding can be performed in the vertical mode, the generation of the vertical mode code is instructed. Return to If it is found that the encoding must be performed in the horizontal mode, the generation of the horizontal mode code is similarly instructed and the process returns to the state 90. If that could be encoded in pass mode places the position of b ₁ point in the register (RBPA) 46 of the processing unit 4 with (thereby the right change point detection target than b ₁ point), In order to invert the output FBLKC of the flip-flop 81 of FIG. 8, the j signal is applied to the control circuit 11 shown in FIG.
Move to

The state 92 is a state in which the points a ₁ and b ₂ are detected. This state is maintained until the points a ₁ and b ₂ are found, and the data shift is repeated as in the state 90. At this time, since the RBPA 46 and the FBLKC have been updated as described above, the processing unit 4 operates to detect the point b ₂ instead of the point b ₁ .

The state 93 is a state in which encoding is performed in the pass mode or the horizontal mode, and has a function similar to the state 91.
When encoding is performed in the pass mode, the control circuit 1 shown in FIG.
The i-signal for 1 is not output, and the next process is performed as the same run.

Next, the operation of the control section 1 will be described with reference to FIG. Also in the present embodiment, the initialization process for each line is performed as in the first three steps in the flowchart of FIG.
Here, the image data of the reference line and the image data of the encoding line are simultaneously shifted until both or _{one of the} points a ₁ and b ₁ is found. When a _1-point or b ₁ point is detected moves to state 91, it is determined coding mode. If the encoding can be performed in the vertical mode and the horizontal mode, it is determined that the encoding is performed in each mode regardless of where the point b ₂ is, and an instruction is issued to the generation unit subsequencer 5.

At this time, since the transition condition 102 is satisfied, the process returns to the state 90 again. If it is determined in state 91 that encoding cannot be performed in either the vertical mode or the horizontal mode, the control unit 1
8 is energized to the control circuit 11 shown in FIG. 8 and only the flip-flop 81 inverts the state. (at the same time,
As with vertical and horizontal mode encoding,
The lower 3 bits of the bit address of b ₁ point sought to AB1A in Figure 3 the register 46 add as RBPA2-0. )

[0110] Thus, in the next state change point detection circuit 44 of FIG. 3, acts as from b ₁ point for detecting a change point in the opposite direction of the right side, but the other points as the run of the same color Processing can be continued.

[0111] In the next state, in the state 92, the detection of b ₂ points or a _1-point. If either or both of the change points are detected, the process goes to the state 93. If the encoding can be performed in the pass mode, the encoding is performed in the pass mode. Otherwise, the encoding is performed in the horizontal mode. In the case of encoding in the pass mode, the i signal of FIG. 8 is not output, and the next processing is performed as a run of the same color. The j signal is output, the flip-flop 81 is inverted again, and the next state is output. in to be able to b ₁ point detection again. Next, the process returns to the state 90.

In the case of encoding in the horizontal mode, an i signal is output to the control circuit 11 (j signal is not output) so that a run of an opposite color can be processed. In this case as well, it is clear from the control circuit 11 shown in FIG. 8 that the flip-flop 81 is in the same state as the flip-flop 80.

[0113] b not have this to, b _2-point detection circuit
_The control circuit 11 shown in FIG.
And processing by the procedure shown in FIG.
It can be encoded by a vertical mode code that occupies most of the code data. At this time, only if b ₁ point and not be vertical mode coding is detected, since the newly b ₂ point detection, even require extra machine cycles for b _2-point detection, as a whole The encoding process can be performed at high speed.

In the above embodiment, as shown in FIG. 1, the processing unit 4 and the generation unit 6 are separated, and perform a pipeline type parallel processing. Therefore, the control unit 1
Instructs the generation unit sub-sequencer 5 to generate a code. However, the present invention can also be applied to an encoder / decoder (codec) in which the processing unit 4 and the generation unit 6 are integrated. In that case, the control unit 1 “generates” the code.

As shown in FIG. 8, the two inverting circuits 23 and 43 are individually controlled by the two flip-flops 80 and 81. However, as shown in FIG.
It is also conceivable to use the EXOR circuit 121 instead of 1. In this case, a signal that is turned on in the states 105 and 106 in FIG. 9 and turned off in other states may be used as a signal.

[0116]

As described above in detail, according to the present invention, the b ₁ point detecting circuit for detecting the b ₁ point in the compression processing is b ₂
Since it is also used for point detection, the b _{2 point} detection circuit can be eliminated. Further, since the compression processing is performed with priority given to the vertical character or horizontal mode, it is possible to avoid compression by unnecessary passcodes and to increase the data compression ratio.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a binary data compression / decompression processing device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing in detail a configuration of a decoding unit 2 shown in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a processing unit 4 shown in FIG. 1 in detail.

FIG. 4 is a circuit diagram showing a configuration of a generation unit 6 shown in FIG. 1 in detail.

FIG. 5 is a circuit diagram showing in detail a configuration of a change point detection circuit 44 shown in FIG. 3;

FIG. 6 is a diagram showing an example of image data in a process of a first step of a line.

FIG. 7 is a view showing an example of image data in a process of a first step of a run.

FIG. 8 is a control circuit 1 for controlling the inverting circuits 23 and 43.
1 is a circuit diagram showing the configuration of FIG.

FIG. 9 is a diagram showing a state transition of the control unit 1.

FIG. 10 is a circuit diagram showing in detail another configuration of the control circuit 11 for controlling the inverting circuits 23 and 43.

FIG. 11 is a flowchart showing the procedure of a compression process according to the CCITT recommendation.

FIG. 12 is a diagram showing an example of encoding according to the flowchart shown in FIG. 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control part, 2 ... Decoding part, 3 ... Decoding part Subsequencer,
4 processing unit, 5 generation unit sub-sequencer, 6 generation unit,
7 buffer unit, 8 reference line image buffer memory, 9 input bus, 10 output bus, 11 control circuit,
21: register (RDTI), 22: barrel shifter, 2
3, 43, 57: inversion circuit, 24: mask generation circuit, 2
5. Register (RPAT), 26, 28, 31, 47,
48, 53, 54, 59, 63, 65, 67, 70, 7
2, 74 ... selector, 27 ... decoder ROM (DRO
M), 29 ... Register (RNLC), 30, 33, 4
9, 52, 56, 58, 69 ... adder, 32 ... register (RBPP), 34, 62 ... comparator, 41 ... register (PREF), 42 ... barrel shifter, 44 ... change point detection circuit, 45 ... priority encoder, 46: register (RBPA), 61: register (RNLG), 64:
Register (RGCD), 66 ... Encoder ROM (ER
OM), 68: register (RBPQ), 71: rotated shifter, 73: register (RODT), 80, 81 ...
Flip-flops, 82 to 87 ... AND gate circuit, 1
20: an inverter circuit; 121: an EXOR circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/41-1/419 H03M 7/30

Claims (1)

(57) [Claims] 1. A binary image compression processing apparatus for compressing a binary image by a two-dimensional encoding method that handles a vertical mode code, a pass mode code, and a horizontal mode code, wherein an image of an encoding line to be compressed is provided. First change point detection means for detecting a predetermined color change point from the inside; second change point detection means for detecting a predetermined color change point from an image of a reference line corresponding to the encoding line; A first control means for controlling a direction of a color change to be detected by the change point detecting means of the first and second control means for controlling a direction of a color change to be detected by the second change point detecting means; When a change point is detected by at least one of the first and second change point detection means, the relative positional relationship between the change point of the coding line and the change point of the reference line is | (coding line
Change point) × (reference line change point) | ≦ 3
Vertical mode when added, horizontal when the above conditions are not met
A first step of generating a code in a vertical mode or a horizontal mode, and determining that generation of a code in a mode is possible, and when the code cannot be generated in the first step,
Wherein the state of the first control means maintaining the same state as the first step, the state of the second control means performs the first step <br/> flop opposite state to change point detection, change 2. A binary image compression processing apparatus , wherein when a point is detected, a compression process is performed in accordance with a second step of generating a pass mode or horizontal mode code.