JPS60140979A - Parallel processor for encoding and decoding of picture signal - Google Patents

Abstract

PURPOSE:To operate plural MH encoding and MH decoding circuits on a parallel bus in parallel at every scan by adding the specific number of continuous zero codes to a partition of one scan of a MH code data series to detect said codes and by setting it to a partition of MH code data at every scan on a parallel bus. CONSTITUTION:Zero codes of 12 bits and those of 20 bits are added to a eight- bit bus and a 16-bit bus, respectively. A bus data zero detection circuit 7 detects all zeros of bus data and transmits a detection signal S1. Code data transferred to a parallel bus 8 from a storage medium 9 are inputted to a code data distribution circuit 10 as well as the bus data zero detection circuit 7. Whenever the detection signal S1 of the circuit 7 turns on, the circuit 10 outputs code data at every scan to MH decoding circuits 11, 12 and 13 cyclically and sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to MH encoding and decoding of image signals.
The present invention relates to an encoding and decoding device that includes a plurality of encoding circuits and decoding circuits and is capable of performing parallel processing.

Conventional configurations and their problems A large-capacity storage medium is required to store image signals, and conventionally, image signals have been compressed using some kind of encoding method and stored as encoded data. Semiconductor memories, magnetic disks, optical disks, etc. are used as storage media for this purpose, and the transfer of encoded data to and from the storage media is faster than facsimile communication (37°' (approximately 9.6 bits/second)). and is done at high speed. Therefore, it is necessary to speed up the processing of encoding from an image signal to code data and decoding from code data to an image signal.

The MR (Modified Hoffman) encoding method recommended by the CCITT (International Telegraph and Telephone Consultative Committee) is a typical encoding method for image signals. , is a method that detects the change point of the image signal and uses the Ml code corresponding to the run length and whether the run is black or white.・Termination code corresponding to length and 64 shown in Table 2
There is a make-up code corresponding to the run length of every 64 runs from 0 to 266°.Also, a line synchronization code (EOL: 000000000001) is inserted every scan of the kH code string.

Table 1 Table 2 51'' In a conventional image signal encoding and decoding device, the encoding circuit 22 and decoding circuit 23 that encode and decode the storage medium 21 and the MH code are generally As shown in FIG. 1, it is connected to a parallel bus 24, through which MH code data is transferred from the encoding circuit to the storage medium and from the storage medium to the decoding circuit.

In such a configuration in which MH code data is transferred through a parallel bus, in order to speed up the encoding and decoding processes, multiple encoding circuits and decoding circuits are connected to the parallel bus to perform one scan. If you try to perform parallel processing every time, as shown in the MF code data string shown in Synthesis of MH code data for each scan output from each encoding circuit and M) for each scan input to each decoding circuit.
A problem arises in that I code data cannot be decomposed.

This is because the MH code has a variable length, so the code data length for 16° scanning is not an integral multiple of the data width of the parallel bus.

Purpose of the Invention The present invention has been made to solve the above-mentioned problems, and is capable of operating a plurality of MH encoding circuits and MH decoding circuits in parallel on a parallel bus for each scan. An object of the present invention is to provide a parallel processing device for image signal encoding and decoding.

Structure of the Invention The present invention focuses on the fact that consecutive 0 codes, including the line synchronization code, on the MH code data string are 14 bits or less. In the case of bits, the bus data on the MH code data string does not have all 0s consecutively in the case of an 8-bit bus, and does not exist in the case of a 16-bit bus. Separation of one scan (
If 12 bits (12 bits for an 8-bit bus, 20 bits (20 bits) for a 16-bit bus) of consecutive 0 codes are added to the front of the line synchronization code (before the line synchronization code), the condition for the bus data to be 0 for all 7'-bits is 8 bits.・For buses, twice in a row,
Since it occurs once on a 16-bit bus, detecting this condition reduces the MI for each scan on the parallel bus.
(This is used as a delimiter for coded data, and is intended to achieve the above purpose.

That is, the parallel processing device for image signal encoding and decoding of the present invention inputs an image signal obtained by scanning an original image from an input terminal and sequentially cyclically distributes it to an MH encoding circuit for each scan. Signal distribution circuit, line memory and Mu
A plurality of MH encoding circuits, which are composed of an encoding processing circuit and a code data buffer, convert the distributed image signals into MH code data, and a bus data 0 detection circuit that converts the code data of each MH encoding circuit into MH code data. A code data selection circuit that sequentially cyclically selects and outputs the selected data to the parallel bus every scan based on the detection signal of the MH code, a parallel bus that transfers the MH code data, and a bus that detects all 0s in the bus data.
A data O detection circuit, a storage medium that stores the Ml code data transferred by the parallel bus, and a detection signal of the bus data 0 detection circuit that stores the MH code code data transferred from the storage medium on the parallel bus. A plurality of code data distribution circuits that sequentially and cyclically distribute the MH code data for each scan, a line memory, a kHz decoding processing circuit, and a code data buffer decode the distributed MH code data into image signals. M) 19 encoding circuit, and an image signal selection circuit that sequentially and cyclically selects the image signals from each B&H decoding circuit for each scan and outputs the selected image signals from the output terminal.

The parallel processing of image signal encoding and decoding by the apparatus of the present invention is performed by dividing the encoded data string generated in the Ml encoding circuit into an arbitrary length corresponding to the data width of the parallel bus. a step of adding a 0 code of 0, a step of detecting the break of one scan on the code data string by determining that all the data on the parallel bus is 0, and a step of detecting the break of one scan on the code data string; One of the MH encoding circuits or MH decoding circuits is connected in parallel.
It consists of a step of sequentially cyclically connecting to the bus, and a step of sequentially cyclically connecting the image signal to one of the plurality of 9-base MH encoding circuits or MW decoding circuits for each scan.

DESCRIPTION OF EMBODIMENTS FIGS. 3 and 4 show an image signal encoding processing device and a decoding processing device according to an embodiment of the present invention. In the figure, 1 is an input terminal for inputting an image signal, and 2 is an image signal distribution circuit that sequentially and cyclically distributes the input image signal for each scan. Reference numeral 3 denotes an MH encoding circuit that converts the image signal distributed by the image signal distribution circuit 2 into MH code data, and is composed of a line memory 3a, an MH code processing circuit 3b, and a code data buffer 3C. . 4 and 6 are also 3 above.
A plurality of MH encoding circuits 3.
4.6 are arranged in parallel. 6 is a code data selection circuit that sequentially cyclically selects and outputs the code data of each VH encoding circuit for each scan, and 7 detects all O's of the bus data and transmits a detection signal S1. bus data 0
A detection circuit, 8 is a parallel bus for transferring MH code data, and 10.t and 9 are storage media for storing MH code data transferred by the parallel bus 8. 1o is a code data distribution circuit that sequentially and cyclically distributes the MH code data on the parallel bus 8 for each scan. 011 is an MH decoding circuit that decodes the Ml code data distributed by the code data distribution circuit into an image signal. The circuit is composed of a line memory 11a, an MH decoding processing circuit 11b, and a code data buffer 110. 12.13 is also the same MH decoding circuit as 11 above, and a plurality of MH decoding circuits 11, 12 and 13 are arranged in parallel. 14 is an image signal selection circuit that sequentially selects and outputs image signals from each Ml decoding circuit for each scan; 15;
is an output terminal that outputs an image signal.

Next, the operation of parallel processing of image signal encoding and decoding in this apparatus will be explained. For convenience of explanation, it is assumed that the data width of the parallel bus is 16 bits, and that there are three MH encoding circuits and three MH decoding circuits.

First, the encoding operation will be explained with reference to FIG. An image signal obtained by scanning an original image is input to an image signal distribution circuit 2 through an input terminal 1. The circuit 2 has an image signal counting function, and divides the image signal into scans of a fixed length, and sequentially and cyclically outputs the divided image signals to the MH encoding circuit 3t 4+ 5. The image signal for one scan input to the circuit 3 enters the line memory 3a, where it is encoded according to the MH encoding method.M)! It is converted into parallel MH code data by the encoding processing circuit 3b and input to the code data buffer 3C. Note that the MH encoding processing circuit 3
b has a function of outputting a 0 code string of 2° bits corresponding to the 16-bit data width of the parallel bus after outputting the code data of one scan. In the circuits 4 and 5, the same operation as described above is performed on the input image signal. Circuit 3.4
．． 5 parallel code data outputs are input to a code data selection circuit 6. Each time the detection signal S1 of the bus data 0 detection circuit 7 is turned on, the circuit 6 operates the circuit 3. 4. 5
The encoded data outputs are sequentially and cyclically selected and outputted to the parallel bus 8. The code data output on the parallel bus 8 is input to the circuit 7, and is transferred to the storage medium 9 and stored therein. The bus data 0 detection circuit 7 has a function of detecting all 0s in the bus data on the parallel bus B, and as mentioned above, on the MH code data string, consecutive Q codes are 14 bits or more. Therefore, the detection signal S1 of the circuit 7 turns on only when the O code added after one scan of code data is output onto the parallel bus 8. Therefore, code data is stored on the storage medium 9 in accordance with the scanning order of the input image signals.

Next, the decoding operation will be explained according to FIG. As explained in the above encoding operation, code data is stored in the storage medium 9 in scanning order separated by consecutive 0 codes that set the parallel bus 8 to all 0s. The code data transferred from the storage medium 9 onto the parallel bus 8 is input to the bus data 0 detection circuit 7 and also to the code data distribution circuit 10. The circuit 10 outputs 13/13 signals every time the detection signal S1 of the circuit 7 turns on, that is, every scan
. . . Code data is sequentially and cyclically outputted to the MH decoding circuits 11, 12, and 13. The encoded data input to the circuit 11 passes through the encoded data buffer 11C'i and is then transferred to M
The image signal is decoded by the MH decoding processing circuit 11b that performs decoding processing according to the H encoding method, and the image signal is
will be entered in the next step. Note that in the MH decoding processing circuit 11b, the 0 code connected after the MH code data is filtered (FI
LL) - Ignore it as a bit and restart the decoding process for the next scan from the next line synchronization code. Circuit 12.13
Similar operations are performed on input code data. The image signal output of the circuit 11'+12°13 is input to the image signal selection circuit 14. The circuit 14 has an image signal counting function, and the circuit 11.1 is counted every scan of a certain length.
2.13 image signal outputs are sequentially and cyclically selected and output to the image signal output terminal 16. Therefore, the image signal from the terminal 15 is outputted in the order of code data for each scan on the storage medium 9.

To help understand the above explanation, Fig. 5 shows the encoded 14°
FIG. 6 shows the timing chart of the image signal, the operation of each 11H encoding circuit, the encoded data on the parallel bus 8, and the signal S1 in the decoding operation. The operation of each MH decoding circuit and the timing diagram of the image signal are shown.

Effects of the Invention The present invention is configured as described above, and includes a plurality of MHs.
Since the encoding circuit and the MH decoding circuit can be operated in parallel for each scan of the image signal, it is possible to speed up the encoding and decoding processing for continuous image signals. It can be effectively applied to

[Brief explanation of drawings]

Figure 1 is a block diagram showing the connection state between the conventional MH encoding circuit, MH decoding circuit, and storage medium, and Figure 2 is
A diagram explaining the relationship between H code data and the data width of the parallel bus, FIG. 3 is a block diagram of an encoding device according to an embodiment of the present invention, and FIG. 4 is a decoding diagram according to an embodiment of the invention. Apparatus 0 Block Diagram Page 15 FIG. 6 is a timing diagram of the encoding operation, and FIG. 6 is a timing diagram of the decoding operation. 1... Image signal input terminal, 2... Image signal distribution circuit, 3, 4.5... MH encoding circuit,
6... Code data selection circuit, A... Bus data ○ detection circuit, 8... Parallel medium bus, 9... Memory 'JX body, 10 . . . Code data distribution circuit, 14 . . . Image signal selection circuit, 1
6... Image signal output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure J Figure 2■ - Sewing diagram -1

Claims (1)

[Claims] An image signal distribution circuit that inputs multiple image signals obtained by scanning an original image through input terminals and sequentially and cyclically distributes them to a Modified Hoffman (hereinafter referred to as MH) encoding circuit for each scan. and a plurality of MH encoding circuits that convert the distributed image signals into MH code data, and the code data of each MH encoding circuit is sequentially cyclically processed every scan by the detection signal of the bus data 0 detection circuit. A code data selection circuit that selects and outputs M)l code data to the parallel bus, a bus data 0 detection circuit that detects all o of the bus data, and A storage medium that stores the transferred M)l code data, and the Ml code data transferred from the storage medium on the parallel bus are sequentially and cyclically distributed for each scan by the detection signal of the bus data O detection circuit. A plurality of MH decoding circuits that decode the distributed MH code data into image signals, and each MH A parallel processing device for image signal encoding and decoding, comprising an image signal selection circuit that sequentially cyclically selects image signals from the decoding circuit for each scan and outputs the selected image signals from an output terminal.