JPH04123670A - Equal speed read corresponding facsimile one-dimensional encoder - Google Patents

Abstract

PURPOSE:To execute the encoding without providing an image memory of a large capacity by constituting the encoder by providing an FIFO memory, a variation point detecting circuit, a run-length converting circuit, a code table ROM, and a parallel/serial converting circuit. CONSTITUTION:When an image signal is written in an FIFO memory 11, a variation point detecting circuit 12 retrieves and detects a variation point, while reading out its image, and transfers a color/run-length signal to a run-length converting circuit 14. Subsequently, a color signal, and a run-length signal are transferred to a ROM 15, as it is, and by dividing it into a multiple part of 64 and the part of <=63 and dividing it into two times, respectively, a code to which a rake-up/terminating discriminating signal is given and code length are outputted, and a code signal converted to serial data by a parallel/serial converting circuit 16 is outputted. Even if any image code is inputted, an encoding processing of one line can be executed within a prescribed time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an encoder for a facsimile machine, and in particular, to an encoder for a facsimile machine, and in particular to a binary image signal for one page that is continuously input in response to constant speed reading. The present invention relates to a facsimile one-dimensional encoder that performs high-speed encoding processing without storing information in line memory or page memory.

[Conventional technology]

Facsimile machines that use a line-by-line controlled reading method that monitors the operating status of the encoder and reads the document line by line when image signals can be transferred have been widely used. . Recently, facsimile machines have been put into practical use that use a constant speed reading method that continuously reads one page of a document at a high constant speed without such reading control.

FIG. 2 shows an example of the configuration of a conventional facsimile machine using a constant speed reading method. In the document reading section 21, image data for one page read at a high constant speed is temporarily stored in the image memory 22. The encoder 23 encodes this image data while reading it from the image memory line by line, and the output code is transferred to the code memory 24.

This code memory absorbs differences in line-by-line coding processing speed depending on the input image, and reduces communication time by storing codes for one page or more and then transmitting them continuously. It is for. Finally, communication department 2
5 outputs the code read from the code memory to the line.

[Problem to be solved by the invention]

Image signals read and transferred using the constant speed reading method,
When it comes to be required to encode any image signal at a high processing speed of about 2 ms/line, conventional one-dimensional encoders can no longer cope with the need.

Therefore, in a facsimile machine that adopts such a constant speed reading method, it must be realized by using a large capacity memory that can store image data for one page or more of a document. Furthermore, when such a device is realized using memory, there is a drawback that the price of the device increases due to the increase in the number of parts and the number of manufacturing steps. Therefore, it has been extremely difficult to realize a low-cost device that uses this constant-speed reading method.

[Means to solve the problem]

In order to solve the above-mentioned problems and realize a constant-speed processing encoder that is compatible with the constant-speed reading method, the encoder of the present invention has a first-in first-out (FO) memory, a change point detection circuit, and a run length. Conversion circuit, code table R
It has an OM and a parallel/serial conversion circuit.

〔Example〕

Next, the one-dimensional encoder of the present invention will be explained using the drawings.

FIG. 1 is a block diagram of a one-dimensional encoder according to the present invention.

First, the constituent elements, their respective functions, and their mutual relationships will be explained. The image signal input in synchronization with the external image transfer lock is synchronized with the internal clock and then F
The data is written to the IFO memory 11. FIFO memory 11
can store 16 pixels of image data, and buffers the difference in processing speed between codes due to the difference in code length. Writing and reading of image data can be performed independently.

The changing point detection circuit 12 detects a pixel (changing point) whose color is different from the immediately preceding pixel in the pixel signal string while reading the pixel signal from the FIFO memory 11.

The run length calculation circuit 13 counts the continuous length (run length) of black pixels or white pixels read from the FO memory 11. A 12-bit color/run-length signal, which is a combination of a 1-bit color signal representing whether the run-length color is white or black and an 11-bit color signal representing the run length, is transferred to the run-length conversion circuit 14 at the next stage. Ru. At this time, the maximum line length is 2048 pixels. The run-length conversion circuit 14 decomposes the input color/run-length signal into a color signal as it is, a run-length signal into a multiple of 64 part and a part below 63, and outputs the divided signal twice. However, when the run length is 63 or less, there is no code corresponding to the 640 multiple part. The multiple part of 64 corresponds to the make-up code, and the part below 63 corresponds to the terminating code.

The decomposed signal is a 1-bit signal that identifies whether it is a make-up code or a terminating code, and a 1-bit signal that is calculated by dividing the run length by 64 in the case of a make-up code.
When it is a terminating code, it is composed of a 6-bit signal representing the run length itself. That is, the output of the run-length conversion circuit 14 is an intermediate code consisting of a total of 8 bits, including a 1-bit color signal, a 1-bit make-up/terminating identification signal, and a 6-bit run-length signal. The code table ROM 15 uses the intermediate code itself as an input address, and complies with CCITT recommendation T.
The make-up codes or terminating codes based on the code 4 and their code lengths are output. The code is a signal of 13 bits and the code length is 4 bits. These are transferred to the parallel/serial conversion circuit 16. The parallel/serial conversion circuit 16 converts the 13-bit code data into valid data by the number of bits given by the code length, and outputs it serially.

Next, the operation of this encoder will be explained. When the image signal is written to the FIFO memory II, the change point detection circuit 1
Step 2 searches for changing points while reading out the image. When the change point detection circuit 12 detects a change point, the color/run length signal is transferred to the run length conversion circuit 14. If white is defined as 0° and black as 1° as a color signal, then the color/run length signal of the white line 150 is, for example, as follows. This signal is converted into (1
) White run 128 and (2) White run 22, which are divided into two signals and transferred to the code table ROM 15 in two parts. As a makeup/terminating identification signal,
Set the make-up code to ``l'' and set the terminating code to 0.
′, this signal becomes White Make-up Run 128 (128 Muro 4 = 2) White Termination Run 22. The code table ROM 15 outputs the corresponding code and code length. Finally, the code signal converted into serial data by the parallel/serial conversion circuit 16 is output.

In this system configuration, the relationship between the image transfer lock speed and the internal clock speed is as follows. The maximum speed of image transfer locking is limited by the processing speed when the amount of code generated for an input image is the largest. This is a case where one white pixel and one black pixel are alternately consecutive. The code amount of the white run 1 and the black run 1 is 6 bits and 3 bits, respectively, and processing of these two pixels requires 11 internal clocks.

Therefore, the speed of the internal clock is 5.5 of the image transfer lock.
5 times more is required.

〔Effect of the invention〕

Since the present invention is configured as described above, it has the advantage that no matter what image signal is input, one line can be encoded within a certain period of time.

As a result, it is possible to encode image signals read using the constant speed reading method without using an image memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a facsimile one-dimensional encoder according to the present invention, and FIG. 2 is a block diagram of a facsimile apparatus using a conventional constant speed reading method. 11... FIFO memory, 12... Change point detection circuit, 13... Run length calculation circuit, 14... Run length conversion circuit, 15...
... code table ROM, 16 ... parallel/serial conversion circuit, 21 ... document reading section, 22 ... image memory, ... encoder, 24... code memory, 25... communication section.

Claims (1)

[Claims] A FIFO (first-in, first-out) memory that receives a binary image signal string serially output from the document reading section of a facsimile machine and can write and read the binary image signal independently; A change point detection means for detecting a pixel having a different color from the previous pixel, a run length calculation means for counting the length (run length) of consecutive white pixels or black pixels, and a run length calculation means for calculating the run length of 64 consecutive white pixels or black pixels. A run-length conversion means that decomposes into a multiple part and a part of 63 or less and outputs it as an intermediate code, and inputs the output of the run-length conversion means to convert make-up codes or terminating codes based on CCITT recommendation T4 and their code lengths. and a parallel/serial conversion means that serially outputs the output code of the code table ROM as code data of the number of bits given by the output code length, and converts the code corresponding to the image signal sequence. A facsimile one-dimensional encoder that outputs a signal sequence.