JPS59156073A - Data decoding device - Google Patents

Abstract

PURPOSE:To execute decoding of one MH code within one system clock, and to realize a high speed decoder of an MH code by processing a picture signal train encoded by an exclusive hardware with a prescribed number of bits each, to obtain a decoded data. CONSTITUTION:Plural pieces (14 pieces) of tri-state buffers of 13-bits are prepared and constituted so that its input line is connected to a signal line 14 by shifting by one bit each, and the output line is wire ORed to connect. When one piece in its tri-state buffer group is selected, an optional data shift can be executed. A run-length decoding ROM is a converting table constituted so that an MH code becomes an address and a run-length corresponding to it becomes an output data, the run-length of an output of the ROM is counted by a run-length counter 6, and a black or white bit number and a white bit number are outputted. 7 denotes a code length decoding ROM, and the MH code becomes an address. Code length 17 is added to an offset register 9 through an adder group 8.

Description

[Detailed description of the invention]

The present invention relates to a data decoding device for image files or facsimile machines. Especially Modified Eight Man (M-
H) It is effective for high-speed decoding of image signals that have been run-length encoded and stored or transmitted. Conventionally, this type of apparatus has the disadvantage that the processing speed of decoding and conversion is not constant, and therefore requires a printer apparatus with a variable sub-scanning speed. For this reason, if a high-speed electrostatic printer with a constant sub-scanning speed is used, it is necessary to expand the buffer memory for -H1 pages. Furthermore, since the process was performed using software using a microprocessor, there was a limit to how high the speed could be increased. The present invention is designed to achieve high speed conversion and to be able to convert one code word in about several hundred nanoseconds. Also, it is configured by hardware. Furthermore, the sub-scanning speed is constant and it is possible to connect directly to a high-speed printer. Therefore, real-time conversion is possible, and the buffer memory for one page, which was conventionally required, can be eliminated. Therefore, it has become possible to quickly print out small-sized image information files. Next, the present invention will be explained in detail based on the illustrated embodiments. FIG. 1 is a schematic block diagram of a decoder for MH codes according to the present invention. In the figure, reference numeral 1 denotes a screen memory in which an MH encoded image signal is stored. 1 is an image file memory. The data from here is output in 24-bit parallel or converted to that format and output. 2 is a read address counter for giving a read address of the screen memory 1; This is a 6-wire parallel/serial converter. The output data line 0'r& from screen memory 1 is connected to 2 to increase the relative speed.
It has a 4-bit configuration. 3 is a parallel-to-serial converter for dividing 24-bit data into three 8-bit data and serially converting each 8-bit data. Therefore, this conversion circuit 6 includes a hexadecimal counter 101 (FIG. 2) for incrementing the read address counter 2 by one after shifting 8-bit data three times. Therefore, it is possible to prevent a time delay caused by converting 24 bits as they are using a shift register. 4 is a tri-state buffer group, which stores up to 16 consecutive pieces of data from the serially converted data 14, starting with the data with the offset value 15 indicated by the offset register 9.
This is for inputting data into the run length decode ROM 5 and code length decode ROM 7. Here, the offset value is data indicating from which position the MH code is extracted from the real data DO""D25 that has been parallel-shifted every 8 bits. Therefore, specifically, a plurality of 13-bit tri-state buffers (14) are prepared, the input lines of which are shifted by 1 bit and connected to the signal line 14, and the output lines are configured by wired-OR connection. . By selecting one of the tri-state buffers, any data shift can be performed. In other words, if you pull one of the buffers for each chord length, it will be 1
0 that allows you to instantly obtain food data within 6 bits
An offset decoder 10 converts the offset value 15 into a buffer selection signal line 16. Therefore, even with an 8-bit configuration, the MH variable key code can be read easily and at high speed. The MH code input to the run length decoding ROM is converted into a run length here. In other words, the run length decode ROM is
This is a conversion table configured so that the MH code is used as an address and the corresponding run length is used as output data. The run length of the ROM output is counted by the ten length counter 6, and when the number of black or white bits and the number of white bits are output, the next run length is loaded at the output (RCO) and the toggle flip 7 is inverted. A Vid in which black bit groups and white bit groups are alternately successive is generated by that output and the counter output.
Get the eo signal. 7 is a code length decoding ROM, which is a 0 code which is a conversion table configured so that an MH code is used as an address and the code length of the MH code is used as output data. The length 17 is added to the offset register 9 via the adder group 8. Now human power G, D and E are together

When it is [0], the original offset value of 15 enters the adder group 808 input, and the code length of 17 enters the B input (.), so when the clock is stamped in the offset register, a new The offset value 15 is the offset value of the new offset value 2 + code length. This value gives the start offset value of the MH code next to the MH code just decoded. In other words, the code length of the previously decoded MH The data shifted by the amount can be read and the next M)I can be determined. In this way, the length is not constant
This means that H codes can be decoded one after another. By the way, since the length of the parallel-serial converter B is limited to M, correction is necessary. This means that the offset value 15 is [
8], it is determined by the comparator 11, and the parallel-to-serial converter 6 is incremented by 8 bits, and [-8] is applied to the E input of the adder group 8. In this case, the offset value is the new offset value binary offset value 10 code length - 8
As the data is shifted by 8 bits, the offset value is also shifted by the same amount, but the relative position of the data and the offset value remains unchanged.As mentioned above, the 8-bit increment is performed by the buffer, decoder, and hexadecimal counter, and the ternary counter is [2] Read the memory every time. Therefore, when viewed from the offset register 9, the fc serial data 14 appears to be infinitely long serial data. The EOL code (synchronization signal indicating the end of one line) is decoded by a dedicated decoder. That is, the F, OL decoder group 12, which is the buffer group 4 mentioned above, as described later.
It is composed of 16 PALs, and decodes serial data shifted one bit at a time, and one of the PALs is EO.
When L is detected, EOI is outputted by the 13-person Chaor Gate. When any of the EOL decoders decodes the EOL signal, the EOL detection signal line 18 becomes H level, resets the toggle 7 lip flop 16, and ignores A, B, and E among the inputs of the adder group 8. Only C and D are added and output. The code length of the EOL code [12] is applied to C, and the offset value 19 at which the EOL code is detected is applied to D. As a result, the value of offset value 15 is as follows. New offset value 2 EOL decoder details offset 1 (
The reason why only the li+12EQL code is decoded by dedicated hardware is to prevent the error from spreading to the entire screen in the event of a malfunction by limiting the error to that line only. If there is no error, the input of adder group 8 is EOL
At the time of detection, B and C are naturally equal, and D is equal to the sum of A and E. I can do that. Next, a detailed explanation will be given using FIG. 2. Components common to those in FIG. 1 are given the same numbers. The output (1 word, 24 bits) from the screen memory (not shown) is once latched by the D latch 100. The timing to latch is when the ripple carrier voltage of the hexadecimal counter 101 becomes Hi and the A>B output of the comparator 11 becomes Hi.
That's when I became K. Eight bits of the latched data Do""D23 are input to the D latch 105 via tristate buffers 102, 103 and 104 in a wired OR manner. D latches 105, 106 and 107 perform parallel-to-serial conversion in the form of 8-pit parallel and byte serial. Therefore, buffers 108, 109, etc. are each DO”” D? -s Di~D8... are stored. Of the serially converted output DO""'D23, arbitrary consecutive 8 bits are selected in the tri-state buffer group 4. For example, tri-state buffer 11
If 0 force is selected, D2 to D are run length decoding)” RO
It is transmitted to M5 and the hood length decode ROM side. Since the maximum code length of the 8MH code is 13, this tri-state buffer group should originally be 16 bits long, but due to the characteristics of the MH code, it is possible to By decoding with another circuit, it can be saved to 8 bits. 112 is a PAL for decoding the leading consecutive '\'. PAL is an abbreviation for Programmable Array Logic and is a trademark of Monolithic Memories, Inc. of the United States. For example, if you use two PAL18L4 devices and program with the logic shown in Table 1, if there is no \ from the start address indicated by the offset value from offset register 9, then if there is at least one \, then outputs a zero bit determination output signal which is 1 when there are 4 \, 2 when there are 5 \, and 6 when there are 5 \. This value is input to the data selector 116 and the two RO
M is input as two address selection data. The data select p I 113 generates binary numbers (0) and (1) based on the zero bit determination signal. Select [4] and [5] and output. The output of the data selector 116 is added to an offset value by an adder 114 and applied to the offset decoder 10. Therefore, the buffer selected from the tri-state 7277 group 4 will be 8 consecutive buffers from the buffer further shifted by the output value of the data selector 113, for example, when \ is one, from the buffer shifted one buffer to the right. output data. When the accumulated code length due to the shift output from the buffer group 4 exceeds 8, the output of the offset register 9 exceeds 8, so the converter 7 (later 11 determines this and operates the conversion circuit 3) Shifts up 8 bits 0 Therefore, for example, the latches 10701 to 8 bits)
~8 and latch 106, for example, the same data as the 10th A77 data is stored in the second buffer.0 The numerical value written in the run length ROM5 is the data with the run length code on the address line. Assigning run lengths to lines. One person inputs the black/white signal input to AIO, the zero bit judgment signal to A8-9, and the MH code to A-7. Table 2 shows program examples for the run length decoding ROM and code length decoding E (OM).The run length of the makeup code is 64.
Since it is a multiple of , the value obtained by dividing the run length by 64 is written in the ROM, and later multiplied by 64 in the 6-bit shift circuit 115 to obtain the accurate run length. In other words, shift 6 bits upwards, set O to the lower 6 bits, and apply 08 of OR0M to the makeup code/termination code (run length of 63 or less) judgment signal output (M/T). Ru0
When the make-up code is output, Inno (- Tara 1
6. Toggle printer flop 16 is not inverted by gate 117. EOL code is reset to 1 white. In this way, the capacity of the run length ROM can be reduced. The code length is added to the offset value in adder 118. The value is data selector 1, where side A is usually selected.
19 and an adder 120 to the offset register 9. The data selector 121 is normally

[0]
is selected, and when the converter 11 detects an offset value greater than 8, select [-8]. Therefore, the adder 120 increases the past accumulation by 118 to 8
decrease only. At the same time, open the gate 122 and latch 105,
Shift the values of 106 and 107 by 8 bits. Further, the hexadecimal counter is incremented by one, and if a ripple carry act occurs as a result, the read address counter 2 is incremented. 124 to 127 are PALs for decoding ECIL codes. For example, the EOL code can be decoded by programming the following logic using PALi6L<5. E-/ AOH/ AI H/ A2 γ/ A'3
w'-a 11 @・” ” f’ / AIOH/
Aii H/A12128 is a decoder that determines which PAL has decoded the EQL code and outputs it.
When EOL is detected, the encoder 12B outputs the PA
The output of encoder 4 is set to [12
] and reset the offset output via 119. As a method for dealing with a run length of zero, the present invention requires a Fi-FQ buffer of about 2 words, but this buffer can be made unnecessary by doubling the clock of the post-coder. The present invention also provides B, G-, R or LY from Me7I), etc. It can also be applied to decoding M and C color image encoded data for each color. As explained above, the MH code decoder according to this example has 1
Since it is possible to decode several MH codes within one system clock, an extremely high-speed MH code decoder can be realized. Therefore, it becomes possible to correspond an electronic file in which pixels are compressed and stored with a high-speed printer. In addition, when decoding an MH code, originally it is necessary to decode by looking at a 16-bit long signal line, but in this example, by dividing and decoding the code with consecutive zeros,
The main decoder can be implemented by simply looking at an 8-bit long signal line, so the conversion ROM can be of low cost. Furthermore, this example can prevent the adverse effect of error data on the entire screen.

[Brief explanation of drawings]

Claims (1)

[Claims] (1) In a device that decodes an encoded image signal, a parallel-to-serial conversion circuit that shifts the decoded data by processing the encoded image signal sequence in units of a predetermined number of heads; A gate circuit that extracts consecutive bits of data from an arbitrary position in a serial data string, a storage means for calculating a run length and a code length from the extracted data, and a register for adding and storing the run length. , an fco-7 circuit that controls the position from which the bit data is extracted according to the value of the register, and an fco-7 circuit that shifts the parallel-to-serial converter circuit by a plurality of bits when the value of the register exceeds a predetermined value, and changes the value of the register. A data decoding device characterized by multiple areas.