JPH04213222A - Decoding circuit for unequal length code data - Google Patents

Abstract

PURPOSE:To reduce the time required for decoding an unequal length code data and to decrease the scale of the software. CONSTITUTION:A shift register 1 converts a serial input MH code data (unequal length code data) into a parallel data and outputs it. A PLA 2 receives the parallel data from the shift register 1 and outputs a decoded run length data and a data representing the code length of the unequal length code data. The run length data outputted from the PLA 2 is used for the processing of a next stage via a latch circuit 4 and inputted to a counter 5. The counter 5 outputs shift clocks SCK by a number represented by the inputted unequal length code data to the shift register 1. Thus, a succeeding unequal length code data is correctly set to the shift register 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to, for example, MH code (m
modified Huffman code) and M
The present invention relates to a decoding circuit for decoding unequal length code data such as an R code (modified READ code).

0002

2. Description of the Related Art A black and white binary image can generally be represented by a series of run lengths, but short code data is used for frequently occurring run lengths.
Transmission information can be effectively compressed by allocating long code data to run lengths that occur less frequently. Examples of this type of unequal length code data include the MH code used in G3 facsimiles, etc.
R code etc. are well known.

By the way, when decoding these unequal length encoded data, conventionally, as shown in FIG. I was trying to get the conversion data.

0004

[Problems to be Solved by the Invention] However, since the above-mentioned conventional decoding device performs determination on a bit-by-bit basis, decoding takes time and the size of the software for performing the decoding process is also large. The problem was that it got too big.

[0005] This invention was made to solve these conventional problems, and it is possible to reduce the scale of software and to significantly shorten the decoding processing time of unequal length code data. An object of the present invention is to provide a decoding circuit for unequal length code data.

[0006]

[Means for Solving the Problems] A decoding circuit for unequal length code data according to the present invention includes a serial-to-parallel conversion means for converting serially input unequal-length code data into parallel data, and a serial-to-parallel conversion means for converting serially input unequal-length code data to parallel data. decoding means for outputting composite data and a code length of the unequal length code data based on a combination of bit data from the most significant bit of the means; and shift control means for shifting the unequal length code data stored in the means.

[0007]

According to the present invention, the decoding means outputs not only the decoded data but also the code length of the unequal length code data. Therefore, when the data stored in the serial-to-parallel converter is shifted based on the data of this code length, the serial-to-parallel converter receives the unequal length code data to be decoded next in the correct set position. It will be set. As a result, the decoding means only needs to always refer to the combination of bit data starting from the most significant bit of the serial-to-parallel converting means, and decoded data can be immediately obtained by a normal decoding operation.

As described above, according to the present invention, the determination is not made in bit units, but in units of combinations of unequal length bits starting from the most significant bit of data stored in the serial/parallel conversion circuit. Therefore, the processing time required for decoding is shortened, and the scale of the software can also be reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the accompanying drawings. Here, a case will be described in which an MH code used in G3 facsimile is used as an example of unequal length code data.

In the MH coding method, the number of pixels in one scanning line is 172.
8, the run length from 0 to 1728 is 64
In each group, a termination code is assigned according to the length of white or black pixels. Furthermore, for white or black pixels that last longer than 64 dots, makeup codes are assigned to each multiple of 64. Since white runs and black runs always appear alternately, the beginning of a scanning line is defined as a white pixel. Also, at the end of the scanning line, there is an EOL (End of Line).
) symbol is inserted.

Tables 1 and 2 show the relationship between run length, termination code, and makeup code, respectively. These code data are unequal length code data of 2 to 13 bits. Note that in these tables, the column indicated by CL is data indicating the MH code length (effective number of bits).

0012

[Table 1]

[Table 2]

FIG. 1 is a block diagram showing the configuration of the decoding circuit of this embodiment.

The MH code data inputted as serial data is serially inputted to the shift register 1. The shift register 1 converts serially inputted MH code data into 13-bit parallel data and outputs it.

Parallel data from shift register 1 is processed by PLA (Programmable Logic Ar).
ray)2. PLA2 inputs 13-bit parallel MH code data and 1-bit monochrome information output from flip-flop 3, decodes the MH code data, and inputs the decoded 7-bit run length data. 4-bit code length data indicating the code length of unequal length encoded data is output.

The run length data outputted from the PLA 2 is once stored in the latch circuit 4 and then subjected to the next stage of processing. On the other hand, the code length data output from the PLA 2 is preset in the counter 5. The counter 5 outputs the shift clock SCK to the shift register 1 by the number indicated by the given code length data.

Next, the operation of the decoding circuit of this embodiment configured as described above will be explained.

When MH code data is set in shift register 1, PLA2 is accessed. This results in
PLA2 is 2 to 13 given from shift register 1.
From the bit code data and the 1-bit black and white information given from the flip-flop 3, 7-bit run length data and 4-bit code length data are output.

[0019] When data is output from PLA2 once,
Flip-flop 3 inverts its output. Also,
When EOL is decoded by PLA2, the output of flip-flop 3 is reset to white information. The run length data output from the PLA 2 is loaded into the latch circuit 4, and the code length data is loaded into the counter 5. The run length data loaded into the latch circuit 4 is subjected to processing by means not shown in the subsequent stages.

Further, when the code length data is loaded into the counter 5, the counter 5 counts down the data based on the clock signal CLK, and supplies the shift clock SCK to the shift register 1 until the count value becomes 0. . As a result, the MH code data to be decoded next is correctly set in the shift register 1 at a predetermined set position.

To explain the above processing in more detail, for example, if "1100101011000" is given as 13-bit data input from shift register 1 and "white" is given as monochrome information, P
LA2 has run length data “5” as output data,
Output code length data “4”. At this time, the lower 7 bits have no effect on the output data.

Next, the data stored in the shift register 1 is shifted by the code length data "4", and the shift register 1 is set to "101011000***" (* is 0 or 1). Therefore, from PLA2,
Run length data "3" and code length data "2" are output as output data. At this time, the bottom 9
The bits have no effect on the output data.

By repeating the above operations, rapid decoding processing becomes possible.

[0024] Thus, according to this embodiment, PLA
Since the code length data of the MH code data is output from 2 and the data in shift register 1 is shifted based on this code length data, PLA 2 can always perform decoding easily by combining from the first bit. can.

[0025] PLA2 is based on Table 1 and Table 2 mentioned above.
Since it can be easily created by a normal logic circuit synthesis procedure based on the data shown in , the detailed structure will be omitted. For example, in the case of MH code, the product term (table size) of PLA2 is 195, and the sum term (number of output bits)
is 11 bits.

[0026] Further, as such a decoding means,
ROM tables with other configurations may also be used. Furthermore,
In the above embodiment, an MH code is taken as an example of unequal length code data, but it goes without saying that the present invention is also applicable to decoding other unequal length code data such as MR code and MMR code. Nor.

[0027]

[Effects of the Invention] As described above, according to the present invention,
Based on the unequal length code data output from the decoding means, by correctly setting the stored data of the serial/parallel converting means to a predetermined set position, the data is stored in the serial/parallel converting circuit instead of making a bit-by-bit determination. Since it is possible to perform judgments in units of combinations of unequal length bits starting from the most significant bit of the data, the processing time required for decoding can be shortened and the size of the software can be reduced. play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an MH code data decoding circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining conventional encoding processing of unequal length code data.

[Explanation of symbols]

1 Shift register 2 PLA 3 Flip-flop 4 Latch circuit 5 Counter

Claims (1)

[Claims] 1. Serial/parallel converting means for converting serially input unequal length code data into parallel data, and decoded data and decoded data based on a combination of bit data from the most significant bit of the serial/parallel converting means. a decoding means for outputting the code length of the unequal length code data; and a shift control means for shifting the unequal length code data stored in the serial-to-parallel conversion means by the code length output from the decoding means. What is claimed is: 1. A decoding circuit for unequal length code data.