JPH053186B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data decoding device for image files or facsimile devices. Especially modified
This is effective for high-speed decoding of image signals stored or transmitted after being run-length encoded using Huffman (M.H) codes. Conventionally, this type of apparatus has had the disadvantage that the processing speed of decoding and conversion is not constant, and therefore requires a printer apparatus with a variable sub-scanning speed. For this reason, when outputting to a high-speed electrostatic printer with a constant sub-scanning speed, it was necessary to first develop the data into a buffer memory for one page. Furthermore, since this was done through software processing using a microprocessor, there was a limit to how high the speed could be increased. Furthermore, as disclosed in Japanese Unexamined Patent Publication No. 55-79565, an MH code decoding device constructed using hardware is also known. However, in the method disclosed in Japanese Patent Application Laid-Open No. 55-79565, the MH code is input into a shift register bit-serially, and the ROM is accessed while shifting the MH code in the shift register bit-serially every time one MH code is decoded. Then, M.H.
It decodes the code. In such a configuration, input is made bit-serial to the shift register, so not only does it take time to input the MH code, but the beginning of the MH code must be bit-serial shifted to a predetermined position in the shift register each time it is decoded. Therefore, it takes time to access the decryption ROM. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a data decoding device that is capable of decoding code data of undefined length at high speed and that has a simplified configuration of a conversion table used for decoding. That is, the present invention provides a memory for storing code data of an undefined length, a reading means for reading out a predetermined number of bits of the undefined length code data from the memory in parallel, and an undefined length code data read out in parallel by the reading means of the predetermined number of bits. storage means for successively storing a plurality of pieces of long code data; extraction means for extracting desired n-bit data in parallel from the indefinite length code data stored in the storage means; A detection means for detecting the number of consecutive 0s at the beginning, and accessed by the number of 0s detected by the detection means and n-bit parallel data extracted by the extraction means, and decoded data and a conversion table for outputting the decoded code length; an addition means for sequentially adding the decoded code lengths; A data decoding device characterized by having means for changing a portion of data extracted by the extraction means, and means for storing indefinite length code data from the memory into the storage means according to the addition result of the addition means. . According to the present invention, the configuration is such that desired n-bit parallel data is extracted from a plurality of continuously stored indefinite length code data, the conversion table is accessed, and decoded data is output. There is no need to shift the undefined length code data bit-serially, and the undefined length code data can be decoded at high speed. Furthermore, according to the present invention, the conversion table is accessed by detecting the number of consecutive zeros at the beginning of the stored indefinite length code data and using n-bit parallel data extracted from the stored indefinite length code data. The configuration of the conversion table can be simplified. Moreover, since the n-bit data part to be extracted is changed according to the addition result of the decoded code length and the detection of the number of consecutive 0s, the data extraction at the time of the next indefinite length code data is also appropriate. can be done. Next, the present invention will be explained in detail based on the illustrated embodiments. FIG. 1 is a schematic block diagram of an MH code decoder according to the present invention. In the figure, reference numeral 1 denotes a screen memory in which an MH encoded image signal is stored.
1 is an image file memory. The data from here is output in 24-bit parallel or converted to that format and output. 2 is a read address counter for giving a read address of the screen memory 1; 3 is a parallel/serial converter. The output data line On from the screen memory 1 has a 24-bit configuration to increase relative speed. 3 is a parallel-to-serial converter for dividing 24-bit data into three 8-bit data and serially converting each 8-bit data. Therefore, this conversion circuit 3 converts the ternary counter 1 to increment the read address counter 2 by one after shifting 8-bit data three times.
01 (Figure 2). Therefore, time delays caused by converting 24 bits as they are using a shift register can be prevented. 4 is a tri-state buffer group that performs run length decoding of up to 13 consecutive pieces of data from the serially converted data 14, starting with the data with the offset value 15 indicated by the offset register 9.
This is for inputting to the ROM 5 and code length decoding ROM 7. Here, the offset value is 8
Serial data shifted in parallel bit by bit
This is data indicating from which position of D ₀ to D ₂₅ the MH code is extracted. Therefore, specifically, a plurality of 13-bit tri-state buffers (14) are prepared, and their input lines are shifted one bit at a time to the signal line 14.
The output line is configured by wired-OR connection. Any data shift can be performed by selecting one of the tristate buffers. In other words, by enabling one of the buffers for each code length, code data within 13 bits can be obtained instantaneously. An offset decoder 10 converts the offset value 15 into a buffer selection signal line 16. Therefore, even with an 8-bit configuration, the MH variable key code can be read easily and at high speed. The MH code input to the run length decoding ROM is converted into a run length here. That is, the run length decode ROM is a conversion table configured to use the MH code as an address and the corresponding run length as output data. The run length of the ROM output is counted by a run length counter 6, and the number of black or white bits and the number of white bits are output. The next run length is loaded by the signal ripple carry out (RCO) indicating the end of counting in the run length counter 6, and the toggle flip-flop 13 is inverted and the black bit group,
Obtain a video signal in which groups of white bits are alternately continuous. 7 is a code length decode ROM, which is a conversion table configured to use an MH code as an address and the code length of the MH code as output data. Code length 17 is added to offset register 9 via adder group 8. Now input C, D and E are together

When it is [0], the original offset value 15 is input to the A input of the adder group 8, and the code length 17 is input to the B input, so when a clock is applied to the offset register, the new offset value is input. 15 is the new offset value=original offset value+code length. This value is the next value of the MH code just decoded.
Gives the starting offset value of the MH code. In other words, the next MH can be determined by reading the data shifted by the code length of the previously decoded MH. In this way, MH codes whose lengths are not constant can be decoded one after another. By the way, since the length of the parallel-serial converter 3 is finite, correction is necessary. This means that when the offset value 15 exceeds [8], the comparator 11 determines, and the parallel-serial converter 3 is incremented by 8 bits, and the E input of the adder group 8 is sent to [-].
8] is applied. In this case, the offset value is: new offset value=original offset value+code length-8, so the data is shifted by 8 bits and the offset value is also shifted by the same amount, so the relative position of the data and the offset value remains unchanged. The 8-bit increment is performed by the buffer, decoder, and ternary counter as described above, and the memory is read every time the ternary counter reaches [2]. Therefore, the serial data 14 viewed from the offset register 9 appears to be infinitely long serial data. The EOL code (synchronization signal indicating the end of one line) is decoded by a dedicated decoder. That is, the EOL decoder group 12 is composed of 13 PALs like the buffer group 4, as described later.
The serial data shifted one bit at a time is decoded, and if any PAL detects EOL, it outputs EOL using a 13-input OR gate. When any of the EOL decoders decodes the EOL signal,
The EOL detection signal line 18 becomes Hi level, and the toggle flip-flop 13 is reset, and among the inputs of the adder group 8, A, B, and E are ignored, and only C and D are added and output. The EOL code table [12] is applied to C, and the offset value 19 at which the EOL code is detected is applied to D. As a result, the value of the offset value 15 is as follows. New offset value = Offset value of the EOL decoder group + 12 The reason why only the EOL code is decoded using dedicated hardware is to prevent the error from spreading to the entire screen in the event of a malfunction by limiting the error to that line only. be. If there is no error, the input of adder group 8 will be equal to B and C when EOL is detected.
Also, D is equal to the sum of A and E. In this way, by resetting the offset register, it is possible to provide the cutting position of the MH code next to the EOL code. Next, a detailed explanation will be given using FIG. 2. Components common to those in FIG. 1 are given the same numbers. The output (24 bits per word) from the screen memory (not shown) is once latched by the D latch 100. The timing for latching is when the ripple carryout of the ternary counter 101 becomes Hi and the A>B output of the comparator 11 becomes Hi. The latched data D ₀ -D ₂₃ are divided into 8 bits and input to D latch 105 via tristate buffers 102, 103 and 104 by wired OR. D latches 105, 106 and 107 perform parallel-to-serial conversion in 8-bit parallel and byte serial format. Therefore, the buffers 108, 109... have D ₀ to D ₇ , D ₁ respectively.
~D ₈ ... is stored. Serialized output
Among D ₀ to _{D 23} , arbitrary consecutive 8 bits are selected in tristate buffer group 4. For example, if tri-state buffer 110 is selected
D ₂ to _{D 9} are transmitted to the run length decode ROM 5 and code length decode ROM 7 sides. Since the maximum code length of the MH code is 13, originally this tri-state buffer group needs to be 13 bits long.
Due to the characteristics of the MH code, it is possible to save 8 bits by decoding the leading 1, 4 or 5 consecutive "0's" using a separate circuit. 112 is a PAL for decoding consecutive "0"s at the beginning.
PAL is an abbreviation for Programmable Array Logic and is a trademark of Monolithic Memories, Inc. in the United States. For example, if two devices called PAL18L4 are used and programmed with the logic shown in Table 1, if there is no 0 from the start address indicated by the offset value from offset register 9, there will be 0, or at least one 0. A zero bit determination output signal is output, which is 1 when there are 4 0s, 2 when there are 4 0s, and 3 when there are 5 0s. This value is input to the data selector 113 and is also input to the two ROMs as two address selection data. Data selector 11
3 is a binary number based on the zero bit judgment signal

[0],
Select and output [1], [4], and [5]. The output of the data selector 113 is added to an offset value in an adder 114 and applied to the offset decoder 10. Therefore, tristate buffer group 4
The buffer selected from among them is further shifted by the output value of the data selector 113, and then
For example, when there is one 0, eight pieces of data are continuously output from the buffer skipped one buffer to the right. When the accumulated code length due to the shift output from the buffer group 4 exceeds 8, the output of the offset register 9 exceeds 8, so the comparator 11 determines this and operates the conversion circuit 3. In other words, Latch 10
5 to 107 are shifted up 8 bits. Therefore, for example, bits 1 to 8 of latch 107 are buffer 10.
8 bits 1 to 8, 107 bits 2 to 8, and latch 106 bits 1 to 8 of buffer 109
Since each buffer and latch are bit-connected in such a manner that the latches are bit-to-bit, the same data as the 10th buffer data is stored in the second buffer, for example. The numerical value written in the run length ROM 5 assigns a run length code to the address line and a run length to the data line. Black/white signal input to A ₁₀ , A ₈ to ₉
Input the zero bit judgment signal to A0 to A7, and input the MH code to _A0 to _A7 . Table 2 shows examples of programs for the run length decode ROM and code length decode ROM. Since the run length of the make-up code is a multiple of 64, the value obtained by dividing the run length by 64 is written in the ROM, and later multiplied by 64 in the 6-bit shift circuit 115 to obtain the accurate run length. In other words, it shifts 6 bits to the upper part, sets 0 to the lower 6 bits, and outputs the result. ₀₈ of the ROM is assigned to the make-up code/termination code (run length of 63 or less) determination signal output (M/T). When the make-up code is output, the toggle flip-flop 13 is not inverted by the inverter 116 and gate 117. Reset to “white” for EOL code. In this way, the capacity of the run length ROM can be reduced. The code length is added to the offset value in adder 118. The value is applied to the offset register 9 via the data selector 119 and the adder 120, in which the A side is normally selected. The data selector 121 is normally

If [0] is selected and the comparator 11 detects an offset value greater than 8, then [-8] is selected. Therefore, adder 120 subtracts the past accumulation by 118 by eight. At the same time, the gate 122 is opened and the latch 10
Shift the values of 5, 106 and 107 by 8 bits. Further, the ternary counter is incremented by one, and if a ripple carry-out occurs as a result, the read address counter 2 is incremented. 124 to 127 are PALs for EOL code decoding.
For example, EOL codes can be decoded by programming the following logic using PAL16L6. E=/A ₉ */A ₁ */A ₂ */A ₃ */… …*/A ₁₀ */A ₁₁ */A ₁₂ 128 determines which PAL has decoded the EOL code and outputs it. It is a decoder. When EOL is detected, the encoder 128 determines in which PAL it occurred, and from there, [12] is added to the output of the encoder 4 to jump the offset output by the amount of EOL, and the offset output is reset via 119. . As a method for dealing with a run length of zero, the present invention requires an F1-F0 buffer of about 2 words, but this buffer can be made unnecessary by doubling the decoder clock. The present invention also provides B, G, R or Y from memory etc.
It can also be applied to decoding M and C color image encoded data for each color. As explained above, the MH code decoder according to this example is capable of decoding one MH code within one system clock, so an extremely high-speed MH code decoder can be realized. Therefore, it becomes possible to correspond an electronic file in which pixels are compressed and stored with a high-speed printer. In addition, when decoding an MH code, originally it is necessary to decode it by looking at a 13-bit long signal line, but in this example, by dividing and decoding consecutive zero codes, the main decoder can decode an 8-bit long signal. This is possible just by looking at the line, so for conversion
ROMs can be inexpensive. Furthermore, this example can prevent the adverse effect of error data on the entire screen.

【table】

Claims (1)

[Scope of Claims] A memory for storing code data of an undefined length; a reading means for reading out a predetermined number of bits of the undefined length code data in parallel from the memory; storage means for successively storing a plurality of pieces of long code data; extraction means for extracting desired n-bit data in parallel from the indefinite length code data stored in the storage means; a detection means for detecting the number of consecutive 0s at the beginning; accessed by the number of 0s detected by the detection means and n-bit parallel data extracted by the extraction means; and decoded data and a conversion table for outputting the decoded code length; an addition means for sequentially adding the decoded code lengths; A data decoding device comprising: means for changing a portion of data extracted by the extracting means; and means for storing indefinite length code data from the memory into the storing means according to the addition result of the adding means.