JPH07236065A - Binary picture compression device - Google Patents

Abstract

PURPOSE:To provide a binary picture compression device capable of performing a high-speed processing by shortening the count time and the coincidence detection time of the picture elements of picture data to be encoded. CONSTITUTION:This device is provided with a picture element detection part 24 for inputting the picture data for prescribed bits and outputting the continuous picture element number of the same color picture elements, a burrel shifter 23 and a noncoincidence detection part 32 for detecting the continuous picture element number of a different picture element color from a position shifted for the bits of the continuous picture element number outputted from the picture element detection part 24 to a low-order side, counters 27 and 29 for counting the continuous picture element number of the different picture element color detected in the noncoincidence detection part 32, an adder 25 for adding the count value outputted from the counters 27 and 29 and the continuous picture element number outputted from the picture element detection part 24 for the same picture element color and code ROMs 30 and 31 for encoding the added result of the adder 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a facsimile 1
The present invention relates to a binary image compression device such as dimensional encoding.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional binary image compression apparatus for one-dimensional encoding of a facsimile. The one-dimensional encoding encodes the number of consecutive same pixel colors. That is, 1 byte (8 bytes) from the image RAM 1 in which the image data is written.
The image data for (bit) is read and output to the flip-flop (FF) 2. The image data input from the image RAM 1 is written and held in the flip-flop 2. The image data held in the flip-flop 2 is output to the shift register 3. The shift register 3 receives the image data from the flip-flop 2 and the clock pulse CLOCK, shifts the image data bit by bit and outputs the pixels pixel by bit. The output of the shift register 3 is output to the mismatch detection section 4. As shown in FIG.
It is composed of a flip-flop 5 that stores the pixel color before the bit and an identity circuit 6 that detects a match between the current pixel color and the pixel color before the bit from the flip-flop 5. That is, M of the shift register 3 is connected to one input of the identity circuit 6.
The SB bit signal is supplied, and the signal one bit before, which is output from the flip-flop 5, is supplied to the other input. Therefore, a high level is output to the output of the identity circuit 6 when the MSB bit signal and the signal one bit before are in agreement. As a result, the continuity of the currently targeted pixel color can be detected. The output signal of the mismatch detection section 4 is output to the input terminal en of the TC (terminator code) counter 7. The TC counter 7 receives the clock pulse CLOCK and counts the clock pulses while the output signal input from the mismatch detection section 4 is at a high level, thereby counting the number of consecutive pixels of the same color.
The carry output terminal CA of the TC counter 7 is connected to the input terminal en of the MC (makeup code) counter 8. Like the TC counter 7, the clock pulse CLOCK is input to the MC counter 8. The counting result of the pixel number of the TC counter 7 is supplied to a code ROM (terminator code) 9, and the counting result of the pixel number of the MC counter 8 is supplied to a code ROM (makeup code) 10. The code ROM (terminator) 9 stores codes corresponding to the pixel numbers 0 to 63 one by one, and the code ROM (makeup) 10 stores the pixel numbers 64 to 17
Up to 28, 64 corresponding codes are stored. Then, when the MSB bit signal of the shift register 3 input to the mismatch detection unit 4 and the signal one bit before do not match, the mismatch detection unit 4 outputs a low level, and the code ROMs 9 and 10 correspond to each other. A code corresponding to the counting result of the number of pixels input from the counters 7 and 8 is output.

[0003]

However, in such a conventional binary image compression apparatus, it is necessary to perform pixel coincidence detection and counting by the number of bits of image data to be encoded in the shift register ( Since the coincidence detection is performed bit by bit), there is a drawback that the processing time becomes long.

The present invention has been made in view of the above circumstances, and provides a binary image compression apparatus capable of reducing the coincidence detection time and the count time of pixels of image data to be encoded and enabling high-speed processing. The purpose is to

[0005]

In order to achieve the above object, the present invention provides a coincidence detecting means for detecting a coincidence of pixel data of a predetermined bit with a previous pixel for each bit, and a coincidence output of the coincidence detecting means. In a binary image compression apparatus having a counting means for counting and an encoding means for outputting a predetermined code corresponding to the count value of the counting means, the number of continuous pixels of continuous pixels in the pixel data of predetermined bits is detected. It has a continuous pixel detecting means and an adding means for adding the number of continuous pixels detected by the continuous pixel detecting means to the count value of the counting means.

Further, according to the present invention, a shift means for holding pixel data of a predetermined number of bits and shifting it from a predetermined position by 1 bit, 1-bit pixel data output from the shift means, and 1 bit of this pixel data. A coincidence detecting means for detecting coincidence with the previous pixel data, a counting means for counting the coincidence output detected by the coincidence detecting means, and an encoding means for outputting a predetermined code corresponding to the count value of the counting means. In a binary image compression apparatus having :, a continuous pixel detecting means for detecting the number of continuous pixels of continuous pixels in pixel data of a predetermined bit; and the number of continuous pixels detected by the continuous pixel detecting means of the counting means. Adding means for adding to the count value, wherein the shift means is configured to add the pixel data for the number of continuous pixels detected by the continuous pixel detecting means. It is characterized in that to shift the data.

Further, according to the present invention, shift means for holding a predetermined number of bits of pixel data and shifting from a predetermined position by 1 bit, 1-bit pixel data output from the shift means, and 1-bit of this pixel data. A coincidence detecting means for detecting coincidence with the previous pixel data, a counting means for counting the coincidence output detected by the coincidence detecting means, and an encoding means for outputting a predetermined code corresponding to the count value of the counting means. A binary image compression apparatus including: and a continuous pixel detecting unit that detects the number of continuous pixels of 1 byte or more in a predetermined bit of pixel data,
An adding unit for adding the number of continuous pixels detected by the continuous pixel detecting unit to the count value of the counting unit, and the shift unit includes the pixel data for the number of continuous pixels detected by the continuous pixel detecting unit. It is characterized by shifting.

[0008]

According to the present invention, the same-color pixel detecting means detects the coincidence of pixels of a predetermined number of bits at a time and adds the coincidence to the counter. Therefore, the coincidence detection of the pixels of the image data to be encoded and the count time can be shortened. Therefore, high speed processing can be achieved.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration explanatory view showing an embodiment of the present invention. In this embodiment, white is "0" and black is "1" for convenience, but white may be "1" and black may be "0". That is, the image RAM 2 in which the image data is written
From 1 to 1 byte (8 bits) of image data is read and output to the flip-flop (FF) 22. Image data input from the image RAM 21 is written and held in the flip-flop 22. The image data held in the flip-flop 22 is the barrel shifter 23.
It is also output to the pixel detection unit 24. As shown in FIG. 2, in the pixel detection unit 24, the output of the flip-flop 22 is input to the selector 34 and the selector 34 via the inverter 35. The selector 34 is supplied with a pixel color storage output (pixel 1 bit before) from the flip-flop 5 of the mismatch detection section 32 described later, and when the color of the pixel 1 bit before is white “0”, The output of the flip-flop 22 is directly input to the priority encoder 36, and when the color of the pixel one bit before is black “1”, the flip-flop 22
An inverted signal obtained by inverting the output of 1 by the inverter 35 is input to the priority encoder 36. This allows
Pixels consecutive one pixel before are always "0". Then, as shown in FIGS. 3A to 3I, in accordance with the input of 1 byte (8 bits) of image data from the MSB bit to the LSB bit of the priority encoder 36 (continuity of "0"), the priority is set. At the output of the encoder 36, the number of consecutive pixels 0 to 8 from 1 bit before is output as 3 bits, and the priority encoder 3
The output of 6 is output to the selector 26 and the adder 25.
That is, as shown in FIG.
The output of the priority encoder 36 becomes 0, which means that a different pixel color is detected without detecting any bit. B
In the case of, the priority encoder 3 means that a different pixel color is detected after detecting 1 bit of the same color pixel.
The output of 6 becomes 1. In the case of C, the output of the priority encoder 36 is 2, which means that the same color pixel is continuously detected for 2 bits and then a different pixel color is detected.
In the case of D, the output of the priority encoder 36 is 3, which means that the same color pixel is continuously detected for 3 bits and then a different pixel color is detected. In the case of E, the output of the priority encoder 36 is 4, which means that the same color pixel is continuously detected for 4 bits and then the different pixel color is detected. In the case of F, the output of the priority encoder 36 is 5, which means that the same color pixel is continuously detected for 5 bits and then a different pixel color is detected. In the case of G, the priority encoder 3 means that the same color pixel is continuously detected for 6 bits and then a different pixel color is detected.
The output of 6 becomes 6. In the case of H, the output of the priority encoder 36 is 7, which means that the same color pixel is continuously detected for 7 bits and then a different pixel color is detected.
In the case of I, the output of the priority encoder 36 is 8, which means that the same color pixel is continuously detected for 8 bits and then a different pixel color is detected.

Here, as shown in FIG. 3, when the input of the priority encoder 36 is I, the appearance rate is high in the document image image data. Therefore, in almost all cases, it is absolutely necessary to detect the coincidence of the image data bit by bit. In addition, the adder 25 adds 8 input from the priority encoder 36 to the counting result of the number of continuous pixels input from the TC counter 27 up to now, so that the continuous pixels up to the image data written in the priority encoder 36 are added. It can be a number. The number of continuous pixels output from the adder 25 is input to the load terminal LOAD of the TC counter 27, and the value of the TC counter 27 is rewritten. The carry output CA of the adder 25 is input to one input terminal of the OR circuit 28. In this case, since the pixel data loaded in the barrel shifter 23 does not need to be scanned, the pixel data is not shifted, and the processing for the next 1 byte (8 bits) of pixel data is started.

Further, when the input of the priority encoder 36 is A to H, it means that the pixel color opposite to the pixel color one bit before is detected in the 1-byte (8-bit) pixel data. The output 0 to 7 of the priority encoder 36 is added to the counting result of the number of continuous pixels up to now which is the output of the TC counter 27 by the device 25, and the addition result is the number of continuous pixels of the pixel color to be encoded. Is loaded into the TC counter 27. This TC counter 27
The carry output terminal CA of is connected to the other input terminal of the OR circuit 28, and the output terminal of the OR circuit 28 is connected to the input terminal en of the MC counter 29. The counter 2
A clock pulse CLOCK is input to 7 and 29.
The number of continuous pixels loaded in the TC counter 27 is supplied to a code ROM (terminator code) 30, and the number of continuous pixels of the MC counter 29 is supplied to a code ROM (makeup code) 31. Code ROM
(Terminator code) 30 has 1 to 0 to 63 pixels
Codes are stored one by one, and the code ROM (makeup code) 31 stores 64 codes by the number of pixels 64 to 1728. Then, the code ROMs 30 and 3
1 outputs a code corresponding to the number of continuous pixels input from the corresponding counters 27 and 29. Next, based on the number of consecutive pixels input through the selector 26, the 1-byte pixel data held in the barrel shifter 23 is shifted by a bit corresponding to the number of consecutive pixels. The pixel coincidence detection shift is performed. This barrel shifter 23 has a flip-flop 22
Since the same image data as that of the pixel detection unit 24 is input, the remaining pixels for which the match cannot be detected by the pixel detection unit 24 are shifted by 1 bit and the mismatch detection unit 32 detects the match. As shown in FIG. 11, the non-coincidence detecting unit 32 is composed of a flip-flop 5 for storing a pixel of 1 bit before and an identity circuit 6 for detecting the coincidence of the current pixel and the pixel of 1 bit before from the flip-flop 5. To be done. That is, the MS of the barrel shifter 23 is connected to one input of the identity circuit 6.
The B-bit signal is supplied, and the signal one bit before, which is output from the flip-flop 5, is supplied to the other input.
Therefore, a high level is output to the output of the identity circuit 6 when the MSB bit signal and the signal one bit before match. Therefore, by counting this coincidence output, the number of continuous pixels of the target pixel color can be detected. The output signal of the mismatch detection section 32 is the selector 3
3 is output to the input terminal en of the TC counter 27. The selector 33 validates the en signal of the TC counter 27 when the bit shift of the barrel shifter 23 is detected. The TC counter 27 is used by the mismatch detection unit 3
While the output signal input from 2 is at the high level, the number of continuous pixels of the target pixel color is counted. The TC counter 27
The counting result of the number of continuous pixels of is supplied to a code ROM (terminator code) 30 and the counting result of the number of continuous pixels of the MC counter 29 is supplied to a code ROM (makeup code) 31. The code ROM (terminator code) 30 stores codes corresponding to the pixel numbers 0 to 63, one by one, and the code ROM (makeup code) is stored.
Reference numeral 31 stores a code corresponding to 64 pixel numbers 64 to 1728. When the MSB bit of the barrel shifter 23 input to the mismatch detection unit 32 and the signal one bit before do not match, the mismatch detection unit 32 outputs a low level and the code ROMs 30 and 31 respectively correspond to the corresponding counters 27. , 29 to output a code corresponding to the result of counting the number of continuous pixels.

In this embodiment, in order to continuously count the number of pixels of the same color, a priority encoder for detecting the coincidence of a plurality of pixels at one time and an adder for adding the coincidence detection output to the counter are provided. It has the advantage that the match detection time and the count time can be shortened, and high-speed processing is possible, so it can be used for facsimiles, document image processors, and the like.

FIG. 4 is a structural explanatory view showing another embodiment of the present invention. That is, the CCD 51 forming the scanner scans the transmission original to convert it into image data of a digital signal and outputs the image data to the flip-flop 52 which holds 1 byte (word) of image data. Image data converted into a digital signal by the CCD 51 is written and held in the flip-flop 52. The image data held in the flip-flop 52 is output to the image memory 53 that stores image data for one page (block) byte by byte. In the image memory 53, the image data input from the flip-flop 52 is written byte by byte and stored by the address from the image memory address counter 54. At the same time, the image data held in the flip-flop 52 is 1
It is output to the flip-flop 60 byte by byte. In the flip-flop 60, the image data input from the flip-flop 52 is written and held in units of 1 byte (8 bits). Therefore, the flip-flop 60 holds the image data of the address before writing to the image memory 53, but at the beginning of one line, "000000" is stored.
01 "is initialized. The image data held in each of the flip-flops 52 and 60 is output to the image data comparison unit 61 by 1 byte (8 bits).

As shown in FIG. 5, the image data comparing section 61 receives an AND circuit 611 and a NOR circuit 612 into which the current image data held in the flip-flop 52 is input by 1 byte (8 bits). The AND circuit 613 and the NOR circuit 614 into which the previous image data held in the flip-flop 60 is input by 1 byte (8 bits), the AND circuits 611 and 613 and the NOR circuit 6
The outputs of 12, 614 are the inverter IV and the AND circuit AN.
D, an OR circuit OR, and an OR circuit 615 that outputs an output signal to the terminal a of the selector 64 and an OR circuit 616 that outputs an output signal to the terminal b of the selector 64. The output signal CA of the line counter 72 is input to the AND circuit AND. That is, the image data comparison unit 61 compares the current address image data of the flip-flop 52 with the previous address image data of the flip-flop 60, detects the first byte and the last byte when the same pixel color continues for 1 byte or more, The previous address selection signal and the current address selection signal are output to the terminals a and b of the selector 64, and the write enable signal to the address memory 62 and the count signal of the address counter 63 are output.

Specifically, the previous address selection signal or the current address selection signal (input to the terminals a and b of the selector 64) in the following cases is output. (1) The current address when the previous address held in the flip-flop 60 and the data of the current address held in the flip-flop 52 are different and the data of the current address are all bits "1" (or "0") A selection signal is output, and when the data of the previous address and the data of the current address are different and the data of the previous address is all bits "1" (or "0"), the previous address selection signal is output.

(2) When the data of the previous address and the current address are different and the data of the previous address and the current address are all bits "1" (or "0") (when the previous address is "1") The current address is "0" and the current address is "1" when the previous address is "0". The previous address selection signal is output, and the current address selection signal is output at the next timing. The address count is held while the selection signal is output.

(3) The carry CA from the line counter 72 is "1" (the last byte of one line), the current address is all bits "1" (or "0"), and the previous address is all bits "1" (or When "0"), the current address selection signal is output.

(4) When the carry CA from the line counter 72 is "1", the data of the previous address and the data of the current address are different, and the data of the current address is all bits "0" (or "1"), The current address selection signal is output, and the current address selection signal is output again at the next timing. The address count is held while the selection signal is output.

The line counter 72, which carries the number of bytes in one line, operates in synchronization with the address count of the image memory address counter 54. That is, the addresses of the image data within one line are counted. The output of the line counter 72 (= current address) and the output of the value (= previous address) obtained by subtracting 1 from the line counter 72 by the decrementer 73 are supplied to the selector 64.

FIG. 6 is a circuit example of the selector 64. That is, the detection signals of the first byte and the last byte when the same pixel color continues for one byte or more from the image data comparison unit 61 are supplied to the terminals a and b of the selector 64. Selector 6
The detection signal of the final byte supplied to the terminal b of No. 4 is input to the input terminal of the inverter 81, and the output of this inverter 81 is input to one input terminal of the NOR circuit 82. The detection signal of the leading byte supplied to the terminal a of the selector 64 is input to the other input terminal of the NOR circuit 82 and one input terminal of the AND circuit 83. The output signal of the line counter 72 is input to one input terminal of the AND circuit 84, and the output signal of the decrementer 73 is input to the other input terminal of the AND circuit 83. The NOR circuit 8
The output signal 2 is input to the other input terminal of the AND circuit 84. The output signal of the AND circuit 84 and the output signal of the AND circuit 83 are respectively input to the input terminals of the NOR circuit 85, and the output signal of the NOR circuit 85 is output to the inverter 86.
It is extracted as an output signal of the selector 64 via.

The selector 64 switches the value written in the address memory 62 between the line counter 72 (= current address) and the decrementer 73 which is a value obtained by subtracting 1 from the line counter 72 (= previous address).

That is, when the previous address selection signal is input to the terminal a, the address from the decrementer 73 is selected and written in the address memory 62, and the address counter 63 is counted up. When the current address selection signal is input to the terminal b, the address from the line counter 72 is selected and written in the address memory 62, and the address counter 63 is counted up.

As a result, when the same pixel color continues for 1 byte or more in the image data, the start address in one line at that time is written to the n address of the address memory 62, and the last address is written to the n + 1 address of the address memory 62. Be done.

Further, the MS of the data in the address memory 62
The image color is written in the B bit. FIG. 8A shows the data structure of the address memory 62. That is, the data in the address memory 62 is composed of the start address, the end address, and the image color.

For example, k lines and k as shown in FIG.
It is assumed that +1 line of image data is input. First, 1 byte of image data from the CCD is first written in the flip-flop 52 and also in the image memory 53. Next, the data of the current address (0) of the flip-flop 52 and the data of the previous address (-1) of the flip-flop 60 are compared. However, since the previous address (-1) does not exist, the image of the flip-flop 52 remains as it is. Data is written in the flip-flop 60, and each counter 54,
Count up 72 (count up is performed each time the data is updated).

Then, the next 1-byte image data is written in the flip-flop 52 and also in the image memory 53, and the image data in the flip-flop 52 and the flip-flop 60 are sequentially updated in this manner (hereinafter the same. ). Here, when comparing the data of the current address (1) and the data of the previous address (0), the data of the previous address and the data of the current address are different, and the data of the current address is all bits “0”. Comparison unit 6
The current address selection signal is output from 1, the selector 64 selects the address (1) from the line counter 72, and the head address is written to the address of the address memory 62 indicated by the address counter 63 (see FIG. 8).
(See (c)), the address counter 63 is incremented. At this time, the pixel color (“0”) is stored in the address memory 62.

Next, when the data of the previous address (1) and the data of the current address (2) are compared, since all the bits of the data of the previous address and the data of the current address are all "0", each counter is counted up.

Next, comparing the data at the previous address (2) and the data at the current address (3), the data at the previous address and the data at the current address are different, and all the bits of the data at the previous address are "0". The previous address selection signal is output from the data comparison section 61, and the decrementer 7 is selected by the selector 64.
The address (2) from 3 is selected, the final address is written to the address of the address memory 62 indicated by the address counter 63 (see FIG. 8C), and the address counter 63 is counted up.

In this way, the count-up is sequentially performed,
The first address, the last address, and the pixel color are sequentially stored in the address memory 62. Then, since the data of the address (n-2) of the k line and the data of the address (n-1) are different and the data of the address (n-1) is all bits "1", n-1 is stored in the head address. It Further, both the data of the address (n-1) and the data of the address (n) are all bits "1", but since the address (n) is the final address (because the carry CA is "1"), the current address Is stored in the final address (see FIG. 8C).

Similarly, in the case of k + 1 lines, FIG.
As shown in (d), the start address, the end address, and the pixel color are stored. Then, when the writing of the image data to the image memory 53 is completed, one byte (8 bits) of image data is read from the image memory 53 and output to the flip-flop (F / F) 55. The image data input from the image memory 53 is written and held in the flip-flop 55. The image data held in the flip-flop 55 is output to the shift register 56. The shift register 56 receives the image data from the flip-flop 55 and the clock pulse CLOCK, shifts the image data bit by bit, and outputs the most significant bit pixel bit by bit. The output of the shift register 56 is output to a mismatch detection section that detects pixels different from the pixel color to be encoded. This mismatch detection unit is composed of a flip-flop 571 that stores the pixel color of 1 bit before, and an identity circuit 572 that detects the match between the current pixel color and the pixel color of 1 bit before from the flip-flop 571. . That is, the MSB bit signal of the shift register 56 is supplied to one input of the identity circuit 572, and the 1-bit previous signal output from the flip-flop 571 is supplied to the other input. Therefore, the output of the identity circuit 572 is MSB
When the bit signal and the signal one bit before are in agreement, a high level is output. As a result, the continuity of the currently targeted pixel color can be detected. The identity circuit 5
The output signal of 72 is output to the input terminal en of the TC (terminator code) counter (6-bit counter) 581. This TC counter 581 has a clock pulse CLOC.
When K is input and the output signal input from the identity circuit 572 is at a high level, clock pulses are counted to count the number of consecutive pixels of the same color. The carry output terminal CA of the TC counter 581 is connected to the input terminal en of an MC (makeup code) counter (6-bit counter) 582. Like the TC counter 581, the clock pulse CLOCK is input to the MC counter 582 to count the number of consecutive pixels of the same color.

At this time, the address n of the address memory 62
Is input to the flip-flop 65 to be held and the address n + 1 of the address memory 62 is input to the flip-flop 6
5 and holds it (the MSB of the data in the address memory 62 is a bit indicating the pixel color). The value excluding the MSB of the flip-flop 65 and the value of the image memory address counter 54 are input to the comparator 67, and the comparator 67 compares the value excluding the MSB of the flip-flop 65 with the value of the image memory address counter 54 and matches them. If the MSB of the flip-flop 65 and the value of the flip-flop 571 match, the pixel scan of the shift register 56 and the increment operation of the counters 581 and 582 are suspended. Thereafter, the value of the flip-flop 65 and the value of the flip-flop 66 are respectively input to the subtractor 68, and the subtractor 68 outputs the value obtained by subtracting the value of the flip-flop 65 from the value of the flip-flop 66 to the incrementer 71. . The incrementer 71 increments the input value from the subtractor 68 by +1 and calculates the number of consecutive identical pixel bytes calculated by the adder 69.
Output to. This adder 69 shifts the output value of the incrementer 71 to the left by 3 bits (shifts to the left by 3 bits to convert the number of bytes into bits) and the count value input from the counters 581 and 582. Is added. That is, when the value of the flip-flop 66 is 2 ₍₁₀₎ and the value of the flip-flop 65 is 0 ₍₁₀₎ , the output value of the subtractor 68 is 2 ₍₁₀₎ -0 ₍₁₀₎ = 2 ₍₁₀₎ . , This 2
₍₁₀₎ becomes 3 ₍₁₀₎ by incrementing +1 ₍₁₀₎ by the incrementer 71, and this 3 ₍₁₀₎ becomes the number of bytes to be added. As shown in FIG. 7, the adder 69 connects the output of the incrementer 71 to 11 bits (MSB) to 3 bits, and 2 bits to 0 bit (LSB) is GND.
The number of bits to be added is 2 by fixing to (ground)
4 ₍₁₀₎ is achieved. The added value of the adder 69 is output to the counters 581 and 582. In this case, consecutive 1
When image data of the same pixel color of bytes or more is detected, the pixel scanning operation of the shift register 56 bit by bit is interrupted and the number of consecutive identical pixels is counted by the counter 58.
Add to the count value of 1,582. Therefore, the pixel scanning operation for each bit of the shift register 56 while the same pixel color continues is omitted. Next, the value of the flip-flop 66 is output to the incrementer 70, and the incrementer 70 outputs the value of the flip-flop 6.
A value obtained by adding 1 to the output value of 6 is output to the image memory address counter 54. The image memory address counter 54 receives the output value from the incrementer 70, reads the image data from the image memory 53, restarts the pixel scanning operation of the shift register 56 bit by bit, and encodes the pixel color to be encoded. When 1 is detected, the scan operation of the shift register 56 bit by bit is ended, and the code corresponding to the final count value of the number of pixels counted by the counters 581 and 582 is obtained from the code ROMs 591 and 592.

At the beginning of one line of pixel data, the value of the image memory address counter 54 is compared by the comparator 67 with the value excluding the MSB of the flip-flop 65,
If they match and the MSB of the flip-flop 65 is 1, the start of one line of pixel data starts with a black pixel, and therefore a code of white 0 run length is output.

Further, the value of the image memory address counter 54 and the value excluding the MSB of the flip-flop 65 are compared by the comparator 67, and when they match, the MSB of the flip-flop 65 and the value of the flip-flop 571 are the identity circuit. If they do not match according to 573, the pixel scan ends with the last bit of the previous byte, so the code corresponding to the coefficient value of the number of pixels is code ROMs 591, 59.
Get from 2.

FIG. 9 is a system application example in which the binary image compression apparatus according to the present embodiment is used in a facsimile. When transmitting by facsimile, the image data obtained by scanning the transmission original by the scanner 41 is transmitted via the system bus. The image memory 42. The image data written in the image memory 42 is read out, encoded by the encoder 43 via the system bus, and transmitted to the partner facsimile by the communication interface 48. When receiving by facsimile, the image data received by the communication interface 48 is decoded by the decoder 44 via the system bus, printed by the printer 45, and output. These operations are performed by a CPU (central processing unit) 47 using a program from the main memory ROM 46. Various configurations of the facsimile are conceivable. For example, the bus configuration may be divided into a system and an image, an image memory and a main memory may be shared, and a display may be provided.

[0035]

As described above, according to the present invention, the number of consecutive pixels of the target pixel color is detected by performing the coincidence detection of the pixels of the predetermined number of bits at once by the same color pixel detection means. Therefore, it is possible to shorten the coincidence detection time and the count time of the pixels of the image data to be encoded,
High speed processing can be enabled.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of the present invention.

FIG. 2 is a configuration explanatory view showing an example of a pixel detection unit in FIG.

FIG. 3 is an explanatory diagram showing an example of input and output of the pixel detection unit of FIG.

FIG. 4 is a structural explanatory view showing another embodiment of the present invention.

5 is a circuit diagram showing an example of an image data comparison unit in FIG.

6 is a circuit diagram showing an example of a selector shown in FIG.

FIG. 7 is an explanatory diagram for explaining the operation of the adder in FIG.

FIG. 8 is an explanatory diagram for explaining the operation of the address memory in FIG.

FIG. 9 is a configuration explanatory view showing a system application example using the present invention.

FIG. 10 is a structural explanatory view showing a conventional binary image compression device.

FIG. 11 is an explanatory diagram of a configuration showing an example of a mismatch detection unit.

[Explanation of symbols]

21 ... Image RAM, 22 ... Flip-flop, 23 ... Barrel shifter, 24 ... Pixel detector, 25 ... Adder, 26 ...
Selector, 27 ... Counter, 28 ... OR circuit, 29 ... Counter, 30 ... Code ROM (terminator), 31 ... Code ROM (makeup), 32 ... Mismatch detection section, 33 ...
Selector, 34 ... selector, 35 ... inverter, 36 ...
Priority encoder, 41 ... Scanner, 42 ... Image memory, 43 ... Encoder, 44 ... Decoder, 45 ... Printer, 46 ... Main memory ROM, 47 ... CPU, 4
8 ... Communication interface.

Claims (3)

[Claims] 1. A coincidence detecting means for detecting coincidence of pixel data of a predetermined bit with a previous pixel for each bit, a counting means for counting coincidence output of the coincidence detecting means, and a count value of the counting means. In a binary image compression apparatus having a coding means for outputting a predetermined code, a continuous pixel detecting means for detecting the number of continuous pixels of continuous pixels in the pixel data of predetermined bits, and the continuous pixel detecting means for detecting the continuous pixel number. A binary image compression apparatus, further comprising: an addition unit that adds the number of continuous pixels to the count value of the counting unit. 2. A shift means which holds a predetermined number of bits of pixel data and shifts by 1 bit from a predetermined position, 1-bit pixel data output from this shift means, and pixel data 1 bit before this pixel data. A coincidence detecting means for detecting a coincidence with the coincidence detecting means, a counting means for counting the coincidence output detected by the coincidence detecting means, and an encoding means for outputting a predetermined code corresponding to the count value of the counting means. In the value image compression apparatus, continuous pixel detection means for detecting the number of continuous pixels of continuous pixels of pixel data of predetermined bits, and the number of continuous pixels detected by the continuous pixel detection means is added to the count value of the counting means. And a shift unit that shifts the pixel data by the number of consecutive pixels detected by the consecutive pixel detecting unit. A binary image compression apparatus characterized by: 3. A shift means for holding a predetermined number of bits of pixel data and shifting from a predetermined position by 1 bit, 1-bit pixel data output from the shift means, and pixel data 1 bit before this pixel data. A coincidence detecting means for detecting a coincidence with the coincidence detecting means, a counting means for counting the coincidence output detected by the coincidence detecting means, and an encoding means for outputting a predetermined code corresponding to the count value of the counting means. In the value image compression device, a continuous pixel detecting means for detecting the number of continuous pixels of pixels of which one byte or more is continuous in the pixel data of a predetermined bit, and the number of continuous pixels detected by the continuous pixel detecting means is counted by the counting means. Adding means for adding the value to the value, and the shift means is configured to add the pixel data for the number of consecutive pixels detected by the consecutive pixel detecting means. A binary image compression apparatus characterized by shifting data.