JP2586143B2 - MH expansion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MH expansion circuit in a compression / expansion circuit used for a facsimile.

[Conventional technology]

Conventionally, G3 facsimile employs an MH (Modify Huffman) method as compression / decompression of image data.
This method is an entropy coding using a Huffman code. A code having a small number of bits is given to a value having a high occurrence probability, and a code having a relatively large number of bits is given to a value having a low occurrence probability.

In the case of facsimile, this code is stipulated in CCITT (International Telegraph and Telephone Consultative Committee) T4, Table 1 (a),
It is divided into a terminating code (T code) and a make-up code (M code) as shown in (b). In the case of facsimile transmission, compression is performed using this code, and the timing chart of FIG. Is transmitted. In the case of reception, the M code and the T code are separated from the received data, and the decompression process is performed based on the result.

[Problems to be Solved by the Invention] As described above, in the G3 facsimile or the like, the compression / expansion of the MH image data is performed. Most of the processing is performed, and the decompression processing time is long, and as a result, the communication time is long.

An object of the present invention is to simplify a decoding circuit of an MH compression code,
An object of the present invention is to provide an MH code decompression circuit that realizes high-speed processing by shortening the processing time.

[Means for solving the problem]

The configuration of the MH decompression circuit according to the present invention includes a byte register that receives received data and holds the data on a byte-by-byte basis, a shift register that shifts data from the byte register one bit at a time by a command, and a data stored in the shift register. When 0 within 8 bits is detected, the command is output to the shift register, and when 1 is detected in the data, the command is stopped and the initial table data is obtained from the following formula.
A control circuit for outputting a TD and an initial index address _{TA 1, TD = 2N + M} , TA 1 = TP + TD ...... (1) However, N is the number of 0 up to detect the data 1, M is the next data of the data 1 , TP is the leading index address of the decoding table.

An MH decoding table composed of a ROM table stored in advance for performing MH decompression corresponding to the index address, and data from the data received from the control circuit.
A signal inverting circuit for inverting 1,0 and outputting to the decoding table, and data decodable from the output code of the MH decoding table output corresponding to the output of the signal inverting circuit and the index address. a data generation circuit for returning the data to the control circuit at the time of 64-fold and output to the sum output as decompressed data undecodable data TD _n is the data at the time of the terminating code when the make-up code when certain a, the control circuit, the data generation reads the decoding table again seeking index address TA ₂ from the table data TD _n returned from the circuit by the following equation _{TA 2 = TA 1 + TD n} ...... (2 This processing is repeated until the read data becomes decompressible.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a system configuration showing an embodiment of the present invention. The byte register 1 latches received data already compressed by the MH system in units of one byte, and is connected to the shift register 2. The shift register 2 operates in conjunction with the control circuit 6 and the MH decoding table 3. The shift register 2 sends the data from the byte register 1 to the control circuit 6 bit by bit, clears the data by shifting one byte, and resets the data from the byte register 1 again. Is to read the data.

The MH decoding table 3 is a ROM table in which data used at the time of decompression is stored, and has two ROMs for white and black.
These are selected by a signal from a monochrome inversion circuit 4 as a signal inversion circuit.

Since the received data is performed in the order of white and black, the white / black inversion circuit 4 sends white and black signals to the MH decoding table 3 and the pixel generation circuit 5 as a data generation circuit in this order. The pixel generation circuit 5 receives the signal from the monochrome inversion circuit 4 and the MH
The decompressed data is generated based on the data from the decoding table 3, and the decompressed data is not transmitted to the control circuit 6.

The control circuit 6 receives data 1 from the shift register 2,
The index address is given to the ROM of the MH decoding table 3 based on the result of detecting 0 and performing the operation in accordance therewith and the result of operating the data from the pixel generation circuit 5 that has not been generated. .

Next, the operation of the decompression circuit thus configured will be described in detail with reference to the flowcharts of FIGS.

First, as shown in FIG. 2, the MH decompression process starts with one line in step 11 starting with white processing, then repeats black processing in step 13 and white processing in step 15 until one line is completed. The same operation is continued until one page is completed.

FIG. 3 shows the white (black) decompression processing of FIG. 2 in detail, and the processing is performed in the following order.

(1) One byte of received data is input to the byte register 1 (step 21), and after latching, the shift register 2 sends the received data to the control circuit 6 bit by bit.

(2) The control circuit 6 detects the received data 1 and 0 in Step 22 and, if eight or more 0s are consecutive (Step 23),
EOL or NULL processing is started (step 24). If there is data 1 within that, the next received data is shifted by one bit in step 25, shift register 2 is stopped, the next operation is performed, and initial table data TD and initial The decoding index address TA1 is obtained, and the index address is given to the MH decoding table 3.

TD = 2N + M (1) At this time, N is the number of data 0 (0 ≦ N ≦ 7) until reception data 1 is detected, and M is the next data (0, 1) after reception data 1 is detected. TA1 = TOP + TD (2) At this time, TOP is the first index address of the white and black decoding table. (3) The MH decoding table 3 outputs the data selected by this index address.

(4) The pixel generation circuit 5 checks the data from the MH decoding table 3 according to FIG. 4 (steps 31 and 3).
4) If the data can be decompressed, it is decompressed here. If it is an M code, the data is multiplied by 64 (step 35). If it is a T code, the data is output as it is (step 37). End as data (step
38).

If the table data (TDn) cannot be expanded, the table data is sent to the control circuit 6, and the intermediate decoding index address TA
2 is obtained (step 32), and an index address is given to the MH decoding table 3 (step 33).

TA2 = TA1 + TDn (3) (5) The MH decoding table 3 outputs the data selected by the index address to the control circuit 6.

(6) The control circuit 6 checks the data from the MH decoding table 3 and determines how many bits of the next received data are to be received. The shift register 2 is operated so as to receive the bits, and the received data is added to TA2 and data 1 to obtain a decoding index address TA3.
Send to H decoding table 3.

(7) The MH decoding table 3 outputs the data selected by this index address.

(8) The pixel generation circuit 5 checks the data from the MH decoding table 3 as shown in (4) according to FIG.
The operation from (4) is repeated until it can be extended.

Here, a case where white 94d (d means a decimal decimal number) is expanded will be described as an example.

The MH-compressed white 94d is represented by white 94d = white 64d + white 30d. This is because the M code (11011) and the T code (000
00011) is transmitted as transmission data.

Since white 64d is N = 0 and M = 1 from equation (1), TD
= 1h (h means a hexadecimal hexadecimal number). Since TOP is 0h at first, TA1 = 01h is obtained from equation (2). This TA1 is given to the MH coding table 3 as an index address, and 14h (00010100) is sent to the pixel generation circuit 5 as data stored in the white ROM table shown in Table 2 below.

Since 14h sent to the pixel generation circuit 5 is the table data TDn which cannot be decompressed from the check in FIG. 4, it is sent to the control circuit 6, and TA2 = 15h is obtained from the equation (3). This TA2
Since the data of = 15h is 02h, TA3 = 17h, and the data at this time is 31h (00110001).

Since this data is also non-decompressible table data TDn, it is sent to the control circuit 6 again to obtain TA2 = 48h from equation (3). Since this data is 01h, TA3 = 4Ah.

Since the data of TA = 4Ah is C1 (11000001), it is determined to be an M code from FIG. 4, and bits other than the determination bit (000001 in this case) are multiplied by 64 to obtain 64d.

Similarly, for white 30d, N = 6 and M = 1 from equation (1), so that TD = Dh. Since TOP is initially 0h, TA1 is obtained from equation (2).
= 0DH. This TA1 = 0DH data is 9Eh (1001111
0), it is determined as a T code from FIG. 4, and the remaining bits 11110 = 1Eh = 30d are obtained.

The pixel generation circuit 5 adds 64d + 30d thus obtained, outputs the result as decompressed data 94d, and ends the processing.

[Effects of the Invention] As described above, the decompression circuit of the present invention decodes from a predetermined table using the features of the white run and black run of the compressed T code and M code. It can be reduced, the decompression process can be performed at high speed,
As a result, the communication time can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention, FIGS. 2 and 3 are flowcharts for explaining the operation of the system of FIG. 1, and FIG. 4 is a pixel generation circuit 5 of FIG.
FIG. 5 is a timing chart showing the state of the MH-compressed received data. 1 ... byte register, 2 ... shift register, 3 ...
MH decoding table, 4... Monochrome inverting circuit, 5... Pixel generating circuit, 6... Control circuit, 11 to 18, 21 to 38.

Claims (1)

(57) [Claims] 1. A byte register for receiving received data and holding the data on a byte-by-byte basis, a shift register for shifting data from the byte register one bit at a time by a command, and a 0 bit within 8 bits from the data of the shift register. A control circuit that outputs the command to the shift register when the data is detected, and stops the command when the data is detected as ₁ to output the initial table data TD and the initial index address TA1 from the next arithmetic expression; = 2N + M, TA ₁ = TP + TD (1) where N is the number of 0s until data 1 is detected, M is the data following data 1, and TP is the leading index address of the decoding table. An MH decoding table composed of a ROM table stored in advance for performing MH decompression in accordance with the index address, and 1 and 2 of data from data received from the control circuit.
A signal inverting circuit that inverts 0 and outputs the result to the decoding table; and data that can be decoded from the output code of the MH decoding table output in accordance with the output of the signal inverting circuit and the index address. when the 64-fold and the terminating undecodable data TD _n adds output as decompressed data and outputs the data when the code at the time of make-up code in has a data generating circuit for returning the data to the control circuit , the control circuit, the data generated was returned from the circuit said table data TD _n reads out the decoding table again seeking index address TA ₂ by the following equation from the _{TA 2 = TA 1 + TD n} ...... (2) the An MH decompression circuit wherein this process is repeated until the read data can be decompressed.