GB2269507A

GB2269507A - Coding a video signal to facilitate aspect ratio conversion

Info

Publication number: GB2269507A
Application number: GB9302408A
Authority: GB
Inventors: Joo Han Kwon
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1992-06-17
Filing date: 1993-02-08
Publication date: 1994-02-09
Anticipated expiration: 2013-02-08
Also published as: GB2269507B; GB9302408D0; KR0147551B1; DE4307418C2; DE4307418A1; KR940001721A

Abstract

A pan vector code is transmitted on line 625 of a D2-MAC signal. In a receiver, the pan vector code is processed by a pan vector data reader 200 and a pan vector data converter 300 to generate start addresses for reading luminance and chrominance signals from respective memories 600, 700. The memories 600, 700 contain all the data for a full 16:9 aspect ratio picture. However, the pan vector code controls the reading of the memories such that only data corresponding to a 4:3 aspect ratio portion of the picture is read out for display on the conventional television screen. <IMAGE>

Description

2269507 TELEVISION SIGNAL AND RECEIVER THEREFOR

DESCRIPTION

The present invention relates to a television signal and receiver therefore for enabling a television picture, having a first aspect ratio, to be displayed on a display having a second aspect ratio. The present invention has particular, though not exclusive, application to the display of 16:9 aspect ratio D2 MAC pictures on a conventional 4:3 aspect ratio television display.

In the D2 MAC broadcasting system sound and picture signals are time division multiplexed on each line.

The picture signal is transmitted after being divided into a luminance signal and a chrominance signal. The luminance signal is transmitted in every line. The chrominance signal, however, is divided into a U signal (B-Y) and V signal (R-Y) which are transmitted in alternate lines. 1 - 2 The D2-MAC broadcasting system is suitable for transmitting pictures having a 16:9 aspect ratio as well as those having the conventional 4:3 aspect ratio.

If a television receiver tube has a 16:9 aspect ratio, a picture signal of 16:9 aspect ratio can be displayed without any loss of information contained in the transmitted signals. However, in the case of a television receiver having 4:3 aspect ratio tube, not all the information contained in the transmitted signal is displayed since the original signal of 16:9 aspect ratio cannot be completely displayed.

Figures 1A and 1B show transmitting and receiving apparatus. as disclosed in Japanese laid-open publication No. 62-299185, in which a television receiver having 4:3 aspect ratio display receives picture signals having an aspect ratio larger than 4:3.

Referring to Figure 1A, a television signal generator comprises a picture separation circuit 2 for dividing the original picture signal into a main picture signal and a sub-picture signal; a cartesian conversion 1 3 circuit 3 for dividing the sub-picture signal into a lowband sub-picture signal and a highband sub-picture signal by cartesian conversion, a time domain multiplexing circuit 4 for multiplexing the lowband sub-picture signal with the main picture signal in the time domain, and a frequency domain multiplexing circuit 5 for multiplexing the highband sub-picture signal with the main picture signal in the frequency domain.

The television signal generator divides an original picture signal with aspect ratio larger than 4:3 into a main picture signal and a sub-picture signal, groups the sub-picture signal into an m x n block, divides the result into a lowband sub-picture signal and a highband sub-picture signal.

The television signal generator then generates the television signal by multiplexing the lowband sub-picture signal with main picture signal in the time domain and multiplexing the highband sub-picture signal with the main picture signal in frequency domain.

At the receiving end, the exact reverse of the above described process is carried out to enable display of the original picture signal of aspect ratio larger than 4:3 on a television screen of 4:3 aspect ratio.

However, the laid-open Japanese publication No.

62-299185 relates to retrieval of an original picture signal having aspect ratio larger than 4:3 on a screen of 4:3 aspect ratio by signal separation and cartesian conversion in the transmitting apparatus, and more specifically only to retrieval of a picture signal of aspect ratio larger than 4:3 on a NTSC television receiver of 4:3 aspect ratio.

is Ac--irding to of a first aspect of the present invention, there is provided a television signal arranged to generate a picture, with a first aspect ratio of greater than a second aspect ratio, including a code for indicating a region of the picture of said second aspect ratio for display on a television display of said second aspect ratio.

Preferably, the television signal is a D2 MAC signal.

The code may occur in any non-picture and non-sound portion of the television signal. However, preferably it occurs in line 625.

According to a second aspect of the present invention, there is provided a television receiver for receiving a television signal according to the first aspect of the present invention, comprising memory means for storing a picture and reading means responsive to said code to read a second aspect ratio portion of said picture from the memory means.

is Preferably, the reading means is responsive to said code to read each line of the picture from a horizontal pixel position defined thereby.

Preferably, the reading means includes adder means for adding a constant to said code to generate the start address for reading each line of the picture from the memory means.

According to the first aspect of the present invention, there is provided a television transmitter for transmitting a signal according to any one of claims 1 to 4, comprising means for adding said code to a picture signal.

Thus, as a result of the present invention, it is possible to display a picture signal having a 16:9 aspect ratio on a screen of 4:3 aspect ratio by cutting out part of the picture signal of 16:9 aspect ratio. A picture signal of 16:9 aspect ratio-may be reproduced with an aspect ratio of 12:9 (i.e. 4:3), by cutting out four horizontal units of each line, where the original line length is taken as 16, and leaving the height of the picture at its original height.

In the D2-MAC system. the sampling frequencies of the luminance and chrominance signals are 697 and 349 per line respectively. In the present invention, the sampling frequency would be reduced to twelve sixteenths of the original frequency, i.e. 523 per line for the luminance signal and 262 per line for the chrominance signal.

7 - Figures 1A and 1B show block diagrams of the transmitting and receiving apparatus of a known television system; Figure 2 shows the composition of an original picture signal, as input in the apparatus shown in Figure 1A; Figure 3 shows a generic waveform on an IM bus; Figure 4 is a block diagram showing a pan vector interface circuit for displaying a 16:9 picture signal on a 4:3 screen according to the present invention; and 15 Figure 5 shows a circuit diagram of Figure 4. Referring to Figure 4, a microprocessor, for providing pan vector addresses and pan vector data on a data line M. based on the logic status of a identity ID signal 20 on the ID line, and a clock signal on the IM bus, is connected to a pan vector address decoder 100 for the pan vector address, received over the IM bus, to be decoded.

A pan vector data reader 200 is connected to the data line DL of the microprocessor and the address decoder 100, and reads the pan vector data from the data line DL from the least significant bit MB, if the pan vector address decoded by the address decoder 100 is matched to the address as received from the television transmitter. A pan vector data converter 300 for converting the pan vector data read from the pan vector data reader into a pan vector value for luminance and chrominance signals suitable for a 4:3 screen is connected to the pan vector data reader 200, and luminance and chrominance signal sample counters 400, 500 for sampling the luminance and chrominance signal at the frequency of 523 per line and 262 per line out of the original 697 and 349 samples per line respectively of D2 MAC system, in accordance with the pan vector for luminance and chrominance signals, suitable for a 4:3 screen received from the pan vector data converter 300. are connected to the pan vector data converter 300.

9 Luminance and chrominance signal memories 600, 700 for providing luminance and chrominance signals stored in the addresses generated by the luminance and chrominance signal sample counters 400,500 are connected to the luminance and chrominance signal sample counters 400,500.

Referring to Figure 3, ID is changed to low or high state after every 8 clocks. When ID is low, signals received over the data line DL are interpreted as 8 bit serial addresses and when ID is high, the signals are interpreted as data.

Referring to Figure 5. a bit matching circuit 110 for is detecting that a predetermined bit pattern has occurred on the data line M. The bit matching circuit 110 comprises a shift register SR1, a number of inverters INV1-INVS for detecting that an address input into the shift register SR1 corresponds to a pan vector address, NAND1,, gates NAND1 and NAND2 connected to the inverters, and a NOR gate NOR1 connected to the NAND gates, such that the NAND gates and NOR1 gate function as a normal AND gate. The output of the NOR gate NOR1 is connected to a D-type flip-flop DFF1 that outputs a high signal when the address input into the shift register corresponds to the pan vector. The inverter INV1 output and the clock CLK are also fed to a counter 120 for supplying a clear pulse to the D-type flip-flop DFF1 through another NAND gate, NAND3.

The pan vector data reader 200 includes another shift register SR2, whose clear CLR pin is connected to the output of D-type flip-flop DFF1, for providing shifted pan vector data while the output of the D-type flip-flop DFF1 is high. The clock CLK1 and the output of the AND gate AND1 are connected to a counter 210 that stops counting as soon as all the outputs QOQ7 of is the shift register SR2 have indicated. The shift register SR2 and the counter 210 are connected to a latch 220 for latching the output of the shift register SR2 and for providing the latched data when the counting by the counter 210 has stopped.

The pan vector data converter 300 comprises pan vector data converters 310, 320 for converting the pan vector data read from the pan vector data reader 200 into pan vectors for luminance and chrominance signals suitable for a 4:3 screen. Each of the pan vector data converters 310, 320 comprises two 8-bit full adders 311, 312, 321, 322.

The present invention as described above, outputs luminance and chrominance signals based on the pan vectors for a 4:3 screen after reading the pan vector address and data. When ID is low, signals received over data line DL of the IM bus are interpreted as 8-bit serial addresses; when ID is high, the signals are interpreted as data. In the following description of an embodiment of the present invention, it is assumed that the pan vector from the microprocessor is sent over the IM bus with a specific address 1,1010010111 in which the first digit is the least significant bit MB and the last digit is the most significant bit MSB.

When the address is input in the pan vector address decoder 100 over the IM bus. the pan vector address decoder 100 should read in all of the 8 bit serial data from the data line while the ID signal is low, and judge if it is the desired address, i.e. 1,1010010111.

Since the ID signal is input in the clear CLR pinof the shift register SR1 after being inverted through the INV1, the shift register SR1 is enabled while the ID signal is low. The data inputs at the pins A and B of the shift register SR1 are shifted at every rising edge of the clock pulse IMCLK input at the clock CLK pin of the shift register SR1, and the result of the shift operation is output to pins QO-Q7. Therefore, while the ID signal is low, the LSB will be output to pin Q7 and the MSB to pin QO after 8 successive rising edges of the clock IMCLK have occurred at the CLK pin of the SR1. At this time, if the data of Q1-Q7 is 1,1010010111, the output of the bit matching circuit becomes high and a rising edge is detected at the CLK pin of the D-type is flip-flop DFF1 such that the output Q of the D-type flip-flop.DFF1 changes to high from low.

Since the D-type flip-flop DFF1 must be reset during the ID low period in order to perform this operation with precision, the counter 210 output Q generates a clear pulse for the D-type flip-flop DFF1 at the third rising edge of the clock IMCLK from the clock pin CM.

The address is judged to be matched when the output Q of the D-type flip-flop DFF1 is high. Then. the output Q of the D-type flip-flop DFF1 is applied to the clear CLR pin of the shift register SR2 of the pan vector data reader 200 to prepare for reception of pan vector data over the data line DL of the IM bus. The pan vector data signal is input in the shift register SR2, and the shift register SR2 outputs the MB of the pan vector data from its pin Q7.

As soon as all the bits of the 8 bit data have appeared at the output of the shift register SR2, a rising edge of a clock pulse is detected at the clock pin CLK of the latch 220. At this time. the 8 bit full adders is 311, 312 of the chrominance signal pan vector data converter 310 output 44 (decimal) or 1101010111" (binary) to PCO-PC7 as the pan load value for the chrominance signal; the 8 bit full adders 321, 322 of the luminance signal pan vector data converter 320 multiply the pan load value at PCO-PC7 by 2 and then subtract 1 from the result to get 87 (decimal) or "0101011111 as the pan load value for the luminance signal output to PYO-PY7, of which the last digit is the MB and the first digit is the MSB.

The reason for adding 44 for the chrominance signal and 87 for the luminance signl at the pan vector data converters 310, 320 is that a 16:9 picture can be displayed on a 4:3 screen without loss of information only if the luminance signals are scanned starting from the 44th pixel and the chrominance signals from the 87th pixel and the pan vector value is 0 at the center of the 4:3 screen.

Therefore, the binary value obtained at the outputs PYO-PY7 of the luminance signal pan vector data converter 320 is used as the starting address of the luminance signal sample counter 400 for selecting 523 samples out of 697 luminance signal samples, using the pan vector data received over the IM bus and the binary value obtained from the outputs PCO-PC7 of the chrominance signal pan vector data converter 310 is used as the starting address of the chrominance signal sample counter 400 for selecting 262 samples out of 349 luminance signal samples, using the pan vector data - 15 received over the IM bus. Beginning from the starting address, luminance and chrominance signal memories 600, 700 are output to the 4:3 screen.

As described above, the present invention enables, for example, display of a picture of 16:9 aspect ratio on a television screen of 4:3 aspect ratio by transmitting on line 625 of the D2-MAC broadcasting signals at the transmitting end, a pan vector containing information 10 on which pixel the picture begins to be displayed at; by receiving and decoding the pan vector from line 625 at the receiving end; by selecting only 523 luminance signal samples and 262 chrominance signal samples, or only the numbers corresponding to 12/16 (the ratio of 15 horizontal lengths between' 16:9 picture and 4:3 picture, if the vertical length of.the latter is made the same as that of the former) times the original numbers of samples, out of the originally transmitted 697 luminance signal samples and 349 chrominance signal 20 samples, using the pan vector for displaying a 16:9 picture on a 4:3 screen; and by retrieving for display only the selected luminance signals and chrominance signals that are suitable for display on a 4:3 screen - 16 from the luminance and chrominance signal memories 600,700, using output signals PCO-PC7 and PYO-PY7 of the luminance and chrominance signal pan vector converter 310,320.

As described above, the present invention has the advantage of displaying a 16:9 picture on a 4:3 screen without any loss of resolution from the transmitted-original signal, by generating a pan vector corresponding to the conventional 4:3 screen, when a 16:9 picture is transmitted in the D2-MAC system that can broadcasting both a 4:3 picture and a 16:9 picture.

From the foregoing, the skilled man will readily is conceive of a circuit embodying a transmitter according to the third aspect of the present invention.

17 -

Claims

1. A television signal arranged to generate a picture, with a first aspect ratio of greater than a second aspect ratio, including a code for indicating a region of the picture of said second aspect ratio for display on a television display of said second aspect ratio.

2. A television signal according to claim 1, wherein the second aspect ratio is 4:3.

3. A television signal according to claim 1 or 2.

having the essential characteristics of a D2 MAC is signal.

4. A television signal according to claim 1, 2 or 3, wherein the code occurs in line 625.

5. An apparatus for receiving a television signal according to any preceding claim,' comprising memory means for storing a 'picture and reading means responsive to said code to read a second aspect ratio portion of said picture from the memory means.

6. An apparatus according to claim 5, wherein the reading means is responsive to said code to read each line of the picture from a horizontal pixel position defined thereby.

7. An apparatus according to claim 6, wherein the reading means includes adder means for adding a constant to said code to generate the start address for reading each line of the picture from the memory means.

is

8. A television transmitter for transmitting a signal according to any one of claims 1 to 4, comprising means for adding said code to a picture signal.

9. In a D2-MAC receiver, a pan vector interface circuit for displaying a 16:9 aspect ratio picture D2-MAC signal on a 4:3 screen, comprising:

a microprocessor for providing clock signal, pan vector 19 - data and address of pan vector onto a IM bus; a pan vector address decoder connected to said microprocessor, for decoding said address of pan vector received from the IM bus; a pan vector data reader connected to said microprocessor and said address decoder, for reading said pan vector data from data lines beginning from the least significant bit, when the decoded address of pan vector matches the address as received from the transmitting end; a pan vector data converter connected to said pan vector data reader, for converting the pan vector data read by the pan vector data reader into pan vectors for luminance and chrominance signals suitable for a 4:3 screen; luminance and chrominance signal - sample counters connected to said pan vector data converter, for sampling the lumiannce and chrominance signal at the frequency of 523 per line and 262 per line, in accordance with the pan vector for luminance and chromiannce signals suitable for a 4:3 screen receiveed from said pan vector data converter; and luminance and chromiance signal memories connected to said luminance and chrominance signal sample counters. for providing luminance and chrominance signals stored in the addresses generated by said lumiance and chrominance signal sample couters.

10. A pan vector interface circuit for displaying a 16:9 picture D2-MAC signal on a 4:3 screen as described in claim 9, whose pan vector address decoder comprises: a shift register for shifting data input at every rising edge of the clock input enabled during the low status of identity input; a bit matching circuit connected to said shift register, for matching the input data with the output data; a D flip-flop, connected to said bit matching circuit, that outputs a high signal when the address input corresponds to an address for pan vector; and a counter connected to the clock pin and the identity line, for supplying a clear pulse to the D flip-flop.

11. A pan vector interface circuit for displaying a 16:9 picture D2-MAC signal on a 4:3 screen as described in claim 9, whose pan vector data reader comprises:

21 - a shift register connectedto said D flip-flop, for providing shifted pan vector data after shifiting the pan vector data input while the output of the D flip-flop is high; and a counter, connected to said clock pin and said pan vector decoder, that stops counting as soon as all of the outputs have appeared; and a latch, connected to said shift register and said counter, for providing data from said shift register when counting of said counter is stopped.

12. A pan vector interface circuit for displaying a 16:9 picture D2-MAC signal on a 4:3 screen as described in claim 9, whose pan vector data converter comprises:

luminance signal and chrominance signal pan vector data converters, connected to said pan vector data reader, for converting pan vector data read by said pan vector data reader into pan vectors for luminance and chrominance signals usitable for a 4:3 screen.

13. A pan vector interface circuit for displayinga 16:9 picture D2-MAC signal on a 4:3 screen as described in claim 12, whose luminance signal and chrominance signal pan vector data converters comprise: full adders and full adders respectively.

14. A circuit for a television receiver substantially as hereinbefore described, with reference to Figures 3, 4 and 5 of the accompanying drawings.