DE4307418C2 - D2-MAC receiver with a pan vector interface circuit - Google Patents

Description

The present invention relates to a D2-MAC Receiver for receiving D2-MAC signals and in particular on a pan (panorama) vector interface circuit for Playback of multiplex analog component (MAC) image signals with an aspect ratio of 16: 9 on a conventional TV (TV) receivers with an aspect ratio of 4: 3 so that when television signals with an aspect ratio of 16: 9 used in the D2 MAC system in Europe, this Signals from a conventional television with a 4: 3 aspect ratio using this circuit can be received.

Since the internationally used transmission systems such as NTSC, PAL and SECAM often show a cross color effect caused by the fact is caused that the luminance and Chrominance signals were transmitted on the same line  developed the D2-MAC transmission system, which transmits the luminance and chrominance signals separately.

In the D2-MAC transmission system mainly used in Europe the audio and video signals are time-division multiplexed transferred in one line. The image signal is divided into Luminance signal and chrominance signal transmitted. The luminance signal is sent for each line. The chrominance signal will divided into a U-signal B-Y and a V-signal R-Y, which on every second line.

Furthermore, in the D2 MAC transmission system, images with a Aspect ratio of 16: 9 and also images with one Aspect ratio of 4: 3 can be displayed. At a TV receivers with an aspect ratio of 16: 9 can an image signal with an aspect ratio of 16: 9 without Loss of information contained in the transmitted signals are reproduced.

However, in the case of a television receiver with a Aspect ratio of 4: 3 not the whole in which transmitted signal contained information, since that Original signal with the aspect ratio of 16: 9 not completely without loss of information on the screen can be played.

. Figs. 3A and 3B show a method for generating a television signal at the transmitter and receiver side, as disclosed in Japanese Unexamined Patent Publication No. 62-299185, in which a television receiver having an aspect ratio of 4:. 3 image signals with an aspect ratio receives greater than 4: 3.

As shown in Fig. 3A, the signal generator includes an image separation circuit 2 for dividing the original image signal into a main image signal and a sub-image signal; a Cartesian converter circuit 3 for dividing the sub-picture signal into a low-band sub-picture signal and a high-band sub-picture signal by Cartesian conversion; a time division multiplexing circuit 4 for mixing the low-band sub-picture signal with the main picture signal in the time domain; and a frequency division multiplexing circuit 5 for mixing the high band sub-picture signal with the main picture signal in the frequency domain.

The television signal generator shares an original picture signal with an aspect ratio greater than 4: 3 in Main picture signal and a sub picture signal orders that Sub picture signal in mxn blocks and divides after one Cartesian conversion of each of the mxn blocks the result in a low-band sub-picture signal and a high-band Sub-picture signal on.

The television picture generator then generates a television signal by he the low-band sub-picture signal with the main picture signal in Time range mixes and the high-band sub-picture signal with the Main picture signal mixes in the frequency domain.

On the receiving end there is an exact reversal of the above described procedure performed on the transmitter side to the Representation of the original image with a Image aspect ratio greater than 4: 3 on a screen with to allow an aspect ratio of 4: 3.  

However, the Japanese laid-open publication refers No. 62-299185 on the recovery of an original Image signal with an aspect ratio greater than 4: 3 on one Screen with an aspect ratio of 4: 3 by signal separation and Cartesian conversion on the receiving end and in particular only on the recovery of an image signal with an aspect ratio greater than 4: 3 on one NTSC receiver with an aspect ratio of 4: 3 summarizes this publication deals with an image wall procedure in the frequency domain.

From German patent application DE 40 02 588 A1 is a Letter box television receiver known. The additional for the Play a TV picture with an aspect ratio of 16: 9 information transmitted in a 16: 9 television receiver (Helper) is reduced in amplitude by the additional transmitted information when playing the transmitted Image with an aspect ratio of 16: 9 on one Standard television receiver with an aspect ratio of 4: 3 make invisible. This also makes the information amount that can be transmitted in the helper signal reduced. It is the job of this application described invention, the amount of additional transferable To increase information. This is the amplitude of the helper signals not reduced as conventional. To nevertheless the Visibility of the transmitted information during playback an image with the aspect ratio 16: 9 on one Standard television receiver with the aspect ratio 4: 3 too decrease, the one transmitted in the "Side Panels" Information converted so that for the viewer in it Only noise appears to have been transmitted to areas.  

The present invention is based on reading of an image signal and its processing in the time domain directed by interpolation on the receiver side in case of Broadcast an image signal with an aspect ratio of 16: 9 in a D2-MAC transmission system or the like, in which the Image signal is sent with a time division.

It is therefore the object of the present invention Receiving an image signal with an aspect ratio of 16: 9 on a screen with a 4: 3 aspect ratio possible by putting part of the picture with the aspect ratio is cut away from 16: 9 and in particular by using a pan vector Interface circuit for displaying a MAC image signals with an aspect ratio of 16: 9 on a television screen with an aspect ratio of 4: 3 is provided, so that a MAC image signal with an aspect ratio of 16: 9 on a television screen with an aspect ratio of 4: 3 can be represented by the pan vector on line 625  of the MAC image signal is sent on the transmitter side and the Pan vector is decoded on line 625 of the receiver side.

This task is carried out by the in the circuitry solved.

In the present invention, an image with a Aspect ratio of 16: 9 by an image with one image side ratio of 12: 9 (i.e. 4: 3) reproduced by the ho horizontal length 4 units (= 16-12) of the original Length of 16 units is cut away and the Image height is left at the original image height, so that the Image with an aspect ratio of 16: 9 on a screen can be displayed with an aspect ratio of 4: 3. In the D2-MAC system the sampling frequencies for the luminance and chrominance signals 697 per line and 349 per Row; however, in the present invention, the scan frequency reduced to 12/16 of the original frequency, So to 523 per line for the luminance signal and 262 per Line for the chrominance signal since the original picture pages ratio should be changed from 16: 9 to 12: 9. Furthermore becomes a pan vector that contains the information when the Sampling the luminance and chrominance signals for one line should start to the original image without loss of to represent information contained in the image, the line 625 of the image signal superimposed. Line 625 appears on the Receiver side decodes to an image with an aspect ratio 16: 9 on a screen with an aspect ratio of 4: 3 completely and without loss of included in the picture to present tener information.  

To achieve the above object, the present invention is characterized by a pan vector interfaces Circuit for displaying an image signal with an image page 16: 9 ratio on a screen with one image pages 4: 3 ratio and includes: a microprocessor for generation a clock signal, pan vector data and addresses of the Panvectors on an IM bus standard, which is one of the in Europe is used bus systems; a pan vector address encoder connected to the microprocessor for De encode the address of the pan vector obtained from the IM bus; a pan-vector data reader that works with the microprocessor and connected to the address encoder for reading the pan vector data from data lines, with the least significant Bits is started when the decoded address of the Panvectors with the address received from the transmitter side matches; a pan-vector data converter that works with the Pan vector data reader is connected to convert the pan vector data read by the pan vector data reader in pan vectors for luminance and chrominance signals, the for a screen with an aspect ratio of 4: 3 ge are suitable; Luminance and chrominance signal sampling counters connected to the pan vector data converter for scanning of the luminance and chrominance signals with a frequency of 523 per line and from 262 per line according to the pank vector for a screen with an aspect ratio of 4: 3 suitable luminance and chrominance signals, which by the Pan-vector data converters can be obtained; and luminance and Chrominance latches using the Luminance and Chromi  scan counters are connected to luminance and chromi to provide nance signals that correspond to those of the luminance and addresses generated from chrominance scan counters are.

Fig. 1 shows a block diagram of a pan vector interface circuit according to the present invention for displaying an image signal with an aspect ratio of 16: 9 on a screen with an aspect ratio of 4: 3.

FIG. 2 shows a detailed circuit diagram of FIG. 1.

FIGS. 3A and 3B show a block diagram of a general television signal generator at the transmitter and the receiver side.

Fig. 4 shows the composition of the original image signal as it will enter in the block shown in Fig. 3A.

Figure 5 shows a standard waveform on the IM bus.

Fig. 1 shows a block diagram of a pan vector interface circuit according to the present invention for displaying an image signal with an aspect ratio of 16: 9 on a screen with an aspect ratio of 4: 3. A microprocessor for generating a pan vector address and pan vector data on a data line DL based on the logical status of an identification signal ID of an ID line and a clock signal on the IM bus is connected to a pan vector address decoder 100 so that the pan vector address obtained via the IM bus is decoded.

Furthermore, a pan vector data reader 200 is connected to the data line DL of the microprocessor and the address encoder 100 and reads the pan vector data from the data line from the least significant bit LSB when the pan vector address decoded by the address encoder 100 matches the address received from the transmitter side. Furthermore, a pan vector data converter 300 for converting the data read from the pan vector data reader into a pan vector value for a screen with an aspect ratio of 4: 3 suitable luminance and chrominance signals is connected to the pan vector data reader 200 , and luminance and chrominance signal sampling counters 400 , 500 for sampling the luminance and chrominance signals at a frequency of 523 per line and 262 per line from the original frequency of 697 per line and 349 per line of the D2-MAC system are corresponding to that for a screen with an aspect ratio of 4: 3 suitable for Panvektor 300 received luminance and chrominance signals with the Panvektor data converter 300 is connected from the Panvektor data converter.

Luminance and chrominance latches 600 , 700 are also connected to the luminance and chrominance scan counters 400 , 500 for providing luminance and chrominance signals stored at the addresses generated by the luminance and chrominance scan counters 400 , 500 .

The IM bus standard, one of the bus standards used in Europe, is shown in Fig. 5. Every 8 clocks, ID is changed to high or low state: if ID is low, signals received via data line DL are interpreted as a serial 8-bit address; if ID is high, the signals are interpreted as data.

FIG. 2 is a detailed circuit diagram of FIG. 1 and shows the pan-vector address encoder 100 in detail, the pan-vector data reader 200 and the pan-vector data converter 300 .

A bit matching circuit 110 for matching the output to that in a shift register SR1 for shifting data inputs A, B on every rising edge of the data input during the low status of the ID input by the inverter INV1 from the ID line IL is with the Pan vector address decoder 100 connected.

The bit matching circuit includes the SR1, a number of inverters INV1-INV5 for matching the bits of the off gangs when the one entered in the shift register Address corresponds to a pan vector address, NAND1- and NAND2- Gates connected to the inverters and one with NOR1 gate connected to the NAND gates so that the NAND Gate and the NOR1 gate ar as a normal AND gate work.

Furthermore, the output of NOR1 is connected to a D flip-flop DFF1, which outputs a high signal when the address input in the shift register speaks to the pan vector. The INV1 and the clock connections CLK are connected to a counter 120 in order to apply an erase pulse to the D flip-flop DFF1 via a further NAND gate NAND3.

The pan vector data reader 200 is connected to a further shift register SR2, the clearing terminal CLR of which is connected to the output of SR1 in order to generate shifted pan vector data after shifting the pan vector data input via the data line DL of the IM bus, while the output of the D flip-flops is high.

Furthermore, the clock CLK1 and the AND gate AND1 are connected to the counter 210 , which stops counting as soon as all outputs Q0-Q7 of the SR2 have indicated. Furthermore, the SR2 and the counter 210 are connected to a latch circuit 200 for storing the output of the SR2 and for generating stored data when the counting is finished.

Furthermore, the pan vector data converter 300 comprises pan vector data converter 310 , 320 for converting the pan vector data read by the pan vector data reader 200 into pan vectors for luminance and chrominance signals which are suitable for a screen with an aspect ratio of 4: 3. Each of the pan vector data converters 310 , 320 for the luminance and chrominance signals comprises two full 8-bit adders 311 , 312 , 321 , 322 .

The present invention as described above luminance and chrominance si based on the pan vectors signals for a screen with an aspect ratio of 4: 3 after reading the pan vector address and data according to the logic state of the ID signal on the IM bus. If ID is low, are on the data line DL of the IM bus  Interpre received signals as an 8-bit serial address animals; if ID is high, the signals are inter data pretends. In the following description of the present Er The invention assumes that the pan vector is from the microprocessor with a special address "10100101" via the IM Bus is sent in the first digit of the LSB (least significant) bit and the last digit the MSB (most significant) bit.

If the address input via the IM bus in the Pan vector address encoder 100, the Panvektor address decoder 100 should read all the 8-bit serial data from the data line, when the ID signal is low, and judge, whether it is the desired address, ie "10100101".

Since the ID signal after inverting by INV1 in the Erase terminal CLR of the SR1 is input, the SR1 enabled while the ID signal is low; the data Inputs to ports A and B of the SR1 are on each rising edge of the clock terminal CLK1 in the CLK connection of the SR1 input clock pulse IMCLK ver and the result of the move is sent to the Connections Q0-Q7 output. Therefore, while the ID Signal is low, the LSB is output at terminal Q7, and the MSB will increase after 8 consecutive Flanks of the clock IMCLK determined on the CLK connection of the SR1 have been output at connection Q0.

Only when the data from Q1-Q7 is "10100101" the output of the bit matching circuit goes high State, and the rising edge is connected to the CLK connection of the  D flip-flops DFF1 detected, so that the output Q of the D- Flip-flops DFF1 from high to low only then passes if the address matches.

Since the D flip-flop DFF1 should have been reset once during the low ID period to perform this operation precisely, the output Q of the counter 210 generates an erase pulse for the D flip-flop on the third rising edge of the clock IMCLK from the clock terminal CLK1.

Since it is determined that the address matches when the Q output of the D flip-flop DFF1 is high, the Q output of the D flip-flop DFF1 is connected to the clear terminal CLR of the SR2 of the pan vector data reader 200 in preparation for receiving of pan vector data via the data line DL of the IM bus. Thereby, after the pan vector address signal, the pan vector data signal is input to the SR2, and the SR2 outputs the LSB of the pan vector data at its terminal Q7.

As soon as all bits of the 8-bit data at the output of the SR2 have appeared, a rising edge of a clock pulse at the clock terminal CLK of the hold-down circuit 220 is determined. At this time, the 8-bit full adders 311 , 312 of the chrominance signal pan vector data converter 310 output 44 (decimal) or "01010111" (binary) to PC0-PC7 as panlast value for the chrominance signal; the 8-bit full adders 321 , 322 of the luminance signal pan vector data converter 320 multiply the pan load value in PC0-PC7 by 2 and then subtract 1 from the result by 87 (decimal) or "01010111" as pan load value for the at PY0- PY7 output luminance signal, of which the last digit is the LSB and the last digit is the MSB.

The reason for adding 44 for the chrominance signal and 87 for the luminance signal in the pan vector data converters 310 , 320 is that an image with an aspect ratio of 16: 9 on a screen with an aspect ratio of 4: 3 without Loss of information can only be shown if the luminance signals are sampled from the 44th pixel and the chrominance signals from the 87th pixel, so that the pan vector value is in the center of the screen with an aspect ratio of 4: 3 0.

Therefore, the binary value obtained from the outputs PY0-PY7 of the luminance signal pan vector data converter 320 is used as the start address for the luminance signal sample counter 400 for selecting 523 sample points from 697 luminance signal sample points using the pan vector data obtained via the IM bus, and that binary values obtained from the outputs PC0-PC7 of the chrominance signal pan vector data converter 310 are used as the start address for the chrominance signal sampling counter 400 for selecting 262 sampling points from 349 chromi nance signal sampling points using the pan vector data obtained via the IM bus; starting from the start address, the luminance and chrominance signals stored in the luminance and chrominance signals stored 600 , 700 are output on the screen with an aspect ratio of 4: 3.

As described above, the present invention enables the full display of an image with an aspect ratio of 16: 9 on a television screen with an aspect ratio of 4: 3 by transmitting a pan vector via line 625 of the D2-MAC transmission signal on the transmitter side Contains information about which pixel the image to be displayed begins with; by receiving and decoding the pan vector from line 625 on the receiver side; by selecting only 523 luminance signal sample points and 262 chrominance signal sample points, or only the number that is 12/16 (the ratio of the horizontal lengths of an image with an aspect ratio of 16: 9 to an image with an aspect ratio of 4: 3 if the vertical length the latter is the same as that of the first) corresponds to the original number of sampling points, from the originally sent 697 luminance signal sampling points and 349 chrominance signal sampling points using the pan vector to display an image with an aspect ratio of 16: 9 on a screen with an aspect ratio of 4: 3; and by recovering only selected luminance and chrominance signals suitable for display on a screen with an aspect ratio of 4: 3 from memories 600 , 700 using the output signals at PC0-PC7 and at PY0-PY7 of the luminance and chrominance signal pan vector converter 310 , 320 .

As described above, the present invention has the advantage of displaying an image with one image page 16: 9 ratio on a screen with an aspect ratio nis of 4: 3 without changing information in the transmitted, original signal by generating a pan vector, the  the conventional screen with an aspect ratio of 4: 3 corresponds when an image with an aspect ratio of 16: 9 in the D2-MAC system, the pictures both with the aspect ratio of 4: 3 as well as with the aspect ratio of 16: 9 can be sent.

Claims (5)

1. D2 MAC receiver with a pan vector interface circuit for displaying an image signal with an aspect ratio of 16: 9 on a screen with an aspect ratio of 4: 3, characterized in that it comprises:
a microprocessor for generating a clock signal, pan vector data and addresses of the pan vector on an IM bus;
a pan vector address encoder ( 100 ) connected to the microprocessor for decoding the pan vector address obtained from the IM bus;
a pan vector data reader ( 200 ), connected to the microprocessor and the address encoder, for reading the pan vector data from data lines, starting with the least significant bits when the decoded address of the pan vector matches the address received from the transmitter side;
a pan vector data converter ( 300 ), connected to the pan vector data reader, for converting the pan vector data read from the pan vector data reader into pan vectors for luminance and chrominance signals for a screen with a 4: 3 aspect ratio are suitable;
Luminance and chrominance signal sample counters ( 400 , 500 ) connected to the pan vector data converter for sampling the luminance and chrominance signals at a frequency of 523 per line and 262 per line corresponding to the pan vector for a screen with an aspect ratio of 4 : 3 suitable luminance and chrominance signals obtained from the pan vector data converter; and
Luminance and chrominance latches ( 600 , 700 ) connected to the luminance and chrominance scan counters to provide luminance and chrominance signals stored at the addresses generated by the luminance and chrominance scan counters. 2. D2 MAC receiver according to claim 1, characterized in that its pan-vector address encoder ( 100 ) comprises:
a shift register (SR1) for shifting data on each rising edge of the clock input (CLK) enabled during the low state of an identification input (ID);
a bit matching circuit ( 110 ) connected to the shift register for matching the input data with the output data;
a D flip-flop (DFF1) connected to the bit matching circuit that outputs a high signal when the address input corresponds to an address for a pan vector;
and
a counter ( 120 ) which is connected to a clock connection (CLK) and the identification line (ID) for applying an erase pulse to the D flip-flop. 3. D2 MAC receiver according to claim 1, characterized in that its pan-vector data reader ( 200 ) comprises:
a shift register (SR2) connected to the D flip-flop (DFF1) to generate shifted pan vector data after shifting the pan vector data input while the output of the D flip flop is high; and
a counter ( 210 ) connected to the clock terminal and the pan vector decoder ( 100 ) which stops counting once all of the outputs have appeared; and a latch circuit ( 220 ) connected to the shift register and the counter to provide data from the shift register when counting the counters is stopped. 4. D2-MAC receiver according to claim 1, characterized in that its pan vector data converter ( 300 ) comprises:
Luminance and chrominance signal pan vector data converters ( 310 , 320 ) connected to the pan vector data reader to convert data read from the pan vector data reader into pan vectors for luminance and chrominance signal suitable for a screen with an aspect ratio of 4: 3 are suitable. 5. D2-MAC receiver according to claim 4, characterized in that its luminance and chrominance signal pan vector data converter ( 310 , 320 ) each comprise full adders ( 311 , 312 , 321 , 322 ).