JPH06225166A - Coding and decoding device - Google Patents

Abstract

PURPOSE:To obtain the coding and decoding device in which a time required to divide data to an output bus width thereby processing coding of picture data and decoding of coded data at a high speed. CONSTITUTION:A run length and white/black or color data of picture data inputted to a change point detection run length counter section are converted at each detection of a change point and the result is converted into a code and code length data corresponding to input data by referencing a code code length table reference section and an outputted terminating code is latched by a 13-bit register 32. Then inputted 13-bit parallel code data are shifted by a barrel shifter 33 according to shift quantity command data from a shift quantity command generating circuit 39 and converted into 1-8-bit parallel code data and outputted between output terminals A, B and the data are latched by an 8-bit shift register 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention arranges code codes obtained by coding input image data in a continuous code code sequence,
An encoding device that divides the arranged code code string into predetermined lengths and outputs them in parallel, arranges the image data obtained by inversely converting the coded code codes into continuous image data strings, and arranges the arranged image data strings to a predetermined length. The present invention relates to a decoding device that divides into two and outputs in parallel, or an encoding / decoding device including these encoding device and decoding device.

[0002]

2. Description of the Related Art In an image processing apparatus such as a facsimile apparatus, data compression processing is performed to compress the redundancy of image data obtained by reading a document. The MH method, the MR method, and the MMR method are known as the redundancy suppression encoding method, and they are standardized and widely used. JP-A-6
As disclosed in JP-A-2-149268, M
The H method encodes run length data of black pixels and white pixels, and is encoded through the following steps. (1) The change point of the density data along the pixel row of the input data is detected, and the run length is counted. (2) By referring to the code / code length table, the MH code corresponding to the color data and the run length data and the code length data thereof are obtained for each pixel at the change point. (3) The MH code is arranged as a one-dimensional code string based on the code length data, and is divided into output bus widths and output.

[0003]

When performing the above process (3), since the shift register is used for the division operation for each array of the one-dimensional code string and each output bus width in the prior art, the process is performed. Requires at least as many shift clocks as the code length, and therefore, the time required for this processing occupies a large proportion of the encoding processing time.
The higher the data compression rate, the longer the encoding processing time, which hinders high-speed encoding processing. The decoding process also has the same problem as the encoding process because the process reverse to the above-described encoding process is followed. SUMMARY OF THE INVENTION The present invention is intended to solve such a problem in the prior art, and it takes time to encode or decode image data, arrange it in a code string or image data string, and divide it into output bus widths. It is an object of the present invention to provide a coding and decoding device which is shortened and capable of high-speed processing of coding image data and decoding coded data.

[0004]

In order to solve the above problems, the present invention provides a barrel shifter for performing a shift operation on code code data based on a code code obtained by coding input image data and the code length data. And a first shift amount calculation means for calculating the shift amount of the barrel shifter, storing the shifted code data in the code data storage means, arranging the code data in a continuous code code string, and arranging the code code string. Are divided into predetermined lengths and are output in parallel. Alternatively, the input code code data and the code length data are decoded and converted into image data, and a barrel shifter for performing a shift operation on the image data based on the code length data, and a second shift amount for calculating the shift amount of the barrel shifter. It has a shift amount calculation means, stores the shifted image data in the image data storage means, arranges it in a continuous image data sequence, and divides the arranged image data sequence into predetermined lengths for parallel output. is there.

[0005]

In the former means, the input image data is converted into a code code and its code length data. The barrel shifter shifts the code code data based on the code length data. The first shift amount calculation means calculates the shift amount of the barrel shifter. The code data storage means stores the shifted code data. The code data stored in the code data storage means is arranged in a continuous code code string, and the arranged code code string is divided into a predetermined length and outputted in parallel. Further, in the latter means, the input code code data and code length data are decoded and converted into image data. The barrel shifter shifts the image data based on the code length data. The second shift amount calculation means calculates the shift amount of the barrel shifter, and the image data storage means stores the shifted image data. The image data stored in the image data storage means is arranged in a continuous image data string, and the arranged image data string is divided into a predetermined length and outputted in parallel.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the image signal compression encoding apparatus according to the first embodiment of the present invention. When the image data is input to the change point detection / run length counting unit 1 in the serial format or the parallel format, the change from the white (minimum density) pixel to the black (maximum density) pixel on the input image data string, or the change from the black pixel to white Detects changes to pixels (change point detection), counts the number of pixels from the first change point to the next change point, that is, the run length, and outputs the run length and black and white color data each time the change point is detected. To do. The code / code length table reference unit 2 refers to the input run length and color data as the MH code / code length table, converts them into codes and code length data corresponding to the input data, and outputs them in parallel format. FIG. 7 shows an MH code / code length table of terminating codes corresponding to the black and white run length data "0 to 31". Since the data length is aligned with 13 bits, which is the maximum code length of the MH code, the code data contains 1 to 1 after the original MH code.
11 pieces of 0 data are added. The code length data is the two's complement of the code length of the original MH code, which is represented by 5 bit data. For example, the code / code length table reference unit 2
If white data of run length data “3” is input to, the termination code [1000
0000] and code length data [11100] are output. By the sequence control of the control unit 4, only the terminating code is applied to the input data whose run length data is “0 to 63”, and the makeup code is applied to the input data whose run length data is greater than “63”. And the terminating code is sent. The code arranging unit 3 arranges the terminating codes on the code string based on the input code length data, divides the arranged code string into output bus width units, and outputs them in a parallel format. FIG. 1 shows an internal circuit of the code arrangement unit 3. The barrel shifter 33 shifts the input 13-bit parallel code data in accordance with the shift amount command data from the shift amount command generation circuit 39, converts it into 1 to 8 bit parallel code data, and straddles the output terminals A and B. Output. Figure 5 (a)
Shows the concept of the circuit wiring inside the barrel shifter 33, and (b) shows the wiring state of the transceiver gate indicated by a circle at each intersection of the vertical (output) horizontal (input) wiring of (a). It is shown. The transceiver gate uses the shift amount command data for each bit as an enable signal,
Make the vertical and horizontal wiring the same polarity. The output line arranged in the vertical direction is grounded via a pull-down resistor, and when none of the transceiver gates connected to it is energized, the output of the bit becomes low level. The 13-bit input code data input to the input lines arranged in the horizontal direction is, for example, the code data input to the input lines 0 to 7b when the 8th bit shift amount command data is turned on. Input lines 8-12 to A-side output lines 0-7b
The code data input to b are output lines 0 to 0 on the output terminal B side.
4b is shifted and output. Output line 5 on the output end B side
~ 11b goes low (0) because none of the transceiver gates connected to it are energized.
Although a transistor element is used as the transceiver gate in this embodiment, it may be formed of a switching element.

FIG. 3 shows the internal circuit of the shift amount command generating circuit 39, and FIG. 4 shows the internal circuit of the selector 34. As shown in FIG. 4, the selector 34 has eight selectors 34.
1 to 348, the 8-bit code data output from the barrel shifter 33 is selected by the selectors 341 to 341, respectively.
Input to the A input terminal of 348. The output code data for each bit of the 8-bit register 35 is input to each B input terminal. A shift amount command generation circuit 3 is provided at each selection signal terminal.
The shift amount command data output from 9 is input as it is or via the OR gates 34a to 34g.
When the shift amount command data for each bit is input, the selectors 341 to 348 from the MSD side instructed by the shift amount command data are switched according to each selection data,
The output code data of the bit from the barrel shifter 33 is selected as an input signal, and each code data output from the selectors 341 to 348 is latched in the 8-bit register 35 by the supply of the latch signal. The shift amount command generation circuit 39 outputs the shift amount command signal and the next operation enable signal shown in FIG. 8 according to the value of the input data n (n is a positive or negative integer). In addition, when n is a positive integer, it indicates that the number of empty bits in the 8-bit register 35 is n. When n is a negative integer, the termination code of the termination code that cannot be completely stored in the 8-bit register 35 is displayed. It represents the number of bits and indicates that code byte data to be transferred is formed in the 8-bit register 35. When n = 0, it indicates that the LSD (least significant number) of the code data registered in the 8-bit register 35 matches the byte boundary, and the code byte data corresponding to the output data is formed. FIG. 6 is a flow chart of code arrangement processing. The operation of the code arrangement unit 3 will be described with reference to FIG. In the reset state, the 13-bit register 32 is cleared and the output of the 5-bit register 38 is set to "8" by the code length data "8" input from the A input terminal side of the selector 36. First, in step S-1, it is determined whether or not the next operation enable signal is on. Since n = 8> 0 after the reset, the operation enable signal is on next time, and thus the process proceeds to the next step S-2. Step S-
In 2, the input of the selector 31 is set to the A input end side and 1
A latch signal is supplied to the 3-bit register 32 to latch the terminating code data input from the code / code length table reference unit 2. Further, the input of the selector 36 is also set to the A input terminal side, the code length data input from the code / code length table reference unit 2 is taken in, and the output of the 5-bit register 38 is set to 5-bit data "n". Barrel shifter 33 is 1 output from 13-bit register 32
8 bits of 3-bit code data according to shift amount command signal
Bit shift. Next, the input of the selector 31 is set to the B input end side, and the 13-bit registers 32 and 8
A latch signal is supplied to the bit register 35 (S-
3). Below, to facilitate understanding, as a specific example,
The input termination code data corresponds to the white run length data “2” [011100000000
0] will be described. Barrel shifter 3
8 bit shift by 3 causes [01
110000] data is output and latched by the 8-bit register 35, and the remaining [0000
0] data is output and latched at 0 to 4 bit positions of the 13-bit register 32. The remaining 5 to 1
0 data is latched at the 2-bit position. In the next step S-4, the latch signal is supplied to the 5-bit register 38, and the code length data (2's complement data of the code length data) input to the A input terminal side of the selector 36 and the 5-bit register are input. The data "n" output from 38 is the adder 3
The data added in 7, that is, the data of [n-code length] is latched. That is, the data of “8-4” = “4” is latched. Note that step S-3 and step S-
4 may be executed simultaneously. In step S-5, the sign of the data "n" output from the 5-bit register 38 is determined. If n> 0, the process proceeds to step S-6,
The shift amount command data in which the n-bit data is on and the data in which the next operation enable signal is on are output. next,
It is judged whether or not the code arrangement processing is completed (S-7),
If not completed, the process returns to step S-1 to repeat the above operation. Through a series of processes, white run length 2 terminating code data [0111] is latched in the LSD side bit position in the 8-bit register 35, and data 0 is latched in the upper bit position. Next, for example, when the terminating code data of black run length 8 is input from the code / code length table reference unit 2, the next operation enable signal is ON, so the process proceeds to step S-3,
4-bit data is turned on by a shift amount command signal
[000101] on the A output terminal side of the barrel shifter 33.
The upper 4 bits of the input terminating code data of [0000000] are shifted to 4 to 7 bit positions, 0 data is set to 0 to 3 bit positions, and 8
It is output as bit data [00000001].
The output data and the 8-bit data output from the 8-bit register 35 are input to the selector 34, and the input terminal B is selected and taken in by the shift amount command signal. As a result, the 8-bit data is output from the selector 34. [01100
01] is output and latched in the 8-bit register 35. On the other hand, the remaining low-order bit data of the input termination code data is output to the B output end side of the barrel shifter 33, is input to the 13-bit register 32 via the selector 31, and is latched from the LSD side bit position. 0 data is set in the remaining bit positions and 1
The 3-bit data [010000000000] is latched. Next, in step S-4, "n" in the adder 37
The operation of “code length”, that is, the operation of “4-6” = “-2” is executed and latched in the 5-bit register 38.
As a result, the determination in step S-5 becomes no, so the process proceeds to step S-8, and the output request signal of the already formed output byte data is sent to the host computer. In step S-9, it is determined whether the output data of the 8-bit register 35 has been read, and the result is y.
If it is es, "8" is set to the shift amount command signal and the input of the selector 36 is set to the B input end side (S-10). When the process of step S-10 ends, the process returns to step S-3. In step S-3, the upper 2-bit data [01] of the 13-bit data created from the termination code data of black run length 8 latched in the 13-bit register 32 is stored in the LSD of the 8-bit register 35.
Latch to side bit position. 13-bit register 3
Insignificant 0 data is set in 2 at all bit positions. In the process of step S-4, the data "8" input from the B input terminal side of the selector 36 and the data n output from the 5-bit register 38 are added by the adder 37, and "-2 + 8" = "" The 6 ″ operation is executed and latched in the 5-bit register 38. Thereafter, the same processing as described above is repeated, and the code arrangement processing is executed for the data of run lengths that are input one after another. In addition, when n = 0, steps S-8 to S-10 and steps S-3 to S-4 are performed.
Routine is executed only to obtain n = 8.

In the present embodiment, the time required for the code arrangement processing for data of one run length can be set to 2 to 5 clock cycles if the reading time of the output data is ignored, so that the code arrangement processing is very fast. Can be converted. In the present embodiment, an example in which run length data is input as MH code input image data has been described, but the present invention is not limited to this, and the same processing is performed on special code data such as EOL code. It can be carried out.

FIG. 9 is a block diagram showing the structure of an image signal decoding apparatus. The input code data string is input to the significant code detection / run length search unit 5 in serial or parallel format. The significant code detection / run length search unit 5 performs MH
By referring to the code / code length table, significant code data is detected from the input code data string, color (black and white) and run length data corresponding to the code data are generated, and output to the image data reproduction arrangement section 6. . The operations of detecting the significant code data and generating the run length data are performed for each code data that is sequentially input. The image data reproduction arrangement unit 6 reproduces the image data according to the input color and code data of the run length, divides it into parallel output widths, and outputs it.
The unit of the run length data input to the image data reproduction arrangement unit 6 is a run length represented by one make-up code, a run length represented by one termination code, or a set of run length data. It is one of the run lengths represented by the make-up code and the terminating code. The run length data is displayed in 2's complement. The control unit 4 is a significant code detection / run length search unit 5
Also, the operation of the decoding process is controlled while monitoring the image data reproduction array unit 6. FIG. 10 shows the image data reproduction arrangement section 6
The internal circuit of is shown. The 8-bit color data output from the significant code detection / run length search unit 5 is input to the barrel shifter 65 and is shifted in accordance with the 8-bit shift amount command signal output from the shift amount command generation circuit 64, and the 8-bit parallel data is output. It is output as output data. The input color data is all 0 or 1. FIG. 12 shows the concept of the circuit wiring inside the barrel shifter 65, which has a configuration similar to that of the barrel shifter 33 of the compression encoder. For example, when the shift amount command signal is for instructing a 4-bit shift amount, 0 to
The 3-bit input color data is shifted to the 4- to 7-bit position, the remaining 0 to 3-bit data becomes 0 data by the pull-down resistor, and is output as 8-bit parallel output data. The selector 66 is the selector 34 of the code arrangement unit 3.
It has the same configuration and operation as.

FIG. 11 shows an internal circuit of the shift amount command generating circuit 64. This circuit configuration also has the same configuration as the shift amount command generation circuit 39 of the compression encoding device. The input color data are all 0 or 1 data,
The input run length data is the 13-bit register 63.
It is the same as the configuration and operation of the shift amount command generation circuit 39 except that it is the 13-bit complement expression data output from The maximum value of the output data of the 13-bit register 63 is "8". FIG. 13 is a flow chart of the image data reproducing arrangement process. The operation of the image data reproduction array unit 6 will be described with reference to FIG. In the reset state, the B input terminal side is selected as the input of the selector 61, and the output data of the 13-bit register 63 is set to "8". First, in step S-11, it is determined whether or not the next operation enable signal is on. Since n = 8> 0 after the reset, the operation enable signal is on next time, and thus the process proceeds to the next step S-12. The shift amount command generation circuit 64 outputs the shift amount command signal and the next operation enable signal shown in FIG. 8 according to the value of the input data n. Step S
In -12, the input of the selector 61 is switched to the A input terminal side, and the 1 input from the significant code detection / run length search unit 5 is input.
13-bit complement expression run length data is captured and
A latch signal is supplied to the bit register 63 to latch the run length data input from the significant code detection / run length search unit 5, and the output of the 13-bit register 63 is set to "n". The barrel shifter 65 shifts the input 8-bit color data according to the shift amount command signal. Next, the input of the selector 66 is set to the B input terminal side, and a latch signal is supplied to the 8-bit register 67 (S-13). In the next step S-14, the latch signal is supplied to the 13-bit register 63 so that the A of the selector 61 is A.
Data obtained by adding the run length data (2's complement data of run length) input to the input end side and the data n output from the 13-bit register 63 by the adder 62, that is,
The data of [n-run length] is latched. Step S-
At 15, the sign of the data n output from the 13-bit register 63 is determined. If n> 0, step S-
Proceeding to 16, the shift amount command signal for turning on the n-bit data and the next operation enable signal on are output. Next, it is judged whether or not the image data reproducing arrangement processing is completed (S-17), and if not completed, step S-11.
Then, the above operation is repeated. Next, step S-1
If the determination in 5 is no, proceed to step S-18,
The output request signal of the already formed output byte is sent to the host computer. In step S-19, 8
It is determined whether or not the output data of the bit register 67 has been read. If the result is yes, the shift amount command signal is set to "8" and the input of the selector 61 is set to the B input end side (S- 20). When the process of step S-20 ends, the process returns to step S-13. Thereafter, the same processing as described above is repeated, and the image data reproduction array processing is executed for the color and run length data that are input one after another. As described in the first embodiment, the main circuit configurations of the compression encoding device and the image signal decoding device have many common parts. Therefore, the main circuit configurations for encoding and decoding can be made common to reduce the size and cost of the circuit. FIG. 14 shows an internal circuit of the code array and the image data reproduction array section according to the second embodiment of the present invention in which the main circuit configurations for encoding and decoding are made common. The parts which can be regarded as the same as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, the code data and the color data input to the barrel shifter 65 are switched by the selector 68, and the code length data and the run length data input to the 13-bit register 63 are switched by the selector 69. In addition, when performing the decoding process, the barrel shifter 3
The color data input to 3 uses 8 bits on the LSD side, and when the encoding process is performed, the 5-bit complement expression run length data is set to 1
In order to extend the width to 3 bits, 8-bit data [11111111] is added to the MSD side. In each of the above-mentioned embodiments, the pull-down resistors used for the barrel shifters 33 and 65 are unnecessary if it is not necessary to determine the output potential.

[0011]

As described above, according to the first aspect of the present invention, the barrel shifter for performing the shift operation on the code code data obtained by encoding the input image data, and the first operation for calculating the shift amount of the barrel shifter Since the shift amount calculating means is included, the time required to divide the code data into the output bus width can be shortened and the image data can be encoded at high speed. According to the second aspect of the present invention, the change point of the input binary image data is detected, the run length is counted based on the detected result, the run length data and its color data are generated, and the generated run length data is generated. Since they are arranged in a continuous run length sequence according to the color data and the run length data, high-speed encoding processing can be realized with a relatively simple configuration. According to the invention described in claim 3, a barrel shifter for decoding input code code data and code length data, converting the code data into image data, and performing a shift operation on the image data based on the code length data, and a shift of the barrel shifter. Since the second shift amount calculating means for calculating the amount is provided, the time required to divide the image data into the output bus width can be shortened, and the decoding of the code code data and the code length data can be processed at high speed. . According to the invention described in claim 4, significant data is detected from the input code code data and code length data, run length data and color data corresponding to the significant data are generated, and the generated color data and run length are generated. Since the images are arranged in a continuous image data sequence according to the data, the high-speed decoding process can be realized with a relatively simple configuration. According to the invention described in claim 5, since the encoding device according to claim 1 or 2 and the decoding device according to claim 3 or 4 are provided, the main circuits of the encoding circuit and the decoding circuit are made common. As a result, downsizing of the circuit and cost reduction of the device can be realized.

[Brief description of drawings]

FIG. 1 is an internal circuit diagram of a code array section according to a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a compression encoding device for image signals.

FIG. 3 is an internal circuit diagram of a shift amount command generation circuit.

FIG. 4 is an internal circuit diagram of a selector.

FIG. 5 is a conceptual diagram showing circuit wiring inside the barrel shifter and a wiring diagram of a transceiver gate at each intersection of wiring of an output line and an input line.

FIG. 6 is a flowchart of code arrangement processing.

FIG. 7 is a table showing an MH code / code length table.

FIG. 8 is a table showing output signals of a shift amount command generation circuit.

FIG. 9 is a block diagram showing a configuration of a decoding device.

FIG. 10 is an internal circuit diagram of an image data reproduction arrangement unit.

FIG. 11 is an internal circuit diagram of a shift amount command generation circuit.

FIG. 12 is a conceptual diagram showing circuit wiring inside a barrel shifter.

FIG. 13 is a flowchart of image data reproduction array processing.

FIG. 14 is an internal circuit diagram of a code arrangement and image data reproduction arrangement section according to a second embodiment of the present invention.

[Explanation of symbols]

 1 Change point detection / run length counting unit 2 Code / code length table reference unit 3 Code arrangement unit 5 Significant code detection / Run length search unit 6 Image data reproduction arrangement unit 32, 35, 38, 63, 67 Registers 33, 65 barrels Shifter 39, 64 Shift amount command generation circuit

Claims (5)

[Claims] 1. A code code obtained by coding input image data, and a shift operation of the code code data based on the code length data, storing the code code data in a code data storage means, and then arranging them in a continuous code code string. In the encoding device that divides the arranged code code strings into predetermined lengths and outputs them in parallel, a barrel shifter for performing a shift operation on the code code data, and a first shift amount calculation means for calculating the shift amount of the barrel shifter are provided. An encoding device having. 2. A first run length data generation means for detecting a change point of input binary image data, counting run lengths based on the detected result, and generating run length data and its color data. 2. The encoding apparatus according to claim 1, further comprising run length sequence arranging means for arranging in a continuous run length sequence in accordance with the color data and the run length data generated by the run length data generating means. 3. The input code code data and the code length data are decoded to be converted into image data, the image data is shifted based on the code length data, stored in the image data storage means, and then the continuous image In a decoding device for arranging in a data string and dividing the arranged image data string into a predetermined length and outputting them in parallel, a barrel shifter for performing a shift operation on the image data and a second shift amount for calculating a shift amount of the barrel shifter. A decoding device comprising a calculation means. 4. A second run length data generating means for detecting significant data from the inputted code code data and code length data and generating run length data and its color data corresponding to the significant data, and the second run length data generating means. 4. The decoding apparatus according to claim 3, further comprising image data sequence arranging means for arranging the image data sequence into a continuous image data sequence according to the color data and the run length data generated by the run length data generating device. 5. The encoding device according to claim 1 or 2,
An encoding / decoding device comprising the decoding device according to claim 3.