JP3029863B2 - Compressed data decoding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for decoding compressed data, which decodes a code sequence that has been data-compressed by constant coding.

[Related Art] In a facsimile apparatus, an electronic image filing apparatus, and the like, it is common to compress image data read from a document by encoding.

In general, when reproducing the original image information from the coded data which has been compressed by such a device, for example, a method disclosed in
As seen in Japanese Patent Application Laid-Open No. 62-149269, a code table in which each code is stored in a ROM is formed, and a code string of encoded data is compared with each code in the ROM.

By the way, in recent years, a one-chip LSI for performing such a decoding process has been developed and widely used.

When the above-described code table is formed in the LSI, the chip size increases according to the data amount of the code table. In addition, the cost increases significantly as the chip size increases. In particular, when a matrix-structured memory is formed by a gate array method, a very large chip area is required for an IC dedicated to the memory, and the amount of data in the table greatly affects the cost. Furthermore, if the chip space is small, it may be difficult to implement LSI.

The publication discloses that decoding is performed using an MH (Modified Hoffman) code, and the data amount of the code table is reduced by selectively using a code table for each code type of a terminating code and a makeup code. .

However, even in the case of this proposal, the data amount of the code table is 31
It was as large as 87 bits.

By the way, in the encoded data of the MH code, the makeup code and the terminating code are not always arranged alternately, and the order in which the codes occur is undefined.

For this reason, conventionally, when decoding one code of the encoded data, for example, it is first determined whether or not there is a code that matches the various terminating codes. Is determined in a two-stage procedure. For this reason, the encoding process took time.

[Problems to be Solved by the Invention] As described above, conventionally, there has been a problem that the data amount of the code table formed in the ROM becomes large and the decoding process takes a long time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a decoding apparatus for compressed data in which the above problem is solved, the amount of data in a code table is reduced, and the decoding process is accelerated.

[Means for Solving the Problems] For this purpose, the first invention of the present application uses, as in the MH code,
If the bit length of each code is indefinite and the bit length exceeds a certain number of bits, the code data with the number of bits less than the above-mentioned certain number of bits is used in the case of a code in which all bits of the excess are the same data. Is stored in the code table. When decoding, the word data of the code table is read out one word at a time, and the code data and the code length are read. Each code is generated according to the data, and the generated code is compared with the input code sequence, and when they match,
It reproduces raw data of various corresponding patterns.

Further, in the second invention, in the case of the MH code, various terminating codes and various make-up codes are generated one by one at the same time, and the generated codes are simultaneously compared with the input code sequence to determine the coincidence. In this case, the original raw data corresponding to the code is reproduced.

[Operation] According to the first aspect, the required number of bits per word of the code table is reduced, and the data amount of the entire code table can be reduced.

In the second invention, the input code sequence is checked for the terminating code and the makeup code at the same time, so that one code can be determined quickly. This speeds up the decoding process.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a compressed data decoding apparatus according to an embodiment of the present invention. In the figure, a shift register 1 is an MH input by a serial signal.
The code data is converted into a 13-bit parallel signal.

The terminating code detection circuit 2 and the makeup code detection circuit 3 detect each code from the output signal of the shift register 1, and when detecting one code, output a specific count value for each code.

The register 4 sets the count value from the terminating code detection circuit 2 and the makeup code detection circuit 3. The pixel data generating circuit 5 outputs white or black pixel data for the number of pixels of the set count value. The control section 6 monitors and controls the above sections.

In the terminating code detection circuit 2, the counter 21 is a 6-bit binary counter, and its output is
It is input to the register 4 and the code table ROM22.

The code table ROM 22 stores various word data as shown in FIG. These word data are used to generate various terminating codes, and are stored in 64 words each of run lengths 0 to 63 for each color of white and black. One word is composed of code data of 8 bits or less and code length data of 4 bits.

The code data read from the code table ROM 22 is:
The code length data input to the barrel shifter 23 is input to the shift amount decoder 24.

The shift amount degoder 24 converts the 4-bit code length data into a 6-bit shift amount signal.

FIG. 3 shows a circuit of the shift amount decoder 24. In the figure, the first bit b ₁ of the code data is
An inverter I _1, are inputted to the AND circuit _{A 1, A 2, A 3} . The outputs of the inverter I ₁ are AND circuits A ₄ and A
_Entered in ₅ respectively.

The second bit b ₂ of the code data includes an inverter I _2, are input to the AND circuit _{A 1, A 3, A 4} , the output of the inverter I ₂ are respectively inputted to the AND circuit A _2, A ₅ .

Third bit b ₃ of the code data includes an inverter I _3, are inputted to the AND circuit _{A 1, A 2, A 4} , A 5, an inverter I ₃
The output of is inputted to the AND circuit A _3.

The fourth bit b ₃ is a shift amount signal S ₅ of the fifth bit.
It is outputted as, through an inverter I _4, are inputted respectively to the AND circuits A ₁ to A _4. The outputs of the AND circuits A ₃ , A ₅ , A ₂ , A ₄ , and A ₁ are output as shift signals S _{0 to} S ₄ in that order.

The barrel shifter 23 shifts the bit position of the code data input from the code table ROM 22 and outputs it as a 13-bit signal.

FIG. 4 shows a circuit of the barrel shifter 23. In the figure, a shift signal is provided in the barrel shifter 23.
S ₀ 6 sets of gate circuits G ₁ ~G ₆ that is opened and closed controlled by to S ₅ are disposed. In each of the gate circuits G _{1 to} G ₆ , each bit b _i of the input code data is
b A tri-state buffer B for outputting to the _j side is provided. The buffer B is adapted to be opened and closed controlled by the shift signal S _k.

The gate circuit G _1, each bit b ₁ of the input code data
The ~b _8, are arranged to output to the bit b ₁ ~b ₈ output signals. The gate circuit G ₂ is, each bit b ₁ ~ code data
b ₈ is replaced by bit b _{2 of the} output signal which is shifted by one bit from the above.
It is arranged so as to output the ~b _9. Similarly, the gate circuit G ₃ ~G ₆ is arranged to output to the output signal side offset the code data bit by bit.

The code table ROM 22, shift amount decoder 24, and barrel shifter 23 constitute code generation means for sequentially generating various MH codes one by one.

The comparator 25 compares the output signal of the barrel shifter 24 with the output signal of the shift register 1.

FIG. 5 shows the circuit of the comparator 25.
In the figure, to the exclusive OR circuit E ₀₁ to E _13, each bit b _i of the output signals of the shift register 1 side and the shift amount decoder 24 side are respectively inputted in a one-to-one.

OR circuit O ₀₁ inputs the output of the exclusive OR circuit E ₀₁ and exclusive OR circuits E _02, the OR circuit O ₀₂ is the exclusive OR circuit E ₀₃ and the output of the OR circuit O ₀₁ Output and input. Similarly, to the OR circuits O _{03 to} O ₁₂ , the output of the preceding OR circuit and the output of the corresponding exclusive OR circuit are input.

Multiplexer M inputs and outputs of the exclusive OR circuit E _01, the outputs of the OR circuit O ₀₁ ~ O _12, code table
According to the code length data from the ROM 22, one of these outputs is selected.

The makeup code detection circuit 3 has the same configuration as the terminating code detection circuit 2 except for a part. The difference is that a table address correction circuit 26 is provided between the counter 21 and the code table ROM 22, as shown in FIG. 6, and the word data in the code table ROM 22.

FIG. 7 shows the word data of the code table ROM22. These word data are used to generate various make-up codes.
27 words are stored from 1 to 1728 in 64 to 64 steps. In addition, 13 words of run length 1792 to 2560 are stored in common for black and white.

Note that a run length up to 1728 corresponds to a standard makeup code up to A4 width, and a run length 1792 or more corresponds to an extended makeup code exceeding A4 width.

With the above configuration, when the decoding device of the present embodiment performs an operation, MH code data is sequentially input as a serial signal from another device (not shown).

When the data of the MH code is input, the control unit 6 first specifies to the code table ROM 22 and the pixel data generation circuit 5 whether the pixel to be reproduced is white or black, as shown in FIG. This designation is white at the start of the current processing. After the pixel data is reproduced, as will be described later, white and black are alternately designated each time the pixel data is reproduced (process 101).

Next, the counter 21 in the terminating code detection circuit 2 and the makeup code detection circuit 3 and the register 4
Are reset (process 102). Then, the input MH code data is read into the shift register 1 for 13 bits (process 103).

Thereafter, the control unit 6 checks the terminating code detection signal D _T and the makeup code detection signal D _M output from the comparator 25 of the terminating code detection circuit 2 and the makeup code detection circuit 3 ( Process 104).

At this time, the code table ROM 22 of the terminating code detection circuit 2 outputs one word data of the table address specified by the counter 21 among the respective specified word data.

On the other hand, on the makeup code detection circuit 3 side, the table address correction circuit 26 determines that the counter 21 has “1” to “27”.
Is output as the table address to the code table ROM 22 as it is. Also,
When the counter indicates "28" or more, it indicates the table address where the black and white common word data shown in FIG. 7 is stored. Thereby, the code table ROM22
Outputs the corresponding word data.

By the way, the code table of the MH code is presented by CCITT. Each code has a bit length of 2 to 13 bits,
Assuming that the left side of the code table is the upper bits, the upper bits are transmitted one bit at a time.

As is clear from the code table, among the codes, those having a bit length exceeding 8 bits have all the higher bits of the ninth and higher bits counted from the lower bit side become "0".

In the code table ROM 22, MH codes having a bit length of 8 bits or less are stored as code data as they are. In the MH code of 9 bits or more, the lower 8 bits are stored as code data. And each MH
The number of bits of the code, that is, the complement of the code or the like is stored as code length data.

For example, an MH code having a pixel color of “white” and a run length of “1” is “000111”, and the code length is “6”. In this case, as shown in FIG. 2, "000111" is stored as word data in the code table ROM 22, and "1010" which is a complement of the code length "6" is stored as code length data.

Further, the MH code of the pixel “black” and the run length “0” is “00”.
00110111 ”and the code length is“ 10 ”. In this case, lower eight bits “00110111” are stored as word data, and “0110”, which is a complement of code length “10”, is stored as code length data.

22 in the terminating code detection circuit 2 outputs word data having a count value of the counter 21 as a run length.
Also, the code table RO in the makeup code detection circuit 3
M22 is a run length "64" when the count value is "1",
When the run length is "2", the run length "128"
And outputs word data having a run length of 7 times.

The shift amount decoder 24 inputs the code length data of the output word data. The code length data is ninth
As shown in the figure, it corresponds to the complement of the code length. Shift amount decoder 24 inputs the code length data, as shown in the figure, to turn on the shift signal S ₀ to S ₅ in accordance with the data.

That is, when the code length is 13 bits, the shift signal S ₀ indicating the shift amount “0” is output, and when the code length is 12 bits, the shift signal S ₁ indicating the shift amount “1 bit” is output.
Is output. Hereinafter Similarly, outputs a large shift signal S _i of the shift amount according to the code length. Further, when the code length is 8 bits or less outputs a shift signal S ₅ indicating the shift amount "5 bits".

The barrel shifter 23 receives the shift signals S _{0 to} S ₅ and the code data output from the code table ROM 22.
In this case, by one of the shift signal S _i which is turned on, the gate circuit G _i corresponding to operate. Thus, is apparent from FIG. 4, 8-bit code data input is shifted by a shift amount indicated by the shift signal S _i, is output as 13-bit data b ₁ ~b _13. Further, since each signal line of the data is grounded by the resistor R and is at the low level, the output in which the code data is not set is output as data "0". This output data is one MH code.

For example, “black” is specified by the control unit 9 now,
Assuming that the count value of the counter 21 is "0", the code data "00110100" and the code length data "0110" are read from the code table ROM 22 of the terminating code detection circuit 2 as shown in FIG. Is output. At this time, the shift amount decoder 23 shifts the code data by 3 bits according to the code length data, and as shown in FIG.
A predetermined MH code “0000110100000” is generated.

The comparator 25 receives the generated MH code and the output data of the shift register 1. Here, as shown in Figure 5, the exclusive OR signal c ₁ the output of the circuit E _01, the OR circuit O ₀₁ ~ O respectively signals c ₂ to c ₁₃ each output of up to _12.

Exclusive OR circuit E ₀₁ to E ₁₃ in the comparator 25 compares the data of the two input respectively by one bit, and outputs a logical value "0" match. Therefore, as is apparent from FIG. 6, for example, when the generated MH code and the output data of the shift register 1 all match 13 bits, the signals c _{1 to} c ₁₃ all become “0”. Become. On the other hand, when the i-th bit counted from the upper bits does not match, the signals c _{1 to} c _i-1 become “0” and the signals c _{i to} c ₁₃
Becomes “1”.

Multiplexer M selectively outputs one of the signal c _j corresponding to the code length indicated by the code length data output from the code table ROM 22. Since the code length indicates the code length of the MH code generated at that time, when the output signal of the comparator 25 is “0”, the generated MH code is
Will be set to

The output signal of the comparator 25 is output as a terminating code detection signal D _{T in} the case of the terminating code detection circuit 2 and is output as a makeup code detection signal D _{M in} the case of the makeup code detection circuit 3.

Control unit 6, when the the terminating code detection signal D _T and make-up code detection signal D _M are both "1" (process
(N in 104), the counter 21 is incremented by +1 (process 105), and the same check is repeated (to process 104).

When the the terminating code detection signal D _T or makeup code detection signal D _M becomes "0" (process 10
(4) Y), the count value of the corresponding circuit-side counter 21 is set in the register 4.

The register 4 has 12 bits. The count value of the terminating code detection circuit 2 is set to the lower 6 bits, and the count value of the makeup code detection circuit 3 is 6 bits.
Set a bit. As a result, the run length of the monochrome pixel is set in the register 4.

Next, the type of the set count value is determined (step 10
7). Here, when the run length of the makeup code is set (N in process 107), the shift register 1 is shifted by the number of bits indicated by the code length, the next new MH code data is read, and the process is performed simultaneously. Yes (Process 103
What).

On the other hand, when the terminating code is set (Y in step 107), the pixel data generating circuit 5 is activated.

The pixel data generation circuit 5 generates and outputs the designated white or black pixel data for the run length set in the register 4 (process 108). In this way, the original pixel data corresponding to one run is reproduced.

Thereafter, the color of the pixel to be reproduced is inverted, and the same processing is performed (to processing 101). Thus, the forward dimension pixel data is reproduced.

As described above, in this embodiment, the code table includes the data of 128 words for the terminating code shown in FIG. 2 and the data of 67 words for the make-up code shown in FIG. One word is composed of code data of less than 8 bits and code length data of 4 bits, and various MH codes are generated by the two data.

Therefore, the data amount of the code table is 12 bits to 195
A word, at most 2340 bits. As described above, the data amount can be significantly reduced as compared with the above-described conventional example of 3187 bits.

As a result, the space required for the LSI chip for the encoding process is reduced, and the cost of the LSI is reduced. On the other hand, it is easy to create an LSI having a higher processing function.

Also, the terminating code detection circuit 2 and the makeup code detection circuit 3 are separately provided, and the input MH
Two types of codes are determined simultaneously for codes. This allows one MH code to be determined quickly,
The decoding speed can be increased.

Further, the code length data in the code table ROM 22 indicates the complement of the code length. Thus, as can be seen from FIG. 3, can be utilized 4 bit code length data as a shift signal S ₅ as it is. Thereby, the circuit configuration of the shift amount decoder 24 is simplified.

However, it goes without saying that the code length data may simply indicate the number of code bits as it is. Further, an EOL code indicating the end of one line may be stored in the code table.

Further, in the above embodiment, the original data of the MH code is assumed to be image information. However, it is obvious that the present invention can be applied to not only image information but also arbitrary bit pattern data.

In addition, the termination code detection circuit 2 and the makeup code detection circuit 3 determine the code at the same time. It is also conceivable to simultaneously determine the sign in the range. Thereby, the decoding speed can be further increased.

Furthermore, the example of the MH code, which is a one-dimensional encoding method for encoding a run length in one line, has been described.
In a two-dimensional coding method such as an MMR code, the position of a black and white change point in a line is expressed as a relative positional relationship with the nearest change point position of the previous line, and is encoded into a variable length code. Can be similarly applied.

[Effects of the Invention] As described above, according to the first invention of the present application, one word is constituted by code data less than the maximum length of each code and code length data indicating the bit length of the code. , And each code is generated by the two data, so that the data amount of the code table can be reduced. On the other hand, according to the second invention, in the case of the MH code, the terminating code and the Since a make-up code is generated at the same time and two types of code determinations are performed at the same time, the decoding process can be sped up.

[Brief description of the drawings]

FIG. 1 is a block diagram of a compressed data decoding apparatus according to one embodiment of the present invention, FIG. 2 is an explanatory diagram of data stored in a code table ROM for terminating codes, and FIG. 3 is a circuit of a shift amount decoder. FIG. 4, FIG. 4 is a circuit diagram of a barrel shifter, FIG. 5 is a circuit diagram of a comparator, FIG. 6 is a supplementary explanatory diagram of a makeup code detection circuit, and FIG. 7 is data stored in a code table ROM for makeup codes. FIG. 8 is an operation flowchart of a decoding process, FIG. 9 is an explanatory diagram of an output signal of a shift amount decoder, and FIG. 10 is an explanatory diagram of an MH code generating operation. DESCRIPTION OF SYMBOLS 1 ... Shift register, 2 ... Terminating code detection circuit, 3 ... Makeup code detection circuit, 4 ... Register, 5 ... Pixel data generation circuit, 6 ... Control part, 21
... Counter, 22 code table ROM, 23 barrel shifter, 24 shift amount decoder, 25 comparator.

Claims (2)

(57) [Claims] 1. Each code is obtained by compressing raw data of a predetermined pattern, and the bit length of each code is indefinite. If the number of bits exceeds a predetermined number of bits, all excess bits are replaced by the same data. In a compressed data decoding apparatus for inputting a code sequence and reproducing the original raw data, one word is composed of the code data of less than the predetermined number of bits and the code length data indicating the bit length of the code. A code table storing each word data, reading means for sequentially reading the word data from the code table one word at a time, and generating each code by the code data and code length data of the read word data. Code generating means; comparing means for comparing the generated code with the input code sequence; Recovery Goka device of the compressed data, characterized in that it comprises a raw data reproducing means for reproducing the original raw data. 2. A compressed data decoding apparatus for receiving a code sequence of an MH code and reproducing original raw data, comprising: a terminating code generating means for sequentially generating various terminating codes one by one; Up code 1
Make-up code generating means, which is sequentially generated one by one, and comparing means for comparing each code simultaneously generated from the make-up code generating means and the terminating code generating means with an input code sequence; And a raw data reproducing means for reproducing the original raw data corresponding to the code which coincided with the compressed data.