JP3054173B2 - Variable length code detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable-length code detection circuit for detecting each code in a data string in which a plurality of codes each having a variable number of bits are continuous.

2. Description of the Related Art In transmitting image information by a facsimile apparatus or the like, the image information is encoded. In this case, coding schemes such as MH, MR, and MMR are often used.

In these encoding methods, each code is generated based on the run length of white / black pixels of image information. Generally, when generating each code from the run length or reproducing the run length from each code, the conversion table between the code and the run length is stored in the ROM.
And refer to the data.

By the way, in the case of an apparatus that performs an encoding process and a decoding process, if a conversion table for encoding and a conversion table for decoding are separately provided, there is a disadvantage that the ROM capacity increases. In particular, when the encoding / decoding circuit is formed into an LSI, there is a problem because a large chip area is occupied by the ROM.

In order to improve such inconvenience, for example,
As can be seen in JP-A-62-149269, by using the same conversion table for encoding and decoding, ROM
There have been proposals for reducing the capacity.

By the way, the code of each of the above-mentioned coding methods is a variable length code in which the number of bits is not constant for each run length. For example, in the code of the MH system, it is data of 2 bits to 13 bits.

In the case of the above proposal, the decoding circuit of the MH code is a circuit that sequentially generates various MH codes, a circuit that compares the generated MH code with a bit string of encoded data, and a bit matching circuit that has a maximum of 13 bits. It is composed of a circuit for validating only the number of bits of each code.

[Problem to be Solved by the Invention] In this case, the circuit for validating the collation of the predetermined bit is composed of a large number of gate circuits and a ROM for generating a control signal for controlling the gate circuits. .

For this reason, another ROM is required in place of the ROM for code conversion, and a large number of gate circuits are also required. Therefore, there is a problem that the amount of hardware is not significantly reduced.

An object of the present invention is to provide a variable-length code detection circuit that solves the above problem and reduces the amount of hardware.

Means for Solving the Problems According to the present invention, continuous data of the number of bits corresponding to the maximum length code is extracted from a data string in which variable length codes are continuous, and this is extracted by a code generated by code generation means and a bit unit When matching is detected and mismatching is detected, and when a mismatching bit is detected, all bits after the mismatching bit directed toward the end bit direction of the continuous data are forcibly determined as mismatching by the matching determination unit, Of the bits determined by the collation determining means, a check is made to determine whether a bit corresponding to the number of bits indicated by the code length generated by the code length generating means matches or does not match. Is determined as a code, and the code in new continuous data including the remaining bits is determined. The next code and the code length are generated from the raw means to determine the code.

[Action] The continuous data to be processed and the generated code are always collated for the maximum number of bits, the collation result of the bit corresponding to the code length is determined, and the code in the continuous data is detected. It is possible to determine whether data matches or does not match only the number of bits of the data, and to detect each code in a data string in which a plurality of codes having an inconsistent number of bits are consecutive with a very simple configuration. Become.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the arrangement of an image information decoding apparatus according to one embodiment of the present invention. In the figure, CP
U1 controls the apparatus and reproduces the decoded image information from the run length of the identified image information.

The shift register 2 latches 13 bits of coded image information input one line at a time by a serial signal and outputs it as a serial signal.

As shown in FIG. 2, the MH code ROM 3 inputs each signal indicating the black and white color and the run length of the image information, and outputs the MH code and the code length data which is the number of bits.
The stored MH codes are known, and some MH codes are used in common for black and white for white pixels and black pixels. The codes for the white pixel and the code for the black pixel are respectively stored in run lengths 0 to 63 and 64 to 1728 in 64 steps. Similarly, the code common to black and white is 17
Data from 92 to 2560 is stored. And each MH
The code is data of various patterns from the shortest 2 bits to the longest 13 bits.

The matching circuit 4 includes exclusive OR circuits 401 to 413,
Image information output from shift register 2 and MH code ROM3
This is to collate the MH code output from the.

The judgment signal output circuit 5 controls the output signal of the collation circuit 4, and the output of the exclusive OR circuit 401 is output from this circuit as it is, while the output of the exclusive OR circuit 401 is output from the exclusive OR circuit 402. Is input to the OR circuit 501. The output of the OR circuit 501 is output from this circuit as it is, and the signal and the output of the next exclusive OR circuit 403 are input to the OR circuit 502. Similarly, the outputs of the exclusive OR circuits 404 to 413 are output via the OR circuits 503 to 512.

The multiplexer 6 selects and extracts one of the output signals of the determination signal output circuit 5 based on the code length data output from the MH code ROM 3.

With the above configuration, when the image information decoding apparatus according to the present embodiment starts operation, image information encoded in the MH system is sequentially input from the outside. At this time, as shown in FIG. 3, the CPU 1 first sets 13 bits of the transferred image information in the shift register 2 (process 1001).

Then, for example, "white", run length "0",
One signal indicating the color and the run length is input to the MH code ROM 3 (process 1002).

Thereby, the corresponding MH code and code length data are output from the MH code ROM3. The MH code is the matching circuit 4
Is input to In this case, codes having less than 13 bits are sequentially input from the exclusive OR circuit 401 in the 413 direction. Also,
The image information output from the shift register 2 is also sequentially input from the exclusive OR circuit 401 to 413 from the first bit.

Thus, the image information and each bit of the MH code are collated. Then, the outputs of the exclusive OR circuits 401 to 413 become “0” when the collation results match and “1” when they do not match.

Assuming that a signal of "white" and a run length of "0" is input to the MH code ROM 3 as described above, an 8-bit MH code shown in FIG. 2 is output. Then, the code is compared with the image information from the first bit to the eighth bit of the code.

As a result of this collation, for example, if it is determined that there is a mismatch between the bits below the eighth bit, one output of the exclusive OR circuits 401 to 413 corresponding to that bit becomes “1”. Then, in the determination signal output circuit 5, the signal of "1" is sequentially transmitted to each OR circuit corresponding to the bit and thereafter, and the output of the determination signal output circuit 5 is "1""become.

On the other hand, the code length data output from the MH code ROM 3 is input to the multiplexer 6. Multiplexer 6
Of the output signals of the determination signal output circuit 5, one signal corresponding to the number of bits indicated by the code length data is detected by the detection signal D.
Selective output.

Now, since the code length data indicates 8 bits, a signal of “1” corresponding to the 8th bit is output as the detection signal D.

After outputting a predetermined signal to the MH code ROM 3, the CPU 1 checks the detection signal D (process 1003), and when the signal is “1” (Y in process 1003), next, for example, “white”, Another signal such as a run length "1" is output. In this way, the signals of each run length and each color are sequentially input to the MH code ROM 3 and the detection signal D is checked (processing 1002).
What).

By the way, when the MH code of a specific number of bits output from the MH code ROM 3 and all the bits of the image information output from the shift register 2 match, the corresponding bit output of the matching circuit 4 becomes “0”, and Each output of the determination signal output circuit 5 also becomes “0”. Thus, the multiplexer 6
Becomes "0".

When the detection signal becomes “0”, the CPU 1 reproduces the decoded original image information based on the black and white and the run length of the signal output to the MH code ROM 3 at that time (process 1004).

Next, it is determined whether there is still image information to be processed (process 1005). If there is image information (Y in step 1005), the image information in the shift register 2 is now decoded.
Shift by the code length of the MH code and set the next image information (to process 1001).

Thereafter, the same processing as described above is repeated. When there is no more image information to be processed (N in process 1005), the above operation is terminated.

As described above, in the present embodiment, the comparison result of each bit from the first bit to the thirteenth bit output from the matching circuit 4 does not match any one of the bits in the determination signal output circuit 5. If there is, signal control is performed so that all bits after that bit do not match.

Thus, the comparison result can be determined only by checking the output signal of the determination signal output circuit 5 corresponding to the code length. Therefore, unlike the related art, a large number of gate circuits for controlling the number of effective bits of the matching circuit, a ROM for generating a signal for controlling the gate, and the like are not required, and hardware can be reduced.

The OR circuits 501 to 512 are connected in multiple stages in the decision signal output circuit 5. However, since such a gate circuit operates at a relatively high speed, the delay time through all stages is equal to the access time of a normal ROM. It is considered below or equivalent, and there is no problem.

Further, in the above embodiment, the example of the apparatus for decoding the image information of the MH code has been described, but other encoding methods may be used.
Furthermore, the present invention is naturally applicable to the case of decoding not only image information but also various variable length codes.

[Effects of the Invention] As described above, according to the present invention, each generated code and the data string to be processed are collated one bit at a time, and if the collation result does not match any one of the bits, The matching result after the bit is unconditionally output as a mismatch, and one of the signal outputs corresponding to the generated code length is used to determine the presence or absence of each code in the data string. So, as before,
A large number of gate circuits, ROMs for generating control signals, and the like are not required, and hardware can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image information decoding apparatus according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of data stored in an MH code ROM, and FIG. 3 is an operation flowchart of a decoding process. 1 ... CPU, 2 ... Shift register, 3 ... MH code RO
M, 4 ... Matching circuit, 5 ... Judgment signal output circuit, 6 ...
Multiplexer, 401-413 ... Exclusive OR circuit, 501
~ 512 …… OR circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/41-1/419

Claims (2)

(57) [Claims] 1. A variable length code detection circuit for detecting each code in a data string in which a plurality of codes each having a non-constant number of bits are continuous, code generation means for sequentially generating each code, Code length generating means for sequentially generating a code length indicating the following, data extracting means for extracting continuous bit data for the number of bits corresponding to the maximum length code from the data string, continuous data extracted by the data extracting means, The code generated by the code generating means is collated bit by bit to detect a match or mismatch, and when a mismatch bit is detected, all bits after the mismatch bit toward the end bit direction of the continuous data are forcibly applied. And a code length generated by the code length generating means in the collation determining means. A check is made to determine whether a bit corresponding to the number of bits is coincident or not, and in the case of a coincidence, the data extracted by the data extracting means is discriminated up to the bit number as a code, and new continuous data including the remaining bits is determined. A variable length code comprising: a code discriminating means for discriminating a code while generating a next code and a code length from the code generating means and the code length generating means when the codes do not match. Detection circuit. 2. The collation judging means converts the continuous data extracted by the data extracting means and the data generated by the code and code length generating means from the first bit to 1 bit.
Matching means for simultaneously checking bits one-to-one and outputting match / mismatch signals one bit at a time, and a determination signal indicating the final determination result for each bit from the matching means is logically combined with a determination signal of a preceding bit. 2. The variable length code detection circuit according to claim 1, further comprising a determination signal output means for obtaining and outputting the sum.