JPS59225676A - Generating circuit of bit length variable code - Google Patents

Abstract

PURPOSE:To match a binary code whose bit length is variable to a control system having a boundary with the hardware of simple constitution by allowing this circuit to code directly serially a data read from a read only memory ROM. CONSTITUTION:A register 1 for information to be coded is a register into which an output of a run length counter counting the run length until point of time when the continuity of white or black levels in, e.g., a picture input are changed is stored. The value of this register 1 is fetched to an address register 10 representing an address of a conversion ROM11. The conversion ROM11 is provided with a code constituting bit section 20 for, e.g., 1-bit's share at each entry corresponding to an address represented by the address register 10, an address informing section 21 to which the address information of the entry stored with the next code constituting bit is stored, and an end flag section 22 representing whether or not a bit is an end bit as to one bit length variable code, and those pieces of information are stored depending on the content of the bit length variable code converted in advance.

Description

Detailed Description of the Invention (5) Technical Field of the Invention The present invention is a variable bit length code generation circuit, in particular, a variable bit length code generation circuit that serially outputs a variable bit length code such as a so-called modified number code. The present invention relates to a variable bit length code generation circuit that can easily perform boundary-matched output to a data bus for a control system having a control system.

[F]) Prior Art and Problems For example, in facsimile image communication, etc., there is a modifier-human encoding method as a band compression encoding method. In this method, white or black information and a continuous length of white or black (hereinafter referred to as run length) are used as encoded information, and for patterns with a high degree of occurrence, a short bit length C is used. Patterns that occur less frequently are encoded with a longer bit length to efficiently compress the band.

If the variable bit length code described above is to be processed serially in a control system, it may be possible to process it sequentially as it is. In this case, it is necessary to separate a series of bit length variable code strings at the 8-bit or 16-bit word boundary and output them in parallel on, for example, a data bus.

FIG. 1 shows an example of a conventional circuit. In the figure, 1 is an encoded information register, 2 is a conversion ROM, 3 is a parallel/serial converter, 4 is an effective code length counter, and 5 is a serial/serial converter.
A parallel converter, 6 a boundary counter, and 7 a data bus.

For example, coded information such as run length.

When stored in the encoded information register 1, the conversion ROM 2 is referenced by the address corresponding to the run length. The conversion ROM 2 stores in advance the contents of the variable bit length code corresponding to the information to be encoded for each variable bit length code to be converted.

Each effective code length information is stored. Depending on the length of the variable bit length code stored in the conversion ROM 2, a dummy part as shown by the cross in FIG. 1 is added so that the R extension unit has a fixed length. It's covered in water. Then, by accessing the conversion ROM 2, the converted code including the dummy part is output to the parallel-to-serial converter 3, and its effective code length information is set in the effective code length counter 4. The parallel/serial converter 3 extracts only the valid part from the input information and outputs it serially until the valid code length counter 4 becomes 0.This serial output information is sent to the serial/parallel converter 5 and the boundary. - Converted by the counter 6 into parallel data corresponding to the data width of the data bus 7. That is.

The boundary counter 6 causes the serial/parallel converter 5 to perform word boundary matching using a count value corresponding to a data width of 8 bits or ]6 bits, reports it to the control system, and converts the bit length variable code. Output to data bus 7 in word units. Note that when the effective code length counter 4 reaches O, the coded information of the 9th order is used.

The conversion ROM 2 is accessed continuously.

According to the above conventional method (2), a circuit such as the parallel-to-serial converter 3 that converts parallel data to serial data is required, and when the amount of information to be encoded increases, the effective part becomes longer. , there is a problem in that the amount of hardware increases as the code length increases.

(Q. Purpose and structure of the invention The present invention aims to solve the above problems, and has a read-only memory (
This bit enables the direct serialization of data read from a ROM (ROM), thereby making a variable bit length binary code compatible with a control system having a counter with a simple hardware configuration. It is an object of the present invention to provide a bit length variable code generation circuit.Therefore, (1) the bit length variable code generation circuit of the present invention sequentially generates a bit length variable code based on information to be encoded, and generates a series of the generated bits. In a bit length variable code generation circuit that outputs a variable length code string by aligning it with a word boundary, each of the bit length variable codes generated is decomposed into each component bit, and information on each component bit is generated for each IJ. and a read-only memory for storing address information in which subsequent configuration bit information is stored, and based on the address information corresponding to the encoded information or the address information in which the subsequent configuration bit information is stored. The present invention is characterized in that the read-only memory is sequentially accessed by the read-only memory, and the constituent bit information extracted from the read-only memory is aligned with word boundaries. This will be explained below with reference to the drawings.

(To) Embodiment of the Invention FIG. 2 shows the configuration of an embodiment of the present invention, FIG. 3 is a diagram for explaining the configuration of the conversion ROM shown in FIG. 2, and FIG. 4 shows the configuration of the embodiment shown in FIG. 2. An example is shown. In figure 1, code 1
, 5, 6.7 correspond to FIG.

10 is an address register, and 11 is a conversion ROM.

12 is a latch for end detection, 20 is a code configuration bit section, 2
1 represents an address information section, and 22 represents an end flag section.

In the case of the present invention, for example, with the configuration as shown in FIG. 2, a serialized variable bit length code is output directly from the conversion ROM II. For example, the Modify Huffman method.

This is an international standard for compression and decompression methods for facsimile machines, but when processing such variable bit length codes in units of words such as 8 bits or 16 bits, the encoded information must be converted into variable bit length codes. It is necessary to convert and align the result to word boundaries.

The encoded information register 1 is a register in which, for example, the output of a run length counter that counts the run length up to the point where the continuous white or black in the image input changes is stored. The value of this register 1 is the conversion ROMII
is loaded into address register 10 indicating the address of .

The conversion ROM II contains the address indicated by the address register 10 (=for each corresponding entry).

For example, the code configuration pit section 20 for one bit, the address information section 21 that stores the address information of the entry in which the ninth order code configuration bit is stored, and the terminal bit for one bit length variable code. A termination flag section 22 indicating whether the bit length variable code is converted or not is provided, and such information is stored and stored in accordance with the contents of the variable bit length code to be converted in advance.

For example, as shown in FIG. 3(A), the bit length variable code corresponding to the encoded information A is "l I Olj, and the bit length variable code corresponding to the encoded information B is r
loolooJ, and encoded information C (=corresponding bit length variable code is J]01j. Transformation R
In the OMII, encoded information to be converted is stored in advance, as shown in FIG. 3 (b), for example.

When encoding is performed based on information to be encoded A.

In FIG. 3(b), first, from the encoded information person (from the corresponding start address AO), the value of the code configuration bit part 20 is “
1" is taken out. This bit is output as the first bit of the variable bit length code.

Simultaneously with the output of this bit, the address A1 of the entry in which the 9th order 1 bit is stored is read out from the address information section 21. Next, the second bit value rlJ and address A2 are read from the entry at address A1, and the constituent bit value "1" is output as the second bit of the variable code. Similarly, the configuration bit value rOJ is output from address A2, and subsequently the configuration bit value "1" is output from address A3. Since the content of the end flag section 22 of the entry at address A3 is "1", when the processing for the entry at address A3 is completed, it is determined that the encoding for the information to be encoded A has been completed. That is, for encoded information A, addresses AO, AI
, A2. rlJ sequentially from the code configuration bit part 20 of A3,
rlJ, rob, rlJ are read,
It will be output serially and encoded. Note that when the termination is detected by the termination flag section 22,
Encoding of the next encoded information 1, for example B, immediately continues. Regarding encoded information B, addresses BO, Bl, B2°B3. B4. From B5, sequentially I
11. roj, rob, rlj.

rob, rOJ will be output. Similarly, the coded information C is sequentially I11 . . . from addresses CO, C1, C2. rOJ, Ill are output. .

By the way, the encoded information A (2 corresponding code “1101
The three bits on the right side of "" correspond to the code "101" corresponding to the encoded information C. Therefore, in such a case 1, for example, as shown in FIG. 3, the address CO can be stored in the address information section 21 of the address AO, so that the encoded information at the rear can be shared and the memory can be saved.

Note that in this example, the end of one encoding is determined by the flag in the end flag section 22.

For example, by setting a special address value in the address information field 21, the process may automatically proceed to the next encoding process, without necessarily relying on the termination flag.

The conversion ROMII is accessed as described above (from the second point, encoded information is directly output serially from the conversion ROMII.
depends on the contents of the termination flag section 22.

The address set to address register 10.

This is a latch that outputs a signal that determines whether to obtain the encoded information from the register 1 or the conversion ROM 11. The bit information sequentially read from the code configuration bit section 2° of the conversion ROM II is input to the serial/parallel converter 5. The serial/parallel converter 5 is a conversion ROMII
Converts serial data to parallel data in synchronization with the output of the data. Boundary counter 6 is serial
When the parallel data in the parallel converter 5 matches the boundary, that is, when the data width of the data bus 7 is 8 bits, and the count is 8, this fact is reported to the control side (not shown). do. The control side is
If counter 6 reports that the boundaries match.

Via the data bus 7, a code string, for example the one shown in FIG. 4, aligned to the word counter, such as a modified Huffman code, can be read word by word.

■ As described in detail, according to the present invention, codes with variable bit lengths can be directly serially output from the read-only memory (I(OM)), so the hardware does not need to be aware of the effective code length. The configuration becomes simpler, the amount of material is reduced, and costs can be reduced.Also,
An increase in the amount of information to be encoded can be dealt with simply by increasing the ROM capacity, which has the effect of reducing the impact on the hardware.

[Brief explanation of drawings]

FIG. 1 is an example of a conventional circuit, FIG. 2 is a configuration of an embodiment of the present invention, FIG. 3 is a diagram for explaining the configuration of the conversion ROM shown in FIG. 2, and FIG. 4 is an example of the implementation shown in FIG. Show example output -r
O In the figure, 1 is an encoded information register, 5 is a serial/parallel converter, and 6 is a boundary counter. Reference numeral 7 represents a data bus, 11 a conversion ROM, 20 a percussion configuration bit section, 21 an AT/S information section, and 22 a termination flag section. Patent applicant: Usatsuk Electronic Industry Co., Ltd. Representative Patent Attorney: Hiroshi Mori 1) Hiroshi (2 others) 41

Claims (1)

[Scope of Claims] A variable bit length code generation circuit that sequentially generates a variable bit length code based on information to be encoded, and outputs the generated series of variable bit length codes aligned with a word boundary, Each bit length variable code generated above is '
Decomposed into Zr configuration bits. Each IJ is provided with a read-only memory that stores the information of each of the above-mentioned constituent bits in pairs with the address information storing the subsequent constituent bit information, and stores the address information corresponding to the above-mentioned encoded information or the above-mentioned subsequent The read-only memory is sequentially accessed based on the address information in which the configuration bit information is stored, and each of the configuration bit information extracted from the read-only memory is aligned with a word boundary. Bit length variable code generation circuit.