JP3087394B2 - Binary arithmetic encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary arithmetic encoder for encoding a binary arithmetic code which is a distortionless data compression technique.

[0002]

2. Description of the Related Art A binary arithmetic encoder proposed by Langdon is shown in FIG. 3 (IBM, Journal of Research and Development, 28 (2), 135-).
149, 1984). In FIG. 3, reference numeral 11 denotes a predicted bit (`0` or` 1`) for predicting whether the next input bit is `0` or` 1` and a probability (2 ^−k ) that the predicted bit does not appear. A table that stores sets of values (K),
12 is a register for storing output bits, 13 is a register indicating a main part of the appearance probability value of the input sequence up to the encoding time,
Reference numeral 14 denotes a processor which performs central operations of encoding for performing subtraction and shift on the register 12 and addition and shift on the register 3, and 15 a controller for controlling output from the register 12 to the buffer 16. is there.

[0003] In order to encode the next input bit, it is determined from the past input bit sequence which set of the table 11 is to be used. Based on the result of comparison between the expected bit and the actual input bit, the processor 14 adds “1” to the lower digit corresponding to K or shifts the register 12 by K or shifts the register 13 to K. Either reduce the digit by '1' from '1' or reset. Register 13
When the most significant bit of the register 13 becomes "0" as a result of the subtraction, the register 13 is shifted by one bit so that the most significant bit becomes "1". At this time, the register 12 is also shifted by one bit. I do. If necessary, the expected bit or probability value (K) in Table 1 is rewritten. FIG. 2 shows the above flow in a flowchart.

[0004] The controller 15 stores the buffer 1 from the register 12.
6 is controlled. For example, if the output is performed in byte units, it is necessary to prevent the output byte from being affected by the carry due to the addition to the register 12. Then, when '1' continues for a long time in the register 12, output to the buffer 16 cannot be performed forever, and the length of the register 12 must be set to infinity.
Encoding time delays are also significant. To avoid this, look at the register 12 at each byte break from the beginning and check if all the bits in each byte are '1', and if so, after the 1 byte's sequence of '1's '
By inserting a few bits of 0's, the carry of the carry was stopped there, and all the bytes of '1' were output from the register 2 to the buffer 6.

[0005]

In order to speed up binary arithmetic coding by bit-serial by coding several bits in parallel, the output in the case of parallel has been previously used. It is desirable to be completely compatible and compatible with the case of bit serials.
The problem at that time is that, as described at the end of the section of the "conventional method", when a sequence of "1" appears in the register 13 in FIG. 3, "0" is inserted. In other words, if encoding is performed in parallel, and at what bit number the bit encoding is originally performed by bit serial, '0' must be inserted. Carry-over may occur, in which case the output result will be different. However, if the arrangement of '1's is detected for each input bit, the encoding speed cannot be increased even if the parallel processing is performed.

[0006]

SUMMARY OF THE INVENTION A binary arithmetic encoder according to the present invention is a binary arithmetic encoder which is a distortion-free data compression device, and is output as a result of encoding which is a part of the encoder. A function of controlling the output from the register by judging from the current state of the register whether or not there is a possibility that a sequence of ones of a certain length may appear in the register for storing bits while encoding a certain number of bits. It is characterized by having.

[0007]

By judging in advance whether there is a possibility that a sequence of '1's will appear during the encoding of a fixed number of input bits, the output bits are converted every time one bit is encoded during the period when there is a possibility. It is observed whether or not a sequence of "1" appears in the register to be stored, and if not, it is not necessary to detect the sequence of "1" during that time. In this way, if the process of detecting the arrangement of “1” in the register is reduced,
Higher coding speed can be expected. In particular, in the case of parallel processing, it is possible to match the output data with that of bit serial processing while maintaining high speed.

[0008]

FIG. 1 shows an example for realizing such an invention, in which encoding is performed in 4-bit parallel.
Table 7 holds the pattern of the bit string of the register 3 in the case where all 1 byte may be "1" when the byte is viewed from the beginning of the register 3 in the process of encoding the next 4 bits. In advance, it is determined whether or not to detect the arrangement of “1” in the process of encoding the next 4 bits by matching the bit string in the register 3. The output from the register 2 to the buffer 6 is performed in byte units when 20 bits or more are stored in the register 2 so as not to be affected by carry.

For example, consider the following situation. When the input bit and the expected bit are equal, 1 is added to any of the least significant digits to four digits higher in the register 3, and 1 is subtracted from the register 2 accordingly. If the expected bits are not equal, consider the case where register 3 is shifted to the probability value and register 2 is reset so that the highest digit is 1 and the remaining digits are 0.
Register 2 may have 5 bits. In the table 7, as shown in FIG. 4, a pattern corresponding to the current bit number n in the register 2 is registered.

Each time the 4-bit encoding is completed, the register 2 is compared with the pattern shown in FIG. The bit pattern of the register 2 is compared with the portion other than ** in FIG. 4. If the bit pattern of the register 2 is smaller than the pattern of FIG.
Encoding can be performed at a stretch in 4-bit parallel. If the pattern is larger than the pattern shown in FIG. 4, this is essentially the same as in the case of bit-serial encoding, and the sequence of '1's is detected each time each of the four bits is encoded. When a sequence of “1” s for one byte appears, the output from the register 2 to the buffer 6 is performed.
Insert 0 '. This output control process is shown in the flowchart of FIG.

[0011]

In the embodiment, when it is considered that "0" and "1" appear at random in the register 2 of FIG. You only have to do it once every 10 times. In other words, according to the conventional method, when the encoding is performed 10 times in 4-bit parallel, the arrangement of the register 12 must be checked 40 times, but in the method proposed this time, the register 2 is checked 14 times. In this case, the number of times is about 30% and 5 minutes in the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a binary arithmetic encoder according to the present invention.

FIG. 2 is a flowchart showing an algorithm of a binary arithmetic code.

FIG. 3 is a block diagram showing a configuration of one embodiment of a conventional binary arithmetic encoder.

FIG. 4 is a table for holding a bit pattern to be compared with an output bit register 2;

FIG. 5 is a flowchart showing a process of output control at the time of 4-bit parallel encoding using the table of FIG. 4;

[Explanation of symbols]

1,11 A table holding a set of predicted bits and a probability value (K) 2,12 A register storing output bits 3,13 A register indicating a main part of a probability value of the input sequence so far 4,14 Register 3, 13, a processor for controlling the operations on the registers 2, 12 and the tables 1, 11, 5, 15 a controller for controlling the output from the registers 2, 12 to the buffers 6, 16 7 a bit pattern for collating with the bit string of the register 2 Table that holds the data 8 Serial-parallel converter

Claims (1)

(57) [Claims] 1. An input bit sequence is a plurality of bits parallel and distortion-free.
A binary arithmetic encoder that compresses only data and encodes it by an arithmetic operation using the probability value corresponding to the input bit.
The current bit string and the encoding of the register (3)
Of the register (2) that stores the bits output as a result of the
For the bit string of the above, the bit string and the table (7) are stored in advance.
By comparing with the registered bit string,
Results a fixed number of input bits from the time to determine the presence or absence of possibility appears arrangement of the first fixed length to the encoded result output by storing the bit register (3) during the encoding, and the encoded Register for storing output bits
(2) A binary arithmetic encoder having a function of controlling an output from (2) .