JPS5883473A - Picture signal encoding system - Google Patents

Abstract

PURPOSE:To speed up reading, by storing an instruction code encoding the result of collation between the number of consecution of the same kind of picture signals and the preceding picture signal, and encoding the signals with read- out instructions. CONSTITUTION:The change in black/white of a picture signal 1 inputted in synchronizing with a timing clock 2 is detected at a picture element change detection circuit 3 and the number of consecutive bits of the same signals is counted at a counter 4. The types of change from white to black or black to white and the number of consecution of the same signals are sequentially stored in a first-in first-out memory 5. The code and length of code corresponding to the length of each signal are stored in an ROM6, the code is stored in a P/S shift register 7 and the code length is in a register 8 tentatively. A clock forming circuit 9 generates clocks for the length of codes, the code of the register 7 is converted into a serial code and inputted to a memory 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an encoding method for image signals read at high speed. A coding method that suppresses the redundancy of the image signal is employed. For example, in Group 3 facsimile equipment, the one-dimensional encoding method is a run-length encoding method using a modified Huffman (ME) code, and the two-dimensional encoding method is a modified read (MR) encoding method. have been adopted respectively.

A run-length encoding method using an MH code is an encoding method in which the number of consecutive white or black bits of an image signal converted into a binary white/black signal is expressed by an MH code. The MR encoding method uses the position of a pixel that changes on the currently encoded line (the position of change from a white signal to a black signal, or the position of a change from a black signal to a white signal) from the position of a pixel that has already changed on the encoded line. This is a two-dimensional sequential encoding method that sequentially encodes using the position of the encoded changed pixel or the relative distance from the position of the nearest changed pixel on the previous reference line, and the encoding algorithm has been published. Things” CCITT.

5GXIV (Facsimile) Eastern Conference Report 1 Journal of the Society of Imaging Electronics, Vol. 9, No. 1 (1980).

The above run-length encoding method using Ml (code) and M
In a sequential encoding method such as the FI encoding method, a code is determined only after a pixel changes from white to black or from black to white. Further, the code length is variable.

Conventionally, in such an encoding method, considering that there are successive pixels that change in the encoded image signal and the corresponding code is determined, encoding is performed based on the speed at which the image signal is input. Therefore, it is necessary to perform the processing at a speed that is twice the maximum code length. Therefore, as the reading speed increases, the encoding speed becomes abnormally fast. On the other hand, when the encoding speed is reduced, if the pixels change continuously or at short intervals, it is necessary to temporarily suspend reading until encoding is completed.

The purpose of the present invention is to implement first-in, first-out (FIFO) between a block that detects a changed pixel and determines a corresponding code and a block that creates a serial code.
A memory is provided, an instruction code that instructs to create a determined code is written in the FIFO memory, and this instruction code is compared and converted into a serial code to reduce the encoding speed and enable continuous or short intervals. To provide an image signal encoding system that almost eliminates temporary interruption of reading even when a code is determined.

The present invention will be explained in detail below with reference to Examples.

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an input terminal for an image signal, into which a binary signal of white or heat is input. 2 is a timing clock input terminal, and the image signal input to input terminal 1 is input in synchronization with this clock. 3 is a pixel change detection circuit, 4
6 is a counter, and 6 is a FIFO memory. A pixel change detection circuit 3 detects a change in the image signal from a white signal to a black signal, or from a black signal to a white signal. Counter 4 is a counter that counts the number of continuous bits of the white signal or black signal.
When a change in the signal is detected by the pixel change detection circuit 3, the FIF
Write the value of the counter 4 and information on whether the white signal changes to a black signal or changes from a black signal to a white signal to the O memory 6, then clear the counter 4 and write the number of continuation bits of the next white or black signal. Count. With this operation, the run lengths of the white signal and black signal are stored in the FIFO memory 6 in order. 6 is the ROM, 7 is the P/S shift register, 8 is the register, 9 is the clock generation circuit, and 10 is the memory. . R
The OP/S soft register 7 temporarily stores the code read from the ROM 6, and the register 8 stores the code corresponding to the run length of the white signal and the run length of the black signal and its code length. The code length read from the ROM 6 is temporarily stored.

The clock generating circuit 9 generates a clock corresponding to the code length stored in the register 8, converts the parallel code stored in the P/S shift register 7 into a serial code, and inputs the serial code to the memo I710. Now, assuming that the run length of the white signal or black signal is stored in the FIFO memory 6, the oldest data of this is read out, the ROMe converts it into the corresponding code and code length, and the code is converted into P/S. shift register 7
Then, the code lengths are input to the registers 8, and the clock generation circuit 9 generates a clock corresponding to the code length, and the clocks are input to the memory 10. When this operation is completed, the FIFO memory 6 is checked, and if data is stored, the oldest data is read out and the same operation is performed. The code is stored.

Next, another example will be described.

FIG. 2 is a diagram showing its configuration. In FIG. 2, reference numeral 11 denotes an input terminal for an image signal, into which a white or black binary signal is input. 12 is a timing clock input terminal. Reference numeral 13 denotes a memory in which the image signal of the previous line is stored. 14
is the pixel matching circuit.

Compare the change position of the currently encoded image signal from a white signal to a black signal or from a black signal to a white signal with the change position of the image signal stored in the memory 13 one line before. Then, create an instruction code that instructs the creation of the corresponding code.

The FIFO memory 16 sequentially stores the instruction codes created by the pixel matching circuit 14.

Also, 16 is ROM, 17 is P/S shift register, 18
1b is a register, 1b is a clock generation circuit, and 20 is a memory. The ROM 16 stores a code corresponding to the instruction code generated by the pixel matching circuit 14 and its code length. The P/S shift register 17 stores the code read from the ROM 16, and the register 18 stores the code length read from the ROM 16. The clock generating circuit 19 generates a clock corresponding to the code length stored in the register 18, converts the parallel code stored in the P//S shift register 17 into a serial code, and inputs the serial code to the memory 20. When an instruction code is stored in the FIFO memory 6, the oldest created instruction code is read out, converted into a code and code length corresponding to this in the ROM 15, and the code is transferred to the P/s shift register 17. Then, the code lengths are respectively input to the registers 18, and the clock generation circuit 19 generates a clock corresponding to the code length, and inputs the generated clocks to the memory 1o.

When this operation is completed, the FIFO memory 6 is checked again, and if an instruction code is stored, the oldest created instruction code is read out and the same operation is performed.

As a result of the above operations, 20 corresponds to the image signal and 7
The code is stored.

As explained above, the present invention does not directly create the determined code, but instead writes the instruction code corresponding to the code into the FIFO memory, while the code creation block reads the instruction code from the FIFO memory and performs encoding. be. Therefore, even if the codes are determined continuously or at short intervals, the corresponding instruction code is simply written into the FIFO memory, and the written instruction code is used when the same type of signal is received. (When the sign has not been determined yet)
Then, the FIFO memory can be read out and converted into the corresponding serial code, and the encoding speed for creating the serial code can be lowered. Also, if the FIFO memory has enough room, Temporary interruptions in reading can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an apparatus for realizing an image signal encoding method according to an embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. Input terminal, 2... Clock input terminal, 3...
・Pixel change detection circuit, 4... Counter, 6...
...FIFO memory, 6...ROM, 7.
River: P/S synt register, 8: Register, 9: Clock generation circuit, 10: Memory.

Claims (3)

[Claims] (1) means for creating an instruction code for instructing to create a code corresponding to the read image signal; A first-in/first-out memory is provided for storing the instruction codes in the order in which they are created. The image signal encoding method is characterized in that an image signal is encoded by reading an instruction from the first-in/first-out memory and creating a code corresponding to the instruction code. (2) The read image signal includes means for creating an instruction code that instructs to create a code corresponding to the number of consecutive run lengths of the same type of signal of the read image signal and the type of the signal. 2. The image signal encoding method according to claim 1, wherein the image signal is encoded according to the number of run lengths of consecutive image signals of the same type. (3) It has a means for comparing a read image signal with an image signal read earlier, and a means for creating an instruction code for instructing to create a code corresponding to the result of the comparison. An image signal encoding system according to claim 1, characterized in that: