JPH0378372A - Picture compression circuit and picture restoration circuit - Google Patents

Abstract

PURPOSE:To compress picture data into a code which is of fixed length and is easy to understand by outputting a compressed code consisting of a count value outputted by a counting means and a picture element value to show the distinction of white or black of continuous picture elements at every detection of a picture element alteration detecting means. CONSTITUTION:The code length of compressed data (compressed code) generated from serial binary picture data to be outputted in order of the scanning of the picture is fixed to be 8-bits. Then, the number of picture elements to constitute the train of only white picture elements or only black picture elements appearing alternately in the serial binary picture data is counted by a counter 3, and the compressed code C consisting of total 8-bits of 1-bit of symbol of the distinction between white and black of the picture element and 7-bits of the count value of the picture elements in a continuous picture element group is generated for every continuous white picture element group and every continuous black picture element group. However, when the count value of the picture elements of the continuous picture element group exceeds 7-bits length, the compressed code is generated by bringing processing once to an end at the maximum 127-picture elements which can be expressed by 7-bits, and subsequently, counting is newly started form the 128-th picture element, and the next compressed code is generated. Thus, the processing by a general purpose CPU is made easy.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an image compression circuit that realizes data amount compression in a device that stores image data such as an optical character reader (OCR) or an optical file system, and an image compression circuit that converts this compressed data (compression code) into original image data. This invention relates to an image restoration circuit that restores images. In the following figures, the same reference numerals indicate the same or equivalent parts.

[Conventional technology]

FA is a compression method for serial binary image data obtained by scanning the original image using an image scanner, etc.
MH (Modified Huff), which is the standard for
man) method, MR (Modified Read)
The method is known.

[Problem to be solved by the invention]

However, in this conventional image compression method, when converting pixel appearance patterns into codes, short codes are assigned to patterns that appear frequently, so the code length of the compressed data is undefined and the code length is variable. It is difficult to understand without inverse transformation itself. Also, 60% for the pixel pattern
More than one code correspondence table and a comparator are required.
There is a problem in that high-speed processing with a general-purpose CPU is difficult. Therefore, in order to solve the above problems, the present invention provides an image compression circuit that uses a simple circuit to compress image data into a fixed-length and easy-to-understand code, and a similarly simple circuit that uses the compressed code to restore the original image data. The present invention aims to provide an image restoration circuit.

[Means to solve the problem]

In order to solve the above-mentioned problems, the image compression circuit of the first invention has the following features: Pixel switching detection means for detecting switching between each continuous pixel for one or more continuous white pixels and one or more continuous black pixels that appear alternately in sequence, (2-bit shift register 2.EXOR
circuit 5, etc.) Counting means (7-bit counter, etc.) that counts and outputs the number of consecutive pixels from the previous detection to the current detection in the form of a count value of a predetermined bit length, for each detection by the pixel switching detection means. 3, etc.), and a compressed code (such as C) consisting of a count value outputted by the counting means and a pixel value representing whether the continuous pixel is white or black is transmitted every time the pixel switching detection means detects a compressed code (such as C). It is assumed that j is output to (to data bus DB2, etc.). Further, the image restoration circuit of the second invention is characterized in that l or a plurality of white continuous pixels and one or a plurality of black continuous pixels appear sequentially and alternately in the serial binarized image data outputted in the scanning order of the r image. A compressed code created for each continuous pixel of , from a count value of a predetermined bit length representing the number of the relevant continuous pixels, and a pixel value representing whether the relevant continuous pixels are white or black. Compressed code (C
etc.), a circuit for restoring the original serial binary image data includes a latch means (data latch 11, etc.) that latches the pixel values in the compressed code, and a count value in the compressed code that also counts down. a counting means (such as a down counter 14), and an image data output means (8 pins) that serially outputs pixel data having a pixel value latched by the latch means while the counting means is counting; and an S/P conversion circuit. 12 etc.) and j
shall be taken as a thing.

[For use]

1) Regarding the first invention: The code length of compressed data (compressed code) created from serial binary image data output in the order of image scanning is fixed to 8 bits. Then, the number of pixels constituting a series of only white pixels and only black pixels that appear alternately in the serial binary image data is counted, and for each continuous white pixel group and continuous black pixel group, the number of pixels is divided into black and white pixels. A compressed code consisting of a total of 8 bits consisting of 1 bit of symbol and 7 bits of the count value of the pixels in the continuous pixel group is generated. However, if the counted value of a pixel in the continuous pixel group exceeds 7 bits, the count is stopped once at a maximum of 127 pixels represented by the 7-bit length, a compressed code is generated, and then a new count is started from the 128th pixel. Generates the following compressed code. 2) Regarding the second invention: Until the number of pixels in the compressed code is subtracted one by one by a down counter until it reaches O, pixel data corresponding to the pixel value in the compressed code is subtracted one by one as described above. Synchronize and serially output to restore the original image data corresponding to the compressed code.

【Example】

The present invention will be explained in detail below based on FIGS. 1 to 5. FIG. 3 shows an example of an original image to be subjected to image data compression. In the figure, Fl is the original image, and P is a pixel that takes a binary value of white (represented by "0" in this example) or black (represented by ° "1'" in this example).The original pixel F1 is in this case It is composed of a line L (LLL2.....---), which is a column of 16 (16 bits) pixels lined up in the horizontal (X) direction.In the present invention, the pixels on this line L are It is assumed that the compressed code of the image data is obtained by repeating the scanning operation in the horizontal (X) direction in the vertical (Y) direction (that is, while scanning the original image F1 in the raster direction). This shows a compression code for serial image data obtained by scanning.In line L1, white pixels, 3 bits, black pixels, 8 bits, and white pixels, 5 bits are lined up in order in the X direction. One by one for each consecutive pixel column, the fourth
A total of three compressed codes C (C1
l. CI2. C13) is produced. Here the compression code C
The first bit D7 of the 8-bit length indicates whether the pixel column in question is white or black, and the 7 bits following this first bit D6
~DO indicates the number of pixels in the pixel column. Therefore, even if the pixel string is of the same color, if the number of pixels exceeds 127, which can be represented by a 7-bit length, one compression code C is created for these 127 pixels, and the remaining From pixels, use the same method to create the following compressed code C
is made. FIG. 5 shows a similarly created compressed code for the next line L2. On this line 2, a white pixel of 6 bits, a black pixel of 2 bits, and a white pixel of 8 bits are lined up in this order, and the corresponding compressed codes C (C21, C22, C
23) is created. FIG. 1 shows an embodiment of the configuration of an image compression circuit that generates a compression code C while scanning the original image F1 as described above. In the figure, the input command LD from the control circuit 4
Based on I, the pixel columns on line L are sequentially input into an 8-bit parallel-to-serial converter circuit (51L, abbreviated as P/S for halal-serial) through the input data path DBI in 8-by-8 increments. ,
It is synchronized with the clock CKI output from the control circuit 4 and is input to the 2-bit shift register 2 as serial data. This 2-bit shift register 2 stores consecutive 2 bits of the input serial data while shifting them in order. Detect black or black-to-white reversal). This BXOR circuit 5
The output is given to the control circuit 4 via the OR circuit 6 as a compressed code output request 6a. On the other hand, 7-bit counter 3 is clocked CKI, so 8
) Count the number of data shifts of P/S conversion circuit 1,
It is output as 7-bit long data, and based on the output request 6a, the count output of this 7-bit counter 3 is used as the lower 7 bits of the compressed code C, and as the data stored in the 2-bit shift register 2. The older one
At the same time that the bit is read externally via the output data path DB2 as the first bit of the compressed code C indicating whether the pixel column is white or black, a clear signal CLI is output from the control circuit 4 and the 7-bit counter 3 is cleared. The contents are cleared. Therefore, the count output value outputted from the counter 3 to the output data path DB2 when outputting the output request 6a is the number of consecutive pixels of the same color on the line L, and similarly, the output data from the 2-bit shift register 2 at this time is the number of consecutive pixels of the same color on the line L. The data given to the path DB2 represents the color (white, black) of these continuous pixel columns of the same color. In other words, the aforementioned compressed code C is output from the output data path DB2 every time the output request 6a is output. However, even when the output count value of the 7-bit counter 3 reaches 127, this value is detected by the AND circuit 7, and the detected output cuff a is given to the OR gate 6 and output request 6a.
is output, and compressed code C is output. Next, FIG. 2 shows an embodiment of the configuration of an image restoration circuit which inputs the compression code C and restores the original image data. In the figure, based on an input command LD2 from the control circuit 15, the first pixel 1-D7 as pixel data representing the color of the pixel string in the compressed code C input via the input data path DB3 is sent to the data latch 11. Similarly, 7 bits D6 to Do as pixel count values in the compressed code C are taken into the down counter 14. Next, the pixel data taken into the data latch 11 is input, and the data is shifted by an 8-bit serial/parallel converter (serial/parallel is abbreviated as S/P) 12 in synchronization with the clock CK2. The number of times is counted by the 8-times counter 13 and down counter 14. The 8-times counter 13 requests output 1 every time it counts 8 times.
3a is output to the control circuit 15. As a result, control circuit 1
5 is 8 pixels) 8 parallel pixel data as a shift result of the S/P conversion circuit 12 is outputted as image data from the data bus DB4 to the outside, and a clear signal CL2 is outputted to the shift register 12. Then, the counter 13 is cleared eight times, and the operation of 12.13 is repeated from the beginning. On the other hand, the down counter 14 counts down the input pixel count value, and when it reaches 0, outputs an input request 14a to the control circuit 15. As a result, the control circuit 15 outputs the input command LD2 again and transfers the data of the next compressed code C to the data latch 11. It is taken into the down counter 14. As a result, the above-described operation of this image restoration circuit is repeated from the beginning. In this embodiment, data of 16 pixels per line is converted into 8 bits x 3 codes, so the compression effect is small. However, when handling images with a resolution of 400 dpi, 0.5
Since it is mm/8 bit, the compression effect is great for images in which the same pixel continues for 0.5 mm or more. This compression rate is A4 size 2 5mm square on a white background, line thickness 0
．． For a document with 5 mm characters, the character line will be 3 times larger and the blank line will be 16 times larger. In addition, the processing speed is 400 dpi, and the basic clock is 16M.
Under the Hz condition, it is fast at 2.5 seconds for A4 size.

【Effect of the invention】

In the image compression circuit of the first invention, one or more continuous white pixels appear alternately in serial binary image data outputted in the scanning order of the image via the 8-bit P/S conversion circuit 1. and a 2-bit shift register 2 as a pixel switching detection means for detecting switching between one or a number of consecutive black pixels. E
A 7-bit counter 3, such as an XOR circuit 5, counts and outputs the number of consecutive pixels from the previous detection to the current detection in the form of a 7-bit count value each time the pixel switching detection means detects the pixel switching. A compressed code C consisting of a count output from the 7-bit counter 3 and a pixel value representing whether the continuous pixel is white or black is output every time the pixel switching detection means detects the pixel switching. Further, in the image restoration circuit of the second invention, a data latch 11 that latches the pixel value in the compressed code C, a down counter 14 that similarly counts down the count value in the compressed code C, and the data latch 11 Since the compressed data (compressed code) C is provided with an S/P conversion circuit 12 that serially outputs pixel data having a pixel value latched to 8 while the down counter 14 is counting, the compressed data (compressed code) C is Because the bit length is fixed,
It is easy to process with a general-purpose CP[I (8, 16, 32 bit). Since this compression code C is expressed by a total of 8 bits, 1 bit representing the color of the pixel row and 7 bits representing the number of consecutive pixels, the compression/decompression process can be performed using a counter circuit without a code correspondence table. is possible. Therefore, even when compressed data is sent to a general-purpose personal computer or the like and restored, there is no need for dedicated hardware, and the process can be performed using simple software. Furthermore, the circuit can be configured with standard shift registers and counters, eliminating the need for memory or dedicated LSI. Furthermore, if this circuit is implemented as a dedicated LSI, it can be realized with about 2800 gates.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an image data compression circuit as an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a compressed code decompression circuit, and FIG. 3 is an example of an original image and its scanning. Figures 4 and 5 showing
Each figure shows the compression result of image data based on the line-by-line image scanning of FIG. 3. Fl: Original image, L (Ll, L2) Niline, C (C1l
~C13, C21~C23): Compressed code, 1:8
Bit P/S conversion circuit, 2:2 bit shift register,
3 Near-bit counter, 4: Control circuit, 5: EXOR circuit, 6: OR circuit, '7: AND gate, 11: Data latch, 12: 8-bit S/P conversion circuit, 13: 8 times counter, 14: Downtown 15: Control circuit, DB
I~DB4: Data path.

Claims (1)

[Claims] 1) One or more white continuous pixels and one or more black continuous pixels that appear alternately in serial binarized image data output in the scanning order of the image, respectively. pixel switching detection means for detecting switching between consecutive pixels; for each detection by this pixel switching detection means, the number of consecutive pixels from the previous detection to the current detection is calculated as a count value of a predetermined bit length; a counting means for outputting a count in the form of , and the pixel switching detection means detects a compressed code consisting of a count value outputted by the counting means and a pixel value representing whether the continuous pixel is white or black. An image compression circuit characterized by outputting data for each time. 2) Create a process for each continuous pixel of one or more white continuous pixels and one or more black continuous pixels that appear alternately in serial binary image data that is output in the scanning order of the image. A compressed code consisting of a count value of a predetermined bit length representing the number of consecutive pixels, and a pixel value representing whether the consecutive pixels are white or black, is extracted from the original serial number. A circuit for restoring digitized image data includes a latch means for latching pixel values in the compressed code, a counting means for down-counting a count value in the compressed code, and a circuit for latching the pixel values latched by the latch means. An image restoration circuit comprising: image data output means for serially outputting pixel data having pixel data while the counting means is counting.