JPH0548027B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an improvement in a compressed data decompression method for decompressing compressed data in a system using compressed data.

(b) Prior Art and Problems Generally, when an image such as a figure or character is converted into an electrical signal and transmitted, the image is separated into a plurality of white or black pixels by visual equipment, and white is "0", Black is converted into an electrical signal of "1". However, in an image, it is extremely rare for white and black pixels to be uniformly distributed, and usually, there are many cases in which a plurality of identical signals are continuous. If the same signal is transmitted as it is, the amount of information will be large, so a redundancy suppression coding system is adopted in which redundant parts of the signal are removed, compressed, and transmitted.

One of such redundancy suppression coding methods is
In the one-dimensional encoding system, the International Telegraph and Telephone Consultative Committee (hereinafter abbreviated as CCITT) uses a compressed code consisting of 1's and 0's for run lengths of 0 to 1728 bits for white and black. He has published a table (terminating code and make-up code) for converting the code into a fixed code.

Data compressed using such a redundancy reduction coding method is restored to the original image by being decompressed using the table specified by CCITT (hereinafter referred to as decompression table). It's getting old.

Conventionally, the circuit shown in FIG. 1 has been used to expand data using an expansion table. FIG. 1 is a diagram of a conventional decompression circuit for decompressing compressed data, and FIG. 2 is a diagram of received data, where 1 is a register, 2 is a decompression table, and 3 is a buffer register. For example, using this circuit, the received data "0" shown in FIG.
Store the address in buffer register 3. When decompressing this data, the 8-bit contents of buffer register 3 are set in register 1, and the value of data 1 is obtained from decompression table 2. Next, register 1 is shifted to the left five times, and the "1" address of buffer register 3 is shifted to the right three times, and the second
Create a form as shown in the lower part of the figure, create a logical sum of addresses "0" and "1" to complete data 2, input the logical sum value to register 1, and obtain the value of data 2 from expansion table 2. Similarly, data 3 and 4
process. Therefore, the disadvantage is that it takes time and effort to determine the address of the expansion table, and the disadvantage is that it is complicated to process the data, resulting in an increase in the number of programs that process this data. It was hot too.

(c) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention aims to provide a compressed data decompression method that does not take much time to process data and can easily complete the processing. be.

(d) Structure of the Invention The present invention includes a first shift register to which compressed received data is input in parallel from a buffer register and outputted serially; a second shift register that is input to the second shift register and output in parallel; and an expansion table that detects the lasso length of compressed received data from the parallel output of the second shift register and outputs decompressed data corresponding to this run length. The compressed data having the same number of bits as the parallel output of the shifted compressed data detected by comparing the second shift register with the expansion table is transferred from the first shift register to the second shift register. After all the data in this first shift register is serially input into this second shift register and all the bits in this first shift register are emptied, the subsequent compressed received data is It is characterized in that it is input to the first shift register in parallel.

(e) Embodiment of the Invention An embodiment of the present invention will be described in detail below with reference to FIG.

FIG. 3 is a block diagram of an embodiment of the compressed data decompression method of the present invention, in which 3 is a buffer register;
4 is a first shift register, 5 is a second shift register, and 2 is an expansion table.

The first shift register 4 is a buffer register 3.
It has a function of inputting 8-bit compressed data from It has a function of comparing the serially input data from the decompression table 2 with the decompression table 2 and outputting the detected compressed data to the decompression table 2 as parallel data.

First, the first 8-bit compressed received data (11000101) is input from the buffer register 3 in parallel to the first shift register 4, and then all of this data is input serially to the second shift register 5. Furthermore, a case in which the next 8-bit received data (00111101) is input from the buffer register 3 to the first shift register 4 in parallel will be specifically explained.

With 8-bit data stored in each of the first shift register 4 and the second shift register 5 in this manner, the 8-bit data in the second shift register 5 is compared with the expansion table 2.
In this case, since the first bit is 1, it is white at first, so the white run length column of the expansion table is the target, and the result of verification (1100) is the first data, which should be expanded to 5 white bits. is detected,
Along with being output from expansion table 2, (1100)
Since there are 4 bits, the remaining data (0101) in the first shift register 4 is shifted by 4 bits. This shift of 4 bits empties the bits, so the first (0011) in the first shift register 4 is serially input to the second shift register 5. In this second shift register 5, the first
Data (1100) is removed and the remaining (0101) and the first
The first data of the shift register (0011) is set. On the other hand, the second half (1101) of the data stored in the first shift register 4 is shifted by 4 bits, and the remaining 4 bits are empty.

In this way, the contents set in the second shift register 5 are compared with the expansion table 2.
In this case, the first bit is 0, so the black run length column of the expansion table is the target.
(010) is the second data, and it is detected that this is 1 bit black, and 1 black bit is output from the second shift register 5 to the expansion table 2, and (010) is 3 bits. Therefore, the remaining data 1 in the second shift register 5 is shifted by 3 bits, and only the last 1 is set in the position of bit 0 in the second shift register 5, and the serial output (0011110) is 1 shift register to 2nd shift register
The signal is input to the shift register 5. As a result, (10011110) is set in this second shift register. When this data is matched with the decompression table,
In terms of order, the white run length column is targeted, and the 5 bits (10011) in the data set above are the third data, which is detected to be the 8 bits of white, and the second shift (10011) is output from the register to the expansion table 2, and since (10011) is 5 bits, only the last (1) is set in the first shift register 4, so this (1) ) is set at the bit 3 position of the second shift register 5, and since the contents of the first shift register 4 are all empty in this state, the next 8-bit compressed data (10000000) of the received data is The signal is inputted in parallel to the first shift register 4 via the buffer register 3, and then the first 4 bits (1000) are outputted serially and inputted to the second shift register 5. In this state, (11011000) is set in the second shift register, and (0000) is set in bit positions 0 to 3 of the first shift register.

As before, the data (11011000) stored in the second shift register 5 is compared with the expansion table 2, and (11) is the fourth data with a 2-bit black run length. (11) is detected as 2 bits and output from the expansion table 2, and (11) is output as a 2 bit detection signal.
The same data shifting process is repeated thereafter.

That is, a first shift register 4 that serially outputs parallel inputs and a second shift register 5 that outputs serial inputs in parallel are connected,
The compressed reception data is input in parallel from the buffer register 3 to the first shift register.
The serial output from the shift register 4 is input to the second shift register, and data is set in all bit positions in the second shift register by the serial input from the first shift register. Also, the first
When all the data stored in the shift register is shifted to the second shift register and all bit positions become empty, the subsequent 8-bit compressed data is input in parallel to the bit position of this first shift register. It is becoming more and more common.

In this state, the parallel output from the second shift register is checked in the order of white run length and black run length in the expansion table 2, and the expanded data corresponding to the detection of the first data is output. Based on a detection signal indicating the number of bits in one data, data corresponding to this number of bits is serially output from the first shift register to the second shift register and set, and then the second data is detected.

If all bit positions in the first shift register become empty, new 8-bit compressed data is transferred to the first shift register.
It is input to shift register 4 in parallel, and from then on,
It becomes possible to decompress received data compressed through a similar process.

(f) Effects of the Invention As explained above in detail, the compressed data decompression method of the present invention has advantages in handling compressed data because it does not take much time to process data and the processing can be easily completed. There will be many.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional decompression circuit for decompressing compressed data, FIG. 2 is a diagram of received data, and FIG. 3 is a block diagram of an embodiment of the compressed data decompression method of the present invention. In the figure, 1 is a register, 2 is an expansion table, 3 is a buffer register, 4 is a first shift register, and 5 is a second shift register.

Claims (1)

[Scope of Claims] 1. A first shift register 4 into which the compressed reception data from the buffer register 3 is inputted in parallel and outputted serially; Detects the run length of the compressed received data from the parallel output of the second shift register 5, and outputs decompressed data corresponding to this run length. and an expansion table 2, the compressed data having the same number of bits as the parallel output of the shifted compressed data detected by comparing the second shift register 5 and the expansion table 2 is transferred to the first shift register. 4 to the second shift register 5, all the data in the first shift register 4 is serially input to the second shift register 5, and all the bits in the first shift register 4 are emptied. 2. A method for decompressing compressed data, wherein subsequent compressed received data is input in parallel to the first shift register 4.