JPS58121866A - Run length decoder - Google Patents

Abstract

PURPOSE:To attain decoding processing quickly, by generating run length decoding data in parallel by n-bit (or l-bit larger than n) and writing the data on a screen memory in parallel. CONSTITUTION:A memory 11 is written with 3-bit ''0'', 11-bit ''1'' and 10-bit ''0''. In writing, decoded data having effective data number M represented with a signal 141 is rearranged, written in the screen memory 11 at each 4-bit storage, the rest signal data are stored in a register and written in parallel by 4-bit together with the next decoding data. When one line decoding is finished and a code interpreting circuit 2 interpretes the one line end code, a one-line end signal 121 is outputted, a timing pulse generating circuit 9 outputs a start pulse 120 again and the interpretation and decoding of the next line is started.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a run-length decoding device that decodes original data from a run-length encoded data string.

Run-length encoding is used for various types of data compression, including data compression for facsimile signals. It is something.

With a normal Factor iU, it takes about 30 seconds to transmit an A4 size manuscript, so there is no problem even if decoding takes about the same amount of time (the decoding device needs to be particularly fast). However, if you store data compressed by run-length encoding in memory, decode it as necessary, and display it on a television display, the time required for decoding can be short. Fees will be charged.

Next, the MH encoded M4Jl [compressed data k
(Let's consider a specific example with the goal of decoding in 1 to 0.2 seconds.The number of pixels in one scanning line is 1728, and the number of scanning lines in one screen is approximately 2300, so the total number of pixels is about 4
It's megabits. If the data compression rate is 10,
The number of compressed data is 0.4 megabits. The process of σ encoding consists of the first step of reading compressed data from memory, decoding it, and separating it into data representing individual white or black run lengths, and decoding the data representing run lengths into black and white colors for each pixel. and a second stage of generating data. Operating clock frequency? If the frequency is 7 MHz and one data is decoded in one clock, the time required for the first stage is T.
l is 0.4//second. If one pixel of decoded data is generated in one clock, the time required for the second stage is T2.
4/! It takes seconds. For example, if the clock frequency f is 10 MHz, Tl = 0.041 seconds, T2
= 0.4 seconds, so the target () will not be reached. In order to reach the target value of 0.1 seconds, the clock frequency must be increased to 40 MHz, and a special ultra-high-speed circuit element is required. Therefore, the equipment becomes expensive.

An object of the present invention is to provide a run-length decoding device that enables high-speed decoding without using ultra-high-speed M elements.

The decoding device of the present invention includes a decoding circuit that decodes a run-length encoded data string and sequentially outputs binary data representing each run length, and the bits indicated by the output value of the decoding circuit. a run-length decoding device that decodes a number of white or black signals and sequentially stores them in a screen memory; an upper counter to which an upper value is set and is subtracted by a clock pulse; a selector that selectively outputs a fixed value or an output signal of the lower counter for each clock according to a carry signal output from the upper counter; a flip-flop or pattern generator that inverts each length;
an array conversion circuit that inputs the decoded data output from the flip-flop or pattern generator and the number of valid data output from the selector, arranges the valid decoded data in order, and outputs it as parallel data of more than one bit. Characteristic 4 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, a run-length encoded data string (hereinafter referred to as compressed data) stored in the memory 1 is read out by a read pulse 101 supplied from the code decoding circuit 2. The output signal 102 of the memory 1 is decoded by the code decoding circuit 2, and the individual run lengths are output as binary numbers. Even if the code decoding circuit 2 uses a circuit tube of the type that serially decodes bits one by one, which is conventionally used, when the pressure ratio is high, the effect on the overall decoding time is small. Therefore, in this embodiment, a known serial code decoding circuit is used (as it is currently used in the MH code decoding circuit of business facsimile machines, its explanation will be omitted).

Of the output signal 102 of the code decoding circuit 2, the lower bit outputs 110, 111? To counter 3, - upper bit output 1
12,113i is supplied to the counter 4. Counters 3 and 4 receive a load pulse 1 given from code decoding circuit 2.
14, all input values are temporarily stored. Now, for the sake of simplicity, the maximum run length is assumed to be 15, and the output signal of the code decoding circuit 2 is assumed to be 4 bits. Then, assuming that the number of parallel bits s f to be simultaneously written to the memory 11 (described later) is 4, the lower two pit outputs 110 and 111 of the above output signal are sent to the counter 3.
Then, the remaining upper two bits output 112 and 113 are stored in the counter 4. Note that the run length Nl is the decoded N
Continuous white or black decoded data 'fr% (an integer of 2 or more) pit parallel data h (an integer) times, remaining 9q (
When generating parallel data of pits (a fraction less than s), the upper digit kakunta 3 stores the digit fraction qt, and the upper counter 4 stores ' in the above.

For example, if N=11*attack=4, NI=2 and #=3, so counter 4 stores "2" and counter 3 stores "3". That is, since the output of code decoder 1 and 2 is expressed in binary as °IUII-, the lower 2 bits @11'' (2 over display) are stored in counter 3, and the upper 2 bits @101 (binary representation) are stored in counter 4. It is stored in counter 3.4.
is a synchronous type [, when a load pulse is applied, data is loaded into the counter at the rising edge of the next clock pulse.
74163, spPH74669 (part name), etc. can be used.

When the color content is @0#, the counter 4 outputs a carry signal 115 from the carry terminal CR,
When the count content is other than @O°, 1 of the carry terminal CH
The principle is 10#. In addition, count enable terminal EP
When fC"1#" is given, the child CCK is input to the clock and the count is set by the clock pulse 119 @["1"
This is a counter that decrements by increments. When the count value becomes @01 due to the above reduction 4, the carry signal 115 "1" KL,
Count enable terminal lP via inverter 5″It
t - "O" [To do Kyo subtraction [Stop. Therefore,
For example, when "2" is loaded into the counter 4, the count enable signal becomes "1" for two clock periods (generally speaking, it becomes "1" for only a clock period). - Since the count enable terminal IP of the sword counter 3 is grounded, the count is not decremented by the clock pulse. In other words, the carry signal 115 becomes "1" and the NAND
The stored value is held until it is cleared by inputting the clear terminal CLK "0" through the circuit 6. Counter 3 may be a register.

The output of the counter 3 (2 bits) and the output of the inverter 5 are manually input to the selector 7, and when the output of the inverter 5 is 111, the selector 7 sets the fixed value "100' (
In decimal notation, "42)" is fully output, and when the output of the inverter 5 is 101, the output value of the counter 3 is selectively output.

The output of the selector 7 indicates the effective number of decoded data.

The flip-flop 8 is a flip-flop that is triggered and inverted by the load pulse output from the code decoding circuit 2, and alternately outputs "1" or "θ"' (corresponding to black and white) for each load pulse. There are four outputs m of the 07 rig 70 tube 8, but at the same time they become 1" and #i "0".

That is, the decoded data corresponding to white and black elements are simultaneously output in units of 4 bits (sometimes including invalid data).

The array conversion circuit 10 arranges the 4-bit output (general KFi bit) data 140t- of the flip-flop 8 and the effective data indicated by the output signal 141 of the selector 7 in the order of occurrence, and summarizes the data into 4 bits each (generally t bits each). 0 screen memory 1 to be output in parallel (described in detail later)
1 writes the 4-bit parallel decoded data 150 output from the array conversion circuit 10 using the loading pulse 109.

Tie/gpulse Yasei circuit 9Fi, clock pulse 11
9 and a line start pulse 120 are output L, and the clock pulse 119 determines the timing of each unit's operation.The line start pulse 12G resets the flip-flop 8 and the array conversion circuit ioe, and starts the operation of the code decoding circuit 2. Then, in response to the l line end signal 121' from the code decoding circuit 2, a line start pulse 120 is output. The carry signal 115 of the counter 4 is fed back to the code decoding circuit 2, and the code decoding circuit 2 detects that the carry signal 115 is "1".
When ``'' is reached, it is known that the generation of decoded data has ended, and the next code decoding is started.

Then, when the IX)L code indicating the end of one line is decoded, a 12-in end signal 121't-timing pulse generator 9 is sent.

The array conversion circuit 10 is configured as shown in FIG. 112, for example. That is, the 4-bit decoded data (including invalid data) 140 output from the flip-flop 8
and a signal 141 (3 bits) 1-indicating the valid data number list outputted by the selector 7 and inputted to the first shifter 71 and the modulo calculation circuit 73. The shifter 71 shifts three successive terminals among the input terminals 11 to I to output terminals 0. It is an I@1 circuit connected to ~0°. The number of shifts is determined by the human power signal 141.The number of shifts is “0”
In this case, the input terminals ■, ~Is' are connected to the output terminals O3~0. and when the shift number is “1”, the input terminals I, ~I4
, when the number of shifts is "2", I, ~I, and when the number of shifts is "3", it is . ~Lt", and when the shift number is "4m, I and -Ia are output terminals 01 to 0. The output terminals O1 to 0 of the first shifter 71 are connected to is input manually to the register 74, and the output of the register 74 is input to the second chic 7.
20 input terminals (1), -Is are connected to I11 in reverse order. 't
Ta. The output of the register 74 is the input terminal of the first shifter 71! The decoded data 140 is input to the input terminals I and I of the first shifter 71. The decoded data 140 is also input to the input terminals I, .about.I of the shifter 72 in reverse order. Schick 71.72 is one of the multi-prep connectors that can connect input lines and output lines, such as Advanced Microb/(Advance
d Micro Device) A@2581
A signal 141 indicating the number of valid data layers such as 0 (IIf1 product name) can be used is used for shift control of the shifter 71, and is also input to the -1:juro arithmetic circuit 73. The modulo arithmetic circuit 73 adds the output signals 175a, 175A of the register 75 and the effective data supplementary information, and stores the remainder when dividing this by the road, that is, the number less than the island, in the register 75 using the signals 1'13h, 173C. , when the addition result is greater than the outside, carry signal 173α
Output. If 旙=4, a normal binary adder can be used.

Further, the register 75 indicates the number of remaining codes after the decoded data is output in 4-bit units.

When the gate 76 is opened by the carry signal 173α, the write pulse 109 is output and the memory 11 (FIG. 1)
sent to. The other human power Kfl clock pulse 119t of gate 76 is human power.

Further, the output value of the register 75 is sent to the second chic 72 and is used as a signal instructing the shift number of the second shifter 72.

Next, the operation of this embodiment will be explained. Now, an example will be explained in which three pixels from the beginning of one line are white, 11 primary pixels 'f:l&', and the next 10 pixels are white. Timing pulse generation times w19 to 3 in Figure 1
When a line start pulse 120 as shown in FIG. The code decoding circuit 2 decodes the enemy's first run-length code t- and outputs "0011", and also outputs "0011" as shown in Figure 113(d).
A load pulse 114 as shown by K is output. Counter 3 is loaded with “11” (Zjk number), and color/re4 is loaded.
The butterfly “00” is loaded. counter 3 and counter 4
The sum of the ren (counter 4 contents F14 times the 9th value) is the third
It is shown in decimal notation in figure (da). Now, the content of counter 4 is "0'", so the carry signal 115 is as shown in Figure 3 (11
As shown in the figure, leave it as “1′”, code decoding time lol! 1
2 immediately begins solving the next run-length code. On the other hand, due to the carry signal 115 being "1'", the output of the inverter 5 is "θ', and the content of the Ryuushikta 7 counter 3 is "
Select 11''' (binary display) and change the array lol! 110
send to Therefore, the number of valid data indicated by the signal 141 is 11L.
is "3" (decimal) as shown in Fig. 3.

Now, the output of 7 lip-flop 8 is “o, o, o, o
However, only 3 bits of these are valid as decoded data, and the last 1 bit is invalid data, as will be described later. The input terminals I4 to Iq of the chic 71 are inputted to the input terminals I4 to Iq of the Schick 71.
It is “ooox” as shown in l.

Here, x is actually h″θ″, but since it is data that will become invalid later, it will be expressed as X to distinguish it from other data. Then, the input terminals I4 to I6 are shifted by 3.
output terminals 01-0. , and “000′” is stored in the register 74. □-10,000, the modulo arithmetic circuit 73 (FIG. 2) adds the number of valid data "3'" indicated by the signal 141 and the output value "Oo" of the register 75, and stores the result "3" in the register 75 ( Figure 3 (i)
reference). Since the carry signal 173α is "01", the write pulse 109 is not output.The register 75 stores a remainder number "3".The remaining 3 bits of decoded data are sent to the input terminal I of the shifter 710 of Ml. I,,I
, to output terminal 0. ．． 0. ．． 0. The signal is outputted to the register 74 and stored in the register 74. The output of register 74 is
Input terminals of the board 71 ■, ~1. Since it is fed back to , it is held even if the shift number reaches O.

Next, counter 3 is cleared at the next clock and becomes “O”.
(Figure 3 (h)) The total value of % counters 3 and 4 is also “
0" ([! Figure 3 (g)). On the other hand, the code decoding circuit 2
decodes the second run-length code and reads “1011”
(10! 11 in display) and load pulse ll4tP
When issued, "3'" (in 1G decimal notation) is stored in counter 3 and 2'" (in decimal notation) is stored in counter 4. That is,
3+2X4=11 consecutive black decoded data are required. The total value of the contents of counter 3 and color/counter 4 is 11 in decimal notation as shown in Figure 3 (-), and 2' has been stored in counter 4 (Figure 1). ) The carry signal 115 is "θ"" It (@3 (-)),
The output signal 41 of the selector 7 is determined by the output of the inverter 5.
is a fixed value of ``100'', that is, 4 in decimal notation (see Figure 3 (A)). Now, the flip 70 knob 8 is inverted by the load pulse 114 and outputs ``1111''. , IXZ
As shown in FIG. 3 (Z), "1111" is input to the input terminals I4 to I4 of the first lid 710 in the figure.

In addition, "000" is manually input from the output of the register 74 to the input terminal Che, ~Ij (see Fig. 3 (A)) o On the other hand, I, ~, of the shifter 72 of $1!2 is 000. ' and evening, I4-11 was "1111" and 1 hbo. Figure 3 (Z
)t;i, input terminal I of the shifter 72, ~I,
It also shows the logical state of

On the other hand, the modulo calculation circuit 73 calculates the value ' of the input signal 141.
ioo'" (binary display) and the output value of register 75 "11
"" (indicated by 2M) is added modulo, "11" gate 76 is opened, and a write pulse 109 is sent to the memory 11. In this case, since the output value of the register 75 is 3, the second shifter 72 connects the input terminals I, to 14 to the output terminals 04 to O0.

From the output terminals 04 to O1, a portion "000!" surrounded by a bold line in FIG. 3(4) is output. That is, the previous remainder 3
A total of 4 bits, including the bit and the current high-order bit, are output. The memory 11 writes the output signals 150 of the seven lids 72 in four bits in parallel by the write pulse 109.

This time's remaining 3 pins) #i, the input terminal of the first chic 71! , ~I, the number of shifts 4 indicated by the input signal 141
By L output terminal O3~0. The signal is output to the register 74 and stored in the register 74.

At the next clock, the input terminals I4-l of the first chic 71,
“1111” is input manually, and 11-1. Since the output "111'" of the register 74 is inputted to the register 74, all seven bits at the input terminals 1-I, li$3 of the first gate 71 become "1" as shown in FIG. Similarly, the modulo addition circuit 73 adds the value 4 indicated by the human input signal 141 and the output 3 of the register 75, sets the remainder 3 in the register 75, outputs a carry signal 173g, and a write pulse 109 is output. At this time, the output of register 75 is 3, so
The shifter 72 connects the input terminals ■, ~I4 to the output terminals 04~0.
*The output terminals 04 to 01 output 4 bits in parallel.
1" is output.

The memory 11 thereby writes "1'" in p4 bits in parallel. The input terminal I of the first shifter 71 was manually input! 111'' of 13 bits is connected to 0.~0. by the value 4 indicated by the human input signal 141, and the register 74
Saved in

Meanwhile, during this period, the counter 4 is decrementing the count by the clock pulse, and when it counts two clock pulses, it becomes "θ"', and outputs a carry signal 115t- as shown in FIG. The output is set to "0", the decrementing is stopped, and the selector 7 selectively outputs the output value "3" (10j! display) of the counter 3. In other words, the number of valid data indicated by the signal 141 at the next clock is "3", and the logic of terminals ■4 to I of the first shifter 71 in Figure 1'2 becomes "111×".The above "×" is actually "1", but it will be invalidated later. Express it as × because it becomes.

In addition, the output value “1” of the register 74 is applied to the terminals l, ~I.
11" is being input, at this time the first shifter 71
The logic of the terminals 11 to I of the shifter 72 is "IIIIIIIX" as shown in FIG. outputs a carry signal 173α by adding the number of valid data “3” indicated by the signal 141 and the output value “3” of the register 75, and outputs a write pulse 109t-.At this time, the output value of the register 75 “ 34, the second 7 lid 72 connects the terminals t~N4 to the terminals 04~01, so the output signal 150F1.4 bit parallel 1
Then, the modulo addition value "2"' of the modulo arithmetic circuit 73 is set in the register 75 (see number (number) in FIG. 3).

On the other hand, due to the value "3" of the input signal 141, the first shifter 71 connects the input terminals I4 to Ist output terminals 01 to 0. and sets "111" in the register 74.

The code decoding circuit 2 decodes the next run length code, and by the load pulse 114, 4[U, color/73K"2'
'' (indicated in decimal decimal) ?r is set in power input 74.

That is, the total value is 2X4+2=40. Selector 7
outputs a fixed pattern "4" for two clock pulses, and outputs "2m" for the third clock (see Figure 3 (A)).
. Now the flip 70 knob 8 is again the load pulse 114
It is inverted and outputs "oooo". Therefore, the input terminal I4 of the first shifter 71 in FIG.
000" is input, and "111" is input to input terminals 11~■,
' is done manually. That is, the logic of terminals ①, .about.I is K"110000"' as shown in FIG. 3(t). Therefore, terminal 1 of shifter 72. The same logic applies to ~I. Modulo jJ1gl path 73 is input signal 141
The number of valid data indicated by “4” and the output value of register 75 “2”
``'' is added and a carry signal 173α is output, and a write pulse 109 is sent from the gate 76 to the memory 11. At this time, the output value of the second thick 7Sl register 75 is
2m by input end check, ~■, output terminal 04~O1
3, the signal "1100'" written in bold line in FIG. On the other hand, the first chic 71Fi,
By the value "4"' of the input signal 14.1, the input terminal ■,
~Ivt-4i to output terminal 0-~03! 1000'' is stored in the register 74.

At the next clock, "oooo" is input to the terminals 4 to 1 of the first 77 terminal 71, and the register 7
4 to "000"' is input. Therefore, the terminals ■6 to ■ of the second shifter 72 are "oooo", and 4 bits are output in parallel from the output terminals 0 to 0 according to the output value "2" of the register 75. B operation Igl path 7
3fi input signal 141 value “4” and register 75 image”
2"' is added and a carry signal 173al is output. A write pulse 109 is output from the gate 76, and the screen memory 11 writes all 4 bits of the output signal 150 of the shifter 72 in parallel. That is, "oooo" is written. For.

Here, the content of counter 4 becomes "0'" and carry 11
5 becomes "1'" (Figure 113 (#)), and inverter 5
The output of is “θ′” (Figure 3 (7)), and selector 7
selectively outputs the output of counter 3. That is, signal 1
The value of 41 is "2" (Figure 3 (L)). Therefore, the modulo arithmetic circuit 73 in FIG. is output. At this time, the output value of the register 75 is "2m," and the shifter 72 has input terminals 1. to I, t.
- Connected to output terminals 04-01. Second 7 Lid 7
2 input terminals I6 to I receive “00” from the register 74.
' is input, and since the output signal 14 of the flip-flop 8 is input to the input terminals 4 to I, the output signal 15G of the shifter 72 is a 4-bit parallel output signal 15G.
oooo”.

The signal is written into the screen memory 1. The calculation result of the modulo calculation circuit 73 is 2+2=0, and "0''' is set in the register 75 (W, FIG. 3 (1)).

With the above operation, the memory IK is set to 3 bits “0”.
'', 11 bits of ``1'', and 10 bits of ``θ''' are written.The above write is performed by rearranging the decoded data of the effective data supplement indicated by the signal 141. Screen memory IKI for every 4 bits accumulated
The remaining decoded data is stored in the register 74, and is written in parallel in 4-bit units together with the next decoded data. Then, when the decoding of one line is completed and the code decoding circuit 2 decodes the one line end code EOT, the third
The timing pulse generation circuit 9 outputs the 1-line end signal 121 as shown in the figure (Al), and the timing pulse generation circuit 9 again outputs the start pulse 1.
20t-output to begin interpretation and decoding of the next line.

The above-mentioned embodiment tifi"4 is explained, but even if sFi is an arbitrary integer, it can be implemented with a similar configuration.

According to the invention, in the second stage of decoding, the generation of N bits of decoded data takes place in *+itm, ie A+1 clock time. If the average run length is 50, &=8, h will be 6 on average, so it can be decoded in 7 clock times. In other words, decoded data can be generated at a rate of approximately 7 bits per l clock time. Therefore, if the clock frequency is 10 MHz, the time T of the second stage is 0.06 seconds, and when added to the time TI of the first stage, it is possible to decode one screen in 0.1 seconds. It is.

The arrangement conversion circuit shown in FIG. 2 described above is an example in which the arrangement is changed from 4-bit (including invalid data) parallel human input data 140 to 4-bit parallel output data 150 excluding invalid data. However, it is also possible to remove invalid data from input data calculation bits (including invalid data), convert the array to fr-L bit parallel output data, and output it.
It is Noh. In this case, the first shifter 71 has the number of input terminals (ru+t-1) bits, the maximum number of shifts n, and the number of output terminals (
The second thick 72 uses a chic with an input terminal number of 2L-1 bits, a maximum shift number (L-1), and an output terminal number of t bits. And the register 74 for storing the remainder bits.

It is sufficient to use a (L, -1) bit register and add an accumulator for counting the remainder bits and a modulo l arithmetic circuit. However, in order to prevent excess bits from accumulating and overflowing, it is desirable that L≧L. for example,
L=8. a=8. If the encoding speed is 10 megahertz, decoding of 80 megabits/second can be achieved.
This is extremely advantageous for high-speed processing.

Furthermore, in the above embodiment, the decoded data 140 input to the array conversion circuit 10 is 4-bit parallel data of "θ" or "1" that is alternately inverted for each run by the flip 70 tube. N decoded data is (N-1)
When the output 141 of the selector 7 is composed of 1 "0" and 1 "1" (the conversion point is "1"), a pattern generator is used in place of the flip 70. It may be configured to receive the information and generate a corresponding pattern. For example, when the signal 141 is "4'," it is "0001," when the signal 141 is "3", it is "001," and when the signal 141 is "2'", it is "01". When it is "1", it is a pattern generator that generates all "1"s.

In the above-mentioned embodiment, when the compression rate of the run-length code is low, it is possible to achieve a sufficiently long decoding time as described above, but when the compression rate is low.

It is necessary to devise ways to shorten the processing time of the code continuation circuit 2. For that rounding, the sign solution w11. The circuit 2 may have a parallel input configuration as described below.

Figure 4 shows the code solution l! FIG. 2 is a block diagram illustrating an example of a parallel code decoding circuit that can execute the code at high speed.

In this case, the output signal 102Fi of the memory 1 is, for example, 4-bit parallel data. Then, the output signal 102t
j register 21 and shifter 22 end checks, ~■, are input. The output of the register 21 is the terminal ■ of the shifter 22,
~, and the shifter 22 is input to the register 28 described later
The number of shifts is controlled by the output of . Output terminals 04 to 0 of shifter 22. t-ROM23C) address terminal A,
The output signal of the register 24 is supplied to ~A4, which is connected to the address terminal of the OM 23. register 2
Load pulse 1 output from ROM 23 is input to input 4.
14 through gate 25 controlled by 几0M2
A 2-pin length output signal of 110 to 113'ft is inputted.

Further, the output of the gate 31 which manually generates the load pulse 114 and the carry signal 115 is reduced by the timing 11 by the register 30, and the gate 26 is controlled by the output of the register 30. The gate 26 is closed at the next clock after the load pulse is output, and the code decoding is temporarily interrupted in order to force code length data I, which will be described later, to zero. ROM
The code length data I output from 23 is input to the arithmetic circuit 27 through the gate 26, and the arithmetic circuit 27t calculates the input and the output of the register 28, and stores the result in the register 28. The output value of the register 28 is used to control the number of shifts of the shifter 22 in the next clock. When the number of shifts output from the register 28 is fd, the arithmetic circuit 27
calculates d-s', and when d-d>o, output line 1
32, outputs y1=d -d, and outputs 'I' to the output line 133.
Output t="0'".

When ml-a'<0, set l, = d-s'-)-4.

Let h=“1”. y, step 1, step 9, and gate 29 output a threading pulse 101. As shown in FIG. 7, the ROM 23 stores the address position K indicated by the address terminals 4 to 4, the decoded run length, the necessity of outputting the load pulse,
A code length I and a 1-line end signal indicating whether it is a 1-line end code are stored in advance. The above code length S
' represents the code length of the nine decoded parts of the code length of the compressed data code.

Next, the operation of decoding the code will be explained. As a premise,
It is assumed that the code darkness of the compression code for run lengths 1 to 15 is defined as shown in FIG. In the figure, the code length of each code word is shown in the right column. Furthermore, the 1-line end code EOL Fi is "00000001"', and the code length is 8.

Now, assuming that compressed codes with run lengths 3, 11, and 10 are stored in memory 1, from FIG. 5, the compressed codes are "10', "0000101" and
ioo"", followed by a line end code "0000"
When the compressed code string is read in parallel 4 bits at a time from the 0 memory 1 to which 0001" is added, the first successive signal 10211"1000" is obtained.

The next one is "0010"', the next one is "1000", and the next one is "0100". The end code for one line, kOL, is
The 0 twin start pulse 120, which is output separately as "oooo" and "0001"", is sent to the registers 24 and 28.
is applied, the outputs of these registers become zero, and the decoding circuit starts the decoding operation.

First, the first 4-bit parallel data "1000" output from the memory 1 is sent to the shifter 2 as shown in FIG. 6(A)K.
2 input terminal check, manually input to ~1m. Therefore, jitter 2
1000" is output to the outputs O4 to 01 of 2, and the ROM
23 address terminals, ~^. Now, in 030M23, which is A4Fi zero to the address terminal, a table as shown in Figure 7, for example, is written in correspondence with the length code word shown in Figure 5. Therefore, ROM
The run length ``3'''', the code length I is ``V'', and the load pulse ``θ'''' are read from the corresponding address position of 23.The run length ``3'''' is read out from the counters 2 and 3 ( @Figure 1) is output to the load pulse ``O
' is stored in counters 2 and 3. Since 25Fi is closed by the load pulse "θ", the register 24 has a zero code length d up to "1" of "θ'".
It passes through the gate 26 and is sent to the arithmetic circuit 27 for calculation llT.
hm27U output line 132Ky, ==+/-s'+4=2
1 is output, and the output line 133Kfft=" is output. Therefore, the register 28K"2'" is set and the gate 29 is opened, and the read pulse 101 as shown in FIG. 3 (1) is output to the memory 1. ◎ The next 4 bits of parallel data read from memory 1''
0010" is the shifter 22 as shown in FIG.
At this time, register 21 is input manually to terminals ■4 to ■1.
stores "000" for the first three bits of the previous manual input data, and inputs input to terminals I, ~I, of the shifter 22 (Fig. 6 (bl)). On the other hand, the output of the register 28 Since the number of shifts m' is 2", the shifter 22 connects the terminals 16 to I3 to the terminals 04 to 01. Therefore, from the terminal 04!-0 of the shifter 22, the terminals 04!-0, The enclosed 4 bits '0000'' are output.i(,0
Since the output "0000"' of the register 24 is input to the address terminals ^ to A4 of M23, the run length "2" is output to the output signals 110 to 113 according to FIG.
A code length of "4"" is output to the output signal line 131. However, since the decoding of the compression code has not been completed yet,
- pulse 114 is not output (logic is "1"). That is, the run length output when the load pulse 114 is not output is in the middle of code decoding, and the run length "2" at this point is stored in the register 24 through the gate 25, and is stored in the address of the ROM 23 at the next clock. It is fed back to A4. In the primary clock, "1000" is input to 4 to 11 of the shifter 22, and the output of the register 21 is "010" (FIG. 6(b)).
Since the output of the register 28 is "2", the output terminal 04
~ From the OI, the part “10” surrounded by a thick line in Fig. 6<b>
10" is output and input to the ROM 23, ~A. At this time, the output "2'" of the register 24, that is, "0
010" (2 way display) is address terminal A of 90M23
, is supplied with ~. Accordingly, the ROM 23 outputs the run length "11'" (in decimal notation), the load pulse "0", and the code length "3" according to FIG. In other words, output signals 110 to 103 have 11 (in decimal notation)
is output and stored in the counter 3 and number by the load pulse 114. Similarly, when the next run length of 10 (decimal) is decoded and the WOL code is finally found, the decoding of one line ends.

The code decoding circuit described above operates at high speed because up to 4 bits of compressed codes are decoded at a time. It goes without saying that the number of parallel manual data to be decoded at one time is not limited to 4 bits and can be arbitrarily selected. Furthermore, it is also possible to perform parallel operations at the same time instead of decoding the code and generating decoded data at different times, making it possible to perform higher-speed processing.

As described above, in the present invention, the run-length decoded data is generated in parallel in units of l bits (and in units of L bits larger than Fin) and written in parallel to the screen memory, so that the decoding process is performed. It has the effect of being done quickly. Also, the code Ps! for decoding compressed data! 15
! By employing a parallel code decoding circuit in the circuit, even higher speeds can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the array conversion circuit 10 of the above embodiment, and FIG. 3 is a block diagram for explaining the operation of the above embodiment. A time chart showing the signals and contents of each part, l! Figure 4 is a block diagram showing an example of a parallel code decoding circuit that performs code decoding at both speeds, wJs diagram is a diagram showing an example of a run-length code, and Figure 6 is a code of the parallel code decoding circuit shown in Figure 4. Figure 7 is a diagram to explain the decoding operation! FIG. 1 is a diagram illustrating the storage contents of a ROM 23 of the parallel code decoding circuit shown in FIGS. In the figure, 1...memory, 2...code decoding circuit,
3.4... Counter, 5... Inverter, 6...
Gate, 7... Selector, 8... Flip 70 tube, 9... Timing pulse generator, lO... Array conversion circuit, 11... Memory, 21.24.28.30.
74.75... register, 22, 71.72... register, 23... it (JM, 25.26.2
9. 31... Gate, 27... Arithmetic circuit, 73.
...Moziero calculation circuit. Agent Patent Attorney Sumi 1) Toshi Sou Figure 5 Figure 6

Claims (1)

[Claims] Two-way data tI that decodes a run-length encoded data string to represent each run length. In a run-length decoding device i that decodes and sequentially stores it in a screen memory, a lower counter or register is set with a fraction less than zero (an integer of 2 or more) of the output value of the code decoding circuit, and a clock is set with an upper value. an upper counter that is subtracted by a pulse, a selector that selectively outputs a fixed @s for each tarok or an output signal of the lower counter according to a carry signal output from the upper counter, and 7 that is inverted for each run length. The decoded data output from the flip-flop or pattern generator and the number of valid data output from the selector are input to a lip 7a or a pattern generator, and the valid decoded data are arranged in order as parallel data of n pits or more. A run-length decoding device comprising: an array conversion circuit that outputs an array.