JPS54159140A - Error correction circuit - Google Patents

Abstract

PURPOSE: To establish the error correction circuit high in flexibility, by inputting the information data, and constituting the circuit with the generation circuit outputting error correction code or syndrome, syndrome decode circuit, two control circuits, and two inversion circuits.

CONSTITUTION: The generation circuit 25 inputs the input information data 23 when the control signal 24 at the terminal 24 is, for example, in write-in state, and outputs the error correction code, and when the signal 24 is in readout state, the syndrome is outputted by inputting the information data and the error correction code. The syndrome decode circuit 29 inputs the syndrome 27 and the byte position designation data 28, outputs the correction position designation data 30 based on the data 28 and the correction position designation data 31 regardless of the data 28 and inputs them to the control circuits 33 and 34 respectively. The circuits 33 and 34 output the correction position designation date 35 and 36 equal to 0, data 30 or data 31 with the state of the control signals 32 and 24. The inversion circuits 37 and 38 correct and output the input information data 23 and the code 26 based on the data 35 and 36, if there is any error.

COPYRIGHT: (C)1979,JPO&Japio