JPS5858699B2 - error correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction circuit that generates error correction codes and syndromes, and particularly to a circuit that simultaneously generates error correction codes and syndromes for a portion of input data.

An example of the configuration of a conventional error correction circuit is shown in FIG.

This configuration example is designed to generate error correction codes and syndromes in the same circuit, thereby reducing the amount of hardware and the number of input/output terminals.

In FIG. 1, 1 is an input terminal to which input information data or input information data and an error correction code are input.

2 is an input terminal, and a control signal is input manually.

3 is a generation circuit which inputs data and control signals from input terminals 1 and 2 and outputs data 4;

Data 4 is an error correction code when the control signal at terminal 2 is in the first state, and is a syndrome when it is in the second state.

A syndrome decoding circuit 5 decodes the syndrome generated by the generation circuit 3 and outputs correction position designation data 6 of input information data to be corrected.

Reference numeral 7 denotes an inverting circuit which inputs the input information data from the terminal 1 and correction position designation data 6, corrects any errors, and outputs the input information data from the output terminal 8.

This conventional circuit has the following problems when performing partial writing.

Partial writing is an operation in which all input information data constituting one word is partially rewritten in units of bytes.

Specifically, before a write operation, all information is read out, any errors are corrected, the information to be partially written is inserted into the corrected information, and an error correction code is used as input information to be newly written. generate.

The conventional circuit shown in FIG. 1 does not have a built-in partial write function, so when used for partial write, the generating circuit 3 is used to generate a syndrome and then used again to generate an error correction code. The processing time in this error correction circuit is ((delay time of generating circuit 3)X2+(delay time of syndrome decoding circuit 5)+(delay time of inverting circuit 9)).

Normally, each logic stage is 5 to 6 stages for the generation circuit 3, 2 stages for the syndrome decoding circuit 5, and 1 stage for the inverting circuit 7. Since the generation circuit 3, which has a large number of stages, is used twice, the processing time is short. This has the disadvantage that it has a large influence on the machine cycle of the information processing device.

On the other hand, there has conventionally been a configuration in which a circuit for generating a syndrome and a circuit for generating an error correction code are separated, and correction of input information data and generation of an error correction code are processed in parallel.

An example of its configuration is shown in FIG.

9 is first input information data, 10 is first control signal, 1
1 is second input information data, and 12 is byte position designation data that designates a position to partially write at the time of partial writing.

13 is a selection circuit (SEL), and data 9°11
．． 12 and control signal 10 as inputs, and when the first control signal 10 is in the first state, the byte position designation data 12
A part of the first input information data 9 is inserted into the second input information data 11 based on the second input information data 11, and when the first control signal 10 is in the second state, the second input is inserted regardless of the byte position specification data 12. All of the information data 11 is selected and output data 14 is output.

Reference numeral 15 denotes a first generating circuit which receives the output data 14 and outputs an error correction code 17.

16 is a second generation circuit which inputs the second input information data 11 and outputs the syndrome.

18 is a syndrome decoding circuit which inputs the syndrome and byte position designation data 12 from the circuit 16 and decodes first correction position designation data 19 of the input information data to be corrected and second correction of the error correction code to be corrected. Position designation data 20 is output.

At this time, in the first correction position designation data 19, a portion corresponding to a byte position that is not designated based on the byte position designation data 12 is logically set to tl OI+.

21 is an inverting circuit, which corrects the input information data 14 and the error correction code 17 if there is a correction based on the first and second correction position designation data 19 and 20, and outputs the output data 22.
Output.

This conventional error correction circuit can generate error correction codes and syndromes in parallel by the first and second generation circuits 15 and 16 during partial writing.

Therefore, the processing time in this error correction circuit 15 is ((
(delay time of second generation circuit 16)+(delay time of syndrome decoding circuit 18)+(delay time of inversion circuit 21)), and partial writing can be performed faster than in the case of FIG.

However, when this circuit is applied to a device that does not require partial writing or a device that does not require high-speed partial writing processing, the amount of hardware and the number of input/output terminals will increase compared to the one in Figure 1. However, there were problems with economy and reliability.

Particularly when large-scale integrated circuits (hereinafter referred to as LSIs) are implemented, there is a drawback that the number of input/output terminals increases.

In addition, when this type of circuit is divided into several functions to reduce the number of input/output terminals and realized using several LSIs, it is possible to
The problem was that it lacked versatility.

In order to solve these drawbacks, the present invention generates error correction codes and syndromes in the same circuit.

Furthermore, the syndrome decoding results for input information data are output when syndromes are generated or when partial writing is performed,
The syndrome decoding result for the error correction code is output only during partial writing, and the configuration can be configured depending on whether high-speed partial writing is required or low speed is sufficient, and the number of input/output terminals is small. , provides an error correction circuit.

The drawings will be explained in detail below.

FIG. 3 shows an example of the configuration of an error correction circuit according to the present invention.

Reference numeral 23 denotes an input terminal, into which input information data or input information data and an error correction code are input.

24 is an input terminal into which the first control signal is input.

25 is a generation circuit which inputs data from the input terminal 23 and generates code 2 which is an error correction code or syndrome.
Outputs 6.

Reference numeral 27 denotes an input terminal, into which a syndrome generated in the same logic block or another logic block is input.

28 is an input terminal, which inputs byte position designation data that specifies the position where a part of other input information data is inserted into the input information data during partial writing. 629 is a syndrome decoding circuit, which inputs the syndrome and byte position designation data. It inputs data and outputs first correction position designation data 30 of input information data and second correction position designation data 31 of error correction code.

32 is an input terminal into which a second control signal specifying partial writing is input.

33 is a first control circuit, which receives first correction position designation data 30, a first control signal from terminal 24, and terminal 32.
The third correction position designation data 35 is output by inputting the second control signal from the controller.

34 is a second control circuit which inputs the second correction position designation data 31 and the second control signal from the terminal 32 and outputs fourth correction position designation data 36.

37 is a first inverting circuit which inputs the input information data from the terminal 23 and the third correction position designation data 35, inverts and corrects the input information data if there is an error, and outputs the output information data to the output terminal 39. Output.

38 is a second inversion circuit which inputs the code 26 and the fourth correction position designation data 36, inverts and corrects the code 26 if there is an error, and outputs it to an output terminal 40.

41 is an error correction circuit including the above-mentioned components in the same block.

Next, the operation of this error correction circuit will be explained.

The generation circuit 25 inputs input information data from the terminal 23 and outputs an error correction code when the first control signal at the terminal 24 is in a first state, for example, a state indicating writing. In state 2, for example, in a state indicating reading, input information data and an error correction code are inputted from the terminal 23, and a syndrome is output.

The syndrome decoding circuit 29 inputs the syndrome from the input terminal 27 and the byte position designation data from the terminal 28, and outputs the syndrome decoding result corresponding to the designated byte position based on the byte position designation data, and also outputs the syndrome decoding result corresponding to the designated byte position based on the byte position designation data. The syndrome decoding result corresponding to the byte position of is logically set as °゛O'' and the first correction position designation data 30 is output.

Further, the second correction position designation data 31 is output regardless of the byte position designation data at the terminal 28.

The first control circuit 33 is configured such that the second control signal at the terminal 32 is
In this state, if the first control signal of the terminal 24 is in the first state, for example, a state indicating writing, the third correction position designation data 35 which is logically OP is output, and the first If the control signal is in the second state, for example, a state indicating reading, third correction position designation data 35 equal to first correction position designation data 30 is output.

Furthermore, when the second control signal at the terminal 32 is in the second state, the first control circuit 33 outputs a third signal equal to the first correction position designation data 30 regardless of the state of the first control signal at the terminal 24.
The correction position designation data 35 is output.

The second control circuit 34 is configured such that the second control signal at the terminal 32 is the first control signal.
If it is in the state, it will logically output "0 +t", and if it is in the second state, it will output the fourth correction position designation data 31, which is equal to the second correction position designation data.
The correction position designation data 36 is output.

The first inversion circuit 37 corrects the input information data from the terminal 23 if there is an error based on the third correction position designation data 35 and outputs the corrected data.

20th) The inversion circuit 38 receives the fourth correction position designation data 36
Based on this, if there is an error, the code 26 is corrected and output.

Next, using this error correction circuit, an example of the configuration and operation of the error correction circuit in an apparatus that does not require partial writing or high-speed partial writing processing will be described.

An example of its configuration is shown in FIG. 4, in which parts corresponding to those in FIG. 3 are given the same reference numerals.

Byte position designation data specifying the positions of all bytes is input to the input terminal 28.

At this time, the syndrome decoding circuit 29 in the circuit 41 outputs correction position designation data for all input information data.

A second control signal is input to the input terminal 32 as the first state to inhibit partial writing.

That is, ``the fourth correction position designation data 36 is logically set as f+OI+, and the correction of code 26 is prohibited.

The output terminal 40 is connected to the input terminal 27, and the syndrome decoding circuit 29 receives the syndrome generated by the circuit 25 in the same block through the terminal 40.

42 is input information data, and 43 is input information data including an error correction code.

The first control signal at the input terminal 24 is also input to the selection circuit 44 .

The selection path 44 selects the input information data 42 from the second control signal when the first control signal at the terminal 24 is in the first state (write state).
In the state (reading state), the input information data 43 is selected and input to the input terminal 23.

When the first control signal at terminal 24 is in the first state, circuit 41
The first inverting circuit 37 in the circuit outputs output information data equal to the input information data 42 to the terminal 39, and the second inverting circuit 38 in the circuit 41 outputs an error correction code for the output information at the terminal 39 to the terminal 40. do.

The first control signal of the terminal 24 is in the second state (read state)
If there is an error, the corrected input information data 43 (excluding error correction code) is output from the first inversion circuit 37 in the circuit 41, and the syndrome is output from the second inversion circuit 38. .

Note that in order to perform partial writing, the first state and the second state must be
This can be achieved by processing the states in series.

Next, FIG. 5 shows an example in which the error correction circuit shown in FIG. 3 is used to configure an error correction circuit in a device that requires high-speed partial writing.

In this example, there are two error correction circuits 41a shown in FIG.
41b is used.

Portions of these error correction circuits 41a and 41b that correspond to those in FIG. 3 are shown with the same numbers and suffixes a and b, respectively.

The input terminal 28a of the circuit 41a is manually inputted with byte position specification data that specifies the positions of all bytes, and the input terminal 2
The first control signal in the second state (read state) is input to 4a, and the output terminal 40a is connected to the input terminal 27a.

A second control signal in the first state is input to the input terminal 32a.

That is, in the error correction circuit 41a, the generation circuit 25a generates and outputs only the syndrome, the syndrome decode circuit 29a manually generates the syndrome and outputs the correction position designation data 30, and the first control circuit 33a generates the first correction Third corrected position designation data 3 equal to position designation data 30
Outputs 5.

In the error correction circuit 41b, the input terminal 27b is connected to the output terminal 40a of the error correction circuit 41a.

Therefore, the syndrome decoding circuit 29b of the circuit 41b receives the syndrome generated by the generation circuit 25a of the circuit 41a and outputs correction position designation data.

46 is input information data including an error correction code, and is input to the input terminal 23a.

47 is input information data that does not include an error correction code.

The selection circuit 48 selects the first control signal at the terminal 24b and the terminal 2
Input information data 46 or 47 is selected and outputted based on the byte position designation data of 8b, and input terminal 23b
Enter.

When the first control signal at terminal 24b is in the first state and the second control signal at terminal 32b is in the first state, circuit 4I
Output information data equal to the input information data 47 is output from the first inverting circuit 37b in b, and the second inverting circuit 38b
The error correction code generated by the generation circuit 25b is output from the error correction code.

Further, if the second control signal is in the second state, the circuit 4Ib
The syndrome decode circuit 29b in the generator circuit 25a
The first inversion circuit 37b inputs and decodes the syndrome generated in If there is an error in the error correction code of the input information data 46, the inversion circuit 38b corrects and outputs the error correction code generated by the generation circuit 25b.

When the first control signal is in the second state, the first inverting circuit 37
A corrects any errors and outputs the input information data 46 (excluding the error correction code), and the second inversion circuit 38b outputs the syndrome.

As explained above, the error correction circuit according to the present invention is
The syndrome and the error correction code are generated by the same generation circuit, and the first. By providing a second control circuit and having a configuration in which correction position designation data for input information data is output at the time of partial write or syndrome generation, and correction position designation data for the error correction code is output only at the time of partial write, partial write can be performed. For devices that do not require a high-speed partial write or do not require high-speed partial writing, it is sufficient to use only one circuit shown in FIG. 3, as explained in connection with FIG. It is possible to realize an accurate error correction circuit.

On the other hand, in a device that requires high-speed partial writing, by providing two error correction circuits shown in FIG. 3 as explained in connection with FIG. circuit delay time) + (syndrome decoding circuit delay time) + (inverting circuit delay time)
×2), and high-speed processing can be performed by parallel processing.

Therefore, the error correction circuit of the present invention has the advantage of being highly flexible and repeatable since it can be configured in accordance with the performance of partial writing.

Furthermore, when converted into an LSI, there is an advantage that a versatile LSI with a small number of input/output terminals can be realized.

[Brief explanation of drawings]

1 and 2 are block diagrams showing a configuration example of a conventional error correction circuit, FIG. 3 is a block diagram showing a configuration example of an error correction circuit according to the present invention, and FIGS. 4 and 5 respectively. 4 is a block diagram showing an embodiment using the configuration example of FIG. 3. FIG. 1: Input terminal, 2: Input terminal, 3: Generation circuit, 4: Error correction code/syndrome, 5: Syndrome decoding circuit, 6: Correction position specification data, 7: Inversion circuit, 8: Output terminal, 9: First input information data, 10: first control signal, 11: second input information data, 12: byte position designation data, 13: selection circuit, 14: output data, 15:
1st generation circuit, 16: 2nd generation circuit, 17: Error correction code, 18: syndrome decoding circuit, 19: 1st
correction position designation data, 20: second correction position designation data, 21: inversion circuit, 22: output data, 23: input terminal, 24: input terminal, 25: generation circuit, 26: code, 2
γ: input terminal, 28 two-person terminal, 29: syndrome decoding circuit, 30: first correction position designation data, 31:
2nd correction position specification data, 32: input terminal, 33: first control circuit, 34: second control circuit, 35: third correction position specification data, 36: fourth correction position specification data,
37: first inversion circuit, 38: second inversion circuit, 39:
Output terminal, 40: Output terminal, 41: Error correction circuit, 42
: input information data, 43: input information data, 44: selection circuit, 46: input information data, 47: input information data,
48: Selection circuit.

Claims (1)

[Claims] 1 Inputs human power information data or input information data and an error correction code, is controlled by a first control signal, outputs an error correction code when the first control signal is in the first state, and outputs the error correction code in the second state. A generation circuit that outputs a syndrome when the condition is present, and a syndrome decoder that receives byte position designation data that specifies a position in the input information data and the syndrome, and that corresponds to the specified byte position based on the byte position designation data. The syndrome decoding result corresponding to the result and other byte positions is logically output as the first correction position designation data, and the syndrome decoding result is output as the second correction position designation data regardless of the above byte position designation signal. a syndrome decoding circuit that outputs the first correction position designation data, the first control signal and the second control signal, and when the second control signal is in the first state, the first control signal; If is in the first state, it is logically 0pa, if the first control signal is in the second state, it is the first correction position designation data, and when the second control signal is in the second state, it is the first corrected position designation data. a first control circuit that outputs the first correction position designation data as third correction position designation data regardless of the state of the first control signal; and the second correction position designation data and the second control circuit. signal as input, and if the second control signal is in the first state, it is logically 0.
a second control circuit that outputs second correction position designation data as fourth correction position designation data if it is in the second state; and the input information data and the third correction position designation data. a first inverting circuit that corrects the input information data and outputs output information data if there is an error in the input information; and a first inversion circuit that corrects the input information data and outputs output information data if there is an error; and a second inversion circuit that corrects and outputs the output data.