JPH05157815A - Address generator - Google Patents

Abstract

PURPOSE:To generate an algorithmic address serially and on the real time basis by providing an address generating circuit, a shift register, and a selector, and simply realizing control of the load and the shift of the shift register. CONSTITUTION:An address generating circuit 2 consists of a register 2A, a computing element 2B to receive the output of the register 2A as the first input, a register 2C to receive the output of the computing element 2B as an input, and to make the output as the second input of the computing element 2B, and an address control circuit 2D to output the control signal 21, the load signal 22 and the shift signal 23. A shift register 3 receives the output of the register 2C, and makes an output by the load signal 22 and the shift signal 23. The gate 4 receives the load signal 22 and the shift signal 23, and executes OR. A selector 5 makes the output of the shift register 3 as the first input, receives the lowest bit among the outputs of the register 2C, and selects the output by the input of the gate 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generator that serially generates an algorithmic pattern address when measuring a memory having a scan path structure.

[0002]

2. Description of the Related Art The structure of a random pattern generator and an address generator according to the prior art will be described with reference to FIG.
In FIG. 4, 1 is a CPU, 6 is a random pattern generator, 7 is an address generator, and 10 is a bus. The random pattern generator 6 includes a pattern control circuit 6A and a pattern memory 6B.
Composed of. A sequence program for an integrated circuit test is written in the CPU 1, and the random pattern generator 6 writes random pattern data from the pattern control circuit 6A to the pattern memory 6B according to an instruction from the CPU 1 when the integrated circuit test is executed. The address generator 7 generates a memory address during a memory test, and the random pattern generator 6 generates a random pattern when testing a random logic IC.

[0003]

In the random pattern generator 6 shown in FIG. 4, when an algorithmic address is serially generated, a pattern is created in advance and the pattern is stored in the random pattern generator 6. However, since the test pattern becomes long in the configuration of FIG. 6, a large capacity pattern memory is required. An object of the present invention is to provide a random pattern generation circuit that serially generates an algorithmic address in real time without the pattern memory 6B of FIG.

[0004]

To achieve this object, in the present invention, a CPU 1 connected to a bus 10,
A register 2A connected to the bus 10, an arithmetic unit 2B having the output of the register 2A as a first input, and a register 2C having an output of the arithmetic unit 2B as an input and an output as a second input of the arithmetic unit 2B. , An address generation circuit 2 connected to the bus 10 and comprising an address control circuit 2D for outputting a control signal 21, a load signal 22 and a shift signal 23, and the output of a register 2C as input, and the load signal 22 and the shift signal Shift register 3 for outputting by 23 and load signal 2
2 and the shift signal 23 as inputs, and a gate 4 that performs OR,
The output of the shift register 3 is used as the first input, and the register 2
The least significant bit of the output of C is used as the second input, and the selector 5 that selects the output by the input of the gate 4 is provided.

[0005]

The block diagram of the address generator according to the present invention will be described with reference to FIG. 2 in FIG. 1 is an address generation circuit,
3 is a shift register, 4 is an OR gate, 5 is a selector, and the CPU 1 and the bus 10 are the same as those in FIG. The address generation circuit 2 is composed of a register 2A, a computing unit 2B, a register 2C and an address control circuit 2D, and the address control circuit 2D generates a control signal 21, a load signal 22 and a shift signal 23.

The register 2A sets the data to be added / subtracted by the arithmetic unit 2B, and outputs it as the addition / subtraction data to the first input of the arithmetic unit 2B. The arithmetic unit 2B receives the address output signal 24A of the register 2C as a second input, adds and subtracts with the control signal 21 of the address control circuit 2D, and outputs it to the register 2C.

The address output signal 24 of the register 2C serves as an input of the shift register 3 and also receives the address signal 24A as a second input of the selector 4. The address signal 24A is the least significant bit of the address output signal 24 of the register 2C, and is the 0th bit of the address (hereinafter referred to as A0). Address signals 24 for bits other than A0
B, which is the first bit of the address (hereinafter referred to as A1) or more, and is output as the address output.

The shift register 3 includes an address control circuit 2
The address output signal 24 is loaded by the load signal 22 of D to fetch the input data, and A0 is input to the first input of the selector 5.
Is output. Further, the data taken in by the shift signal 23 of the address control circuit 2D, that is, the address signal 24
And the shift register 3 outputs A1 to the first input of the selector 5. The selector 5 selects either the first input or the second input according to the output of the gate 4.

When the output of the gate 4 is "0", the second input is selected and output. This operation generates an algorithmic address in parallel when measuring a normal memory IC. When the output of the gate 4 is "1", that is, when the shift register 3 is in the load or shift operation, the selector 5 selects the first input. When measuring a memory IC having a scan structure, this operation serially generates an algorithmic address.

Next, a timing chart showing the operation of serial generation in the case of an algorithmic address of 4 bits will be described with reference to FIG. The address signal 24 is A0
Among the 4 bits of A3, A0 is the least significant bit. The address signal 24 is loaded into the shift register 3 by the load signal 22, and the selector 5 outputs A0. Shift signal 23
Then, the shift register 3 performs a shift operation, and the selector 5 outputs A1. When the shift signal 23 is added, the shift register 3 performs the shift operation, the selector 5 outputs A2, and the selector 5 outputs A3 with the next shift signal 23. In this way, by repeating the load signal 22 and the shift signal 23, the selector 5 serially generates A0 to A3.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the circuit of the embodiment of FIG. 1 will be described with reference to FIG. A sequence program is written in the CPU 1 and is connected to the address generation circuit 2 by the bus 10. FFs 2A and 2C are used for the registers 2A and 2C in FIG. Data to be added / subtracted is set in FF2A. The output of the FF2A is connected to the first input of the arithmetic unit 2B, and the output of the FF2C outputs "A1-9" excluding "A0" as an address output to the outside and also connects to the data input of the shift register 3. And again
It is connected to the second input of the arithmetic unit 2B. The least significant bit “A0” of the address output is connected to the second input of the selector 5.

The control signal 21 of the address control circuit 2D is connected to the arithmetic unit 2B, and the arithmetic unit 2B executes addition / subtraction.
The output of the computing unit 2B is connected to the data input of the FF2C, and the signal 25 of the address control circuit 2D causes the FF2C to operate.
Is set to. The signal 26 of the address control circuit 2D is
It is connected to the clock input of the shift register 3 to load or shift the shift register 3. The load signal 22 and the shift signal 23 of the address control circuit 2D are connected to the mode input of the shift register 3 and the load signal 2
When 2 is "1", the shift register 3 is in the load mode, and when the shift signal 23 is "1", it is in the shift mode.

The output of the shift register 3 is connected to the first input of the selector 5, which selects the address control circuit 2D.
When either the load signal 22 or the shift signal 23 of "1" is "1", the address input to the first input is selected, and the algorithmic address is serially generated at this time. When both the load signal 22 and the shift signal 23 are "0", the selector 5 selects the address input to the second input and outputs the least significant bit "A0" of the output of the FF2C. At this time, "A1 to A9", which are bits other than "A0" in the output of the FF2C,
The output "A0" of the selector 5 generates an algorithmic address in parallel.

[0014]

According to the present invention, the address generating circuit,
Since a shift register and a selector are provided, data that generates an algorithmic pattern address is previously written in the pattern memory as in the prior art, and this pattern memory is read to generate the address. In comparison, an algorithmic address can be serially generated in real time simply by controlling the load and shift of the shift register. As a result, a large-capacity pattern memory becomes unnecessary and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an address generator according to the present invention.

FIG. 2 is a timing chart showing an operation when an address output is 4 bits.

FIG. 3 is a circuit diagram of an embodiment according to the present invention.

FIG. 4 is a configuration diagram of a random pattern generator and an address generator according to a conventional technique.

[Explanation of symbols]

 1 CPU 2 address generation circuit 2A register 2B arithmetic unit 2C register 2D address control circuit 3 shift register 4 gate 5 selector 10 bus 21 control signal 22 load signal 23 shift signal

Claims (1)

[Claims] 1. A CPU (1) connected to a bus (10), a first register (2A) connected to the bus (10), and an output of the first register (2A) as a first input. Is connected to the bus (10) and the second register (2C) whose input is the output of the arithmetic unit (2B) and whose output is the second input of the arithmetic unit (2B). , An address generation circuit (2) consisting of a control signal (21), a load signal (22) and an address control circuit (2D) that outputs a shift signal (23) and an output of a second register (2C). Input and load signal (22)
And a shift register (3) that outputs the shift signal (23)
, And the load signal (22) and shift signal (23) as input, OR gate (4) and shift register (3) output as first input, and output of second register (2C) Selector (5) that uses the least significant bit as the second input and selects the output by the input of the gate (4)
An address generator comprising: