JPH03231174A - Test pattern generator - Google Patents

Abstract

PURPOSE:To generate a test pattern for shortening the processing time of a calculator and conformable to the purpose of test by a method wherein all of paths capable of reaching an end point from a start point are traced while delay calculation is performed and the most critical path is selected. CONSTITUTION:A path trace delay calculation part 1 traces all of paths capable of reaching an end point from a start point while performing delay calculation and a critical path selection part 2 selects the traced paths. A pulse activating part 3 activates the path selected by the critical path selection part 2 and, when the selected path can be activated, a test pattern output part 4 generates the test pattern of the activated path and, when the selected path can not be activated, the selection part 2 selects a new path to activate the same. By this method, a critical path can be certainly selected and, since the path tried at the time of activation is limited, the processing time of a calculator can be shortened.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a test pattern generation device, especially a test pattern generation device used for delay calculation etc. during the design and manufacturing of digital circuits, which has a short computer processing time and meets the purpose of testing. In order to be able to generate test patterns based on a critical path selection section that selects the most critical path from among the paths selected; a path activation section that activates the path selected by the critical path selection section; and a test pattern output section that generates a test pattern for the activated path. It consists of

(Industrial Application Field) The present invention relates to a test pattern generator, and more particularly to a test pattern generator used for delay calculations and the like during the design and manufacture of digital circuits.

[Conventional technology]

In recent years, with the demand for larger and faster computer systems, it has become known that the digital circuits of mainframes and supercomputers, in particular, do not operate correctly due to abnormalities in signal propagation velocity (delay). Therefore, in order to ensure the reliability of the calculator,
It is necessary to perform the detection of the propagation velocity delay time described above. Such signal propagation speed measurements must be performed assuming the most time-consuming (critical) path, and the digital circuit must be set up under conditions that will result in such a path, that is, the test pattern must be set. There is a need. However, as the scale of the target digital circuits increases, the number of path combinations increases proportionally, and the computer processing time required to perform the above processing increases, so an efficient method is desired. It will be done. Conventionally, in the generation of test patterns for digital circuits as described above, in many cases, a final test pattern is created while searching for path limbs that can be activated. That is, a procedure is taken in which activation is attempted for all combinable paths.

(Problem to be solved by the invention) By the way, in the conventional test pattern generation described above, activation is performed for all combinations, so in order to improve the activation rate, it is necessary to increase the processing time of the computer. The problem is that it becomes long. Also, the activated path is not necessarily critical in terms of delay time (
There is also the problem that a path that is easy to activate is selected instead of one that takes time. That is, a path with simpler activation conditions (fewer activation conditions) may be selected and a test pattern created.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a test pattern generation device that can generate a test pattern that meets the purpose of a test with a short computer processing time.

[Means to solve the problem]

In the present invention, means for solving the above problems are as follows:
As shown in Figure 1, there is a path trace/delay calculation unit 1 that traces all possible paths from the start point to the end point while calculating the delay, and a critical path selection unit that selects the most critical path from the traced paths. 2, a path activation section 3 that activates the path selected by the critical path selection section, and a test pattern output section 4 that generates a test pattern of the activated path.

(Operation) According to the present invention, the path trace/delay calculation unit traces all paths from the start point to the end point while performing delay calculation, and the critical path selection unit selects the most critical path from the traced paths. do. Then, the path activation section activates the path selected by the critical path selection section, and the test pattern output section generates a test pattern for the activated path, so it is possible to reliably select a critical path. Since the paths tried during activation are limited, computer processing time can be reduced.

〔Example〕

Embodiments of the test pattern generation device according to the present invention will be described below with reference to the drawings.

1 to 3 show an embodiment of a test pattern generating device according to the present invention. In this embodiment, as shown in FIG. 1, the test pattern generation device includes a path trace/delay calculation unit 1 that traces all paths from a start point to an end point while calculating the delay, and a path trace/delay calculation unit 1 that traces all paths from the start point to the end point while a critical path selection unit 2 that selects a critical path; a path activation unit 3 that activates the path selected by the critical path selection unit;
The test pattern output section 4 generates a test pattern of an activated path.

First, the path trace/delay calculation unit traces all possible paths from one start point to the end point while calculating the delay (5TI), and the critical path selection unit selects the most critical path from the traced paths (S
r2). Then, the path activation section activates the path selected by the critical path selection section 5T3), and if activation is successful (Sr1), the test pattern output section (Sr1
) generates a test pattern for the activated path, and if activation is not possible, selects a new path and activates it, so it is possible to reliably select a critical path, and also to perform a trial at the time of activation. Since the number of paths to be used is limited, computer processing time can be reduced.

The above processing will be explained with reference to a specific circuit shown in FIG. Figure 3 shows four latches (Fl to F4),
Two AND gates (A.

B), one Noah gate (C) and one or gate (
D).

First, find the critical path from Fl to F4.

■Since the signal from Fl is combined at gate D, F1→
Total delay of A→C→D “13” and F1→B-
Find the total delay of D "11".

(2) Since the critical delay is F1→A-C→D, F1→A-C-+D is selected as the test path.

Next, activate the test path.

■Since gate A is an AND gate, other inputs are “1”
Therefore, the external input terminal P1 must be “1”.
give pa.

■Gate C is a Noah gate, so other inputs are “0°°
Therefore, latch F2 is scanned into OIT.

■Since gate D is OR, other inputs are “OII”.
Therefore, the gate B needs to be set to "0", and therefore the latch F3 is scanned in to 11011.

As a result, a test pattern is output by adding a pattern for transferring "O" and "1" from latch F1.

Therefore, according to this embodiment, the critical path Fl→A
-+C-4D is selected and activation is performed only on this path.

〔Effect of the invention〕

As explained above, according to the present invention, the test pattern generator includes a path trace/delay calculation unit that traces all the paths from the start point to the end point while calculating the delay, and a path trace delay calculation unit that traces all the paths from the start point to the end point, and It is composed of a critical path selection section that selects a path, a path activation section that activates the path selected by the critical path selection section, and a test pattern output section that generates a test pattern of the activated path. In addition to being able to select a critical path, it also has the effect of reducing computer processing time because the paths to be tried at the time of activation are limited.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing the principle and embodiments of the present invention, Fig. 2 is a flowchart showing the operation of the test pattern generator shown in Fig. 1, and Fig. 3 is a block diagram showing the operation of the test pattern generator shown in Fig. 1. It is a figure showing an example of occurrence. 1... Path trace delay calculation section 2... Critical path selection section 3... Path activation section 4... Test pattern output section

Claims (1)

[Scope of Claims] A path trace/delay calculation unit (1) that traces all possible paths from a start point to an end point while performing delay calculations; and a critical path selection unit that selects the most critical path from the traced paths. (2), a path activation section (3) that activates the path selected by the critical path selection section, and a test pattern output section (4) that generates a test pattern of the activated path. A test pattern generator for