JPH0242369A - Test circuit for counter - Google Patents

Abstract

PURPOSE:To easily make the test for a counter in a short time by inputting data, all bits of which are '0' or '1', at first with a shift register and inputting on and after the second time by means of making the data to inverse in order from the bit in a lowest rank. CONSTITUTION:A test circuit consists of the shift register S1 to generate data for the test, a selecting circuit M1 which is controlled by a control signal X1 to change-over the signal to be inputted to the counter C1, and a register R1 to output counted values of the counter C1 to a data bus D1. At first from the shift register S1, the data, the all bits of which are '0' is '1' are inputted to the counter C1 to be tested to the make counter C1 to perform an increment operation. On and after the second time, the data for the test which '0' is jammed in order form the bit in a low rank are inputted to the counter C1 from the shift register S1, and the output results are confirmed respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a test circuit for counters. More specifically, the present invention relates to a counter test circuit that can perform a counter operation test with simple operation and in a short time.

BACKGROUND OF THE INVENTION Conventionally, built-in counters in integrated circuits have been tested using the following method. That is, a count value is input from a register to a counter, and if a value can be freely set in the register, a specific value is written in the register to operate the counter.

Next, the operation result of the counter is read from the register data related to the operation of the integrated circuit or the output of the counter, and compared with an expected pattern to confirm whether the operation of the counter is good or not.

By repeating the above operations, the operation of all bits of the counter was tested.

Problems to be Solved by the Invention In the conventional counter test described above, for all bits of the counter, when there is a carry, "θ" → "1" or "1" - 0, and when there is no carry, the result is “0” → “0”
Or, to confirm that the operation from "1'" to "l" is to be performed, the operation of writing data into a register, inputting the data from the register to the counter, and operating the counter is repeated.

Therefore, if writing to the register or operating the counter is complicated, there is a drawback that testing the counter requires an enormous amount of time.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a counter test circuit that solves the problems of the prior art described above and can test a counter in a short time with simple operations.

Means for Solving the Problems According to the present invention, in a circuit that tests a counter built into an integrated circuit by inputting data to the counter and operating the counter, all bits are initially set to "1" or "0". A counter test circuit, characterized in that a shift register capable of inputting data that is `` and inverting the data one bit at a time starting from the least significant bit from the second time onwards is coupled to the counter so that it can be input in parallel. is provided.

Operation The counter test circuit of the present invention has a configuration in which data in which all bits are "0" or "11" is first inputted using a shift register, and from the second time onwards, each bit is inverted and inputted sequentially starting from the least significant bit. It becomes.

In order to test a counter using the counter test circuit of the present invention, it is preferable to follow the following procedure. First, data in which all bits are "0" is input from the shift register to the counter to be tested, and the counter is incremented. By checking the output of this counter, it is possible to test whether the least significant bit of the counter is incremented from 10" to "1" and whether unnecessary bit inversion occurs.Next, the least significant bit from the shift register is Input data in which the bit is "L" and other bits are "0" into the counter, operate the counter, and check the output result.Next, input data from the shift register where the lower two bits are "1" and other bits are "0". Input data whose bit is "0" into the counter and check the output result.In this way, "1" is packed starting from the lower bit (input test data from the shift register to the counter each time). By this,
It is possible to efficiently test the operation of the counter when it is incremented. Also, when testing the operation during decrement, first input data in which all bits are "1" from the shift register to the counter, and from the second time onwards, test the data in which "0" is filled in sequentially from the lower bit. This is done by inputting the data from the shift register to the counter and checking the respective output results.

By using the counter test circuit of the present invention and performing the test according to the above procedure, you can test the operation of all bits of the counter when incrementing or decrementing by simply operating the counter continuously (number of counter bits + 1) times. becomes possible. Further, in both cases of increment and decrement, the shift register of the counter test circuit of the present invention almost automatically generates test data, so that the test can be performed very efficiently.

Hereinafter, the present invention will be explained in more detail with reference to Examples.
The following disclosure is merely an example of the present invention and does not limit the scope of the present invention.

Embodiment 1 FIG. 1 shows an embodiment of a counter test circuit of the present invention. The counter test circuit shown in FIG. 1 includes a shift register S1 that generates test data, and a control signal x1.
It is mainly composed of a selection circuit M1 that switches the signal input to the counter C1, and a register R1 that outputs the count value of the counter C1 to the data bus D1. The shift register S1 is configured such that the lowest bit is connected to the power supply Vcc and inputted with '1#.

In addition, after all bits of the shift register S1 become "0" in the reset state, the control signal x4 inverts the data one bit at a time from the lowest bit to the highest bit. It is structured so that it is packed toward the bit.

In the test mode, the control signal Xl causes the selection circuit M1 to select the shift register S as an input to the counter C1.
Select output 1. The counter C1, which receives the test data, increments the input data in accordance with the control signal x2, and outputs the result to the register R1. By control signal X3, counter C is transferred from register R1.
The counter C1 can be tested by outputting a count value of 1 to the data bus D1 and reading it out.

Taking an 8-bit counter as an example, the operation of the counter test circuit of this embodiment will be explained with reference to FIG.

FIG. 3 is a data transition diagram of the shift register output and the counter output when a counter is tested using the counter test circuit of this embodiment.

First, reset the shift register S1 and set it to “00000”.
000" is input to the counter C1. The counter C1 is operated by the control signal x2, the input data is incremented by one count, and the count value is output to the register R1.

The value of counter C1 is transferred to register R1 by control signal X3.
and causes the value to be output to the data bus D1. By checking whether the value of register R1 is "00000001", it is possible to test whether the least significant bit of counter C1 is incremented from "O" to "1'" and whether unnecessary bit inversion occurs. Yes, you can.
Control signal X.

4, the value of shift register S1 is set to “000000.
01" and inputs it to the counter C1. As before, operate the counter C1 with the control signal x2, read the result via the register R1 and data bus D1, and input it to the counter C1.
000010". This will result in
It is possible to confirm the normal increment operation and carry propagation of the lowest bit of counter C1 from “1” to “O” and the second bit from “0” to “1” due to carry propagation, and unnecessary bits. It is possible to test whether there is no inversion of .From now on, the data input from shift register S1 to counter C1 can be controlled by control signal X4.
00000011”, “00000111”, etc.
..., "11111111", and the output of counter C1 is "00000100" for each of them.
,'“00001000”,... “oooo
oooo”. Check if it is “1111111
If 1'' is input, the carry propagates from the least significant bit to the most significant bit by incrementing the count by 1. In this way, it is possible to determine whether individual increment operations from "0" to "1" and "1" to "0" and carry propagation have been performed for all bits of counter C1, and whether unnecessary It becomes possible to test whether or not bit reversal occurs. In particular, in the data input from the shift register, the number of bits set to "1'" differs each time, so if there is an abnormality in carry propagation, it is possible to identify the position. In the case of an 8-bit counter as in this embodiment, by operating the counter 9 times in succession as described above, it is possible to know whether the increment operation and carry propagation are normal or abnormal for each bit for all bits, and the count up is increased. All tests necessary for operation can be completed. Moreover, since the shift register S1 generates the data used for the test each time, there is no need to input test data from the outside each time as in the past. It goes without saying that even with counters other than 8 bits, it is possible to perform a test by continuously operating the counter (number of bits of the counter + 1) times in the same manner as above.

Embodiment 2 FIG. 2 shows another embodiment of the counter test circuit of the present invention. In the counter test circuit shown in Figure 2, the input of the rightmost bit of the shift register is replaced with a power supply, and a signal x representing increment/decrement of the counter is used.
5 is different from the first embodiment. Hereinafter, the explanation of this embodiment will focus on the differences from the first embodiment.

In the counter test circuit of this embodiment, the signal x5
When is “1”, the counter CI increments and the signal x
5 is 0", the counter C1 is decremented. Taking an 8-bit counter as an example as in the first embodiment, the operation of the counter test circuit of this embodiment will be explained with reference to FIGS. 3 and 4. FIG. 4 is a data transition diagram of the shift register output and the counter output when a counter decrement operation is tested using the counter test circuit of this embodiment.

In the counter test circuit of this embodiment, first, the control signal x
5 is set to "1", and the shift register S1 is set to "oooo" as shown in FIG. 3, as in the first embodiment.

Input the inverted data from "000" to "11111111" in order from the lowest bit to "0" → "1",
The increment operation and carry propagation for each bit of the counter C1 are tested.

After that, the control signal x5 is set to "0", and as shown in FIG.
1111" is input to the counter C1. The control signal X2 operates the counter C1, decrements the input data, and outputs it to the register R1. The control signal x3 outputs the value of the register R1 to the data bus D1. By reading it out and checking whether it is "11111110", you can test whether the lowest bit of the counter C1 is decremented from "l" to "0" and whether unnecessary bit inversion occurs. .next,
The value of shift register S1 is set to “11” by control signal X4.
111110'' and input it to the counter C1.Same as last time, operate the counter C1 with the control signal “0” → “1” of the lowest bit of C1
It is possible to test whether or not there is an error, a decrement operation of the second bit from "1" to "0", borrow propagation, and unnecessary bit inversion.

Thereafter, the data input from the shift register S1 to the counter C1 is changed to "11111100" by the control signal x4.
"11111000", ..., "00000"
000", and the output of counter C1 is "11111011" and "1111011" respectively.
1”, ...... By confirming whether it is "11111111", all bits of counter C1 are decremented from "1" to "0" and from ``0'' to ``1''. It is possible to test whether operation and borrow propagation have occurred, and whether unnecessary bit inversion has occurred as a result.In other words, in the counter test circuit of this embodiment, it is possible to test whether the operation and borrow propagation have occurred. Through nine consecutive counter operations, it is possible to know whether there is an abnormality in the decrement operation for each bit and the borrow propagation, and it is possible to perform all the tests necessary for the countdown operation.Testing the counter of this embodiment The circuit can also test both increment and decrement operations for counters other than 8 bits by continuously operating the counters (number of bits of the counter + 1) times in the same manner as above.

As described in detail, according to the counter test circuit of the present invention, the counter can be tested by continuously operating the counter with (the number of bits of the counter + 1) the counter. Moreover, there is no need to input test data from outside.

This is because the counter test circuit of the present invention uses a shift register to first input data in which all bits are "1" or "0" to the counter, and from the second time onwards, data from the lowest bit of the wave data is input. This was made possible for the first time by a configuration in which data inverted one bit at a time is input to the upper bits.

The present invention has the effect of significantly shortening the counter test time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of a test circuit for a counter according to the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, and FIGS. FIG. 3 is a data transition diagram when an 8-bit counter is tested using the counter test circuit of FIG. [Main reference numbers] Sl...shift register, Ml...selection circuit, C1...counter, R1...
・Register, Dl...Data bus, X1 to X5...
・Control signal, VCC...Power supply Figure 1

Claims (1)

[Claims] In a circuit that tests a counter built into an integrated circuit by inputting data to a counter and operating the counter, data in which all bits are “1” or “0” is input first, and from the second time onwards, the counter is tested. 1. A counter test circuit characterized in that a shift register capable of sequentially inverting data one bit at a time starting from the least significant bit is coupled to the counter so as to be input in parallel.