JP2511028B2 - Memory test method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test method, and more particularly to a simple, high-speed and highly accurate test method for a memory using a bidirectional linear feedback shift register.

[Conventional technology]

In testing random access memory (RAM), more test patterns than before are known.
For example, if the memory capacity is N bits, the so-called test time is proportional to N, such as marching pattern and checkerboard pattern, and the test time
Walking as N ² pattern test proportional to N ^2, galloping pattern and the like are known. These are used properly in terms of test time and test accuracy. For example, the N pattern test is inferior in terms of test accuracy-it is used because high-speed testing is possible, and the N ² pattern test is used. It is used when there is a problem in terms of time-test accuracy is important. In addition, these intermediate M
^{A 3/2} pattern is also proposed.

On the other hand, the recent improvement in the integration density of RAM is remarkable, 1Mbit, 4M
With the advent of bit elements, test time has become a major issue. From this point of view, research on a test method with high test accuracy and capable of high-speed test is actively conducted. In addition, a method has been considered in which a test circuit is built in the chip and an automatic test can be performed.

In the past, K.K.
“Built-In Testing of M” by Kinoshita, KK Soluja
emory Using an On-Chip Compact Testing Scheme ", IEEE, Transactions on Coomputers, Vol.C-35, N
o.10, pp862-870 (October 1986).
This method adds a write pattern that takes into account fixed failures of memory cells, address decoding failures, and failures due to the influence of the contents of neighboring cells, and then reads the memory contents by sequentially specifying the addresses and reading Is a simple test method that counts the number of "1" s or the number of "1s" based on the logic (count logic) considering data from neighboring cells and compares it with the correct value.

[Problems to be solved by the invention]

In the above-mentioned test method, the control is performed by a microprogram built in the chip, and the correct value and the like are also built in the control program to carry out comparison inspection. Therefore, even with the simple test method, control is not necessarily easy because a microprogram must be used and correct values must be prepared in advance.
In addition, the stepping of the address is a form in which 1 is added in principle, and there is a problem that it cannot be said that the address test is irregularly changed to perform the margin test of the address decoder. Furthermore, for example, the number of “1” s in the read data is counted and compared with the correct value, so that the address is often separated and inspected, which is not necessarily a highly accurate test method. ing.

An object of the present invention is to provide a simpler, faster, and more accurate memory test method that does not require obtaining the correct answer value in advance.

[Means for solving problems]

Linear feedback shift register (LFSR) is often used for compression of test output or encoding / decoding circuit at the time of error correction, usually based on irreducible polynomial,
Often used as a one-way shift register.

The present invention relates to a memory having ^{a 2a} word-b bit structure,
LFSR and g constructed based on a-th order primitive polynomial g (x)
A bidirectional address generation LFSR capable of bidirectionally generating an a-bit address sequence is provided, which has a structure in which an LFSR configured based on the reciprocal polynomial for (x) is switched by a switching gate in a shared register format. With this bidirectional LFSR, when 2 ^a forward addresses are generated during a write operation, it is possible to generate an address sequence in the reverse direction of the write operation during a read operation. For compressing (a + b) bit length information that compresses both data at the same time
The LFSR is also configured to allow bidirectional operation in the same manner.

[Work]

First, for example, "1" is set as the initial value of the information compression LFSR.
Information is set in advance, and based on this, the bidirectional address generation LFSR is shifted in the forward direction to generate an address, and a write operation to the memory is performed with the specified write data, and at the same time Both address information and write data (a + b) bits are simultaneously input to the bidirectional compression LFSR in parallel and shifted in the forward direction, the addresses are stepped and compressed one after another to generate 2 ^a addresses. When finished,
Input the (a + b) bit of the LFSR for information compression All
Set to "0" and step forward only once. Next, using this result as the initial value, the LFSR for information compression is set to the LFSR for backward information compression.
When switched to, the LFSR for address generation is also switched, an address in the reverse direction to that at the time of writing is generated, and at the same time the memory read operation is executed, the address information and read data are converted to the LFSR for reverse direction information compression. Input in parallel, step by step, and after the last 2 ^a addresses have been generated,
The input of the (a + b) bit of LFSR is set to All "0", and only one step is performed in the reverse direction. As a result, the original initial value All
Check if a "1" was generated in the LFSR. At this time, if the original initial value All “1” is generated in the information compression LFSR, the memory is normal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of an embodiment of the present invention. 1 is a memory cell array, 2 is an address decoder, 3 is a register for storing write data, 4 is a register for storing read data, and 5 is a bidirectional LFSR. Address generator, 6 is 2
Input selection circuit, 7 is an information compressor composed of bidirectional parallel input LFSR, 8 is an AND gate, R / W is a control signal for controlling writing or reading, C is a clock signal, P is a preset terminal of a shift register, and t is It is a timing signal.

In this embodiment, basically the generation of address information,
The use of a bidirectional LFSR to create a compressed value is a major difference from the prior art. Therefore, firstly bidirectional LF
The SR will be described.

If the forward LFSR is based on the primitive polynomial g (x), the backward LFSR is the reciprocal polynomial g ^* (x) of g (x).
It is based on. If g (x) is a polynomial of degree a, then g ^* (x) is defined as follows.

g ^* (x) = x ^a g (1 / x) Therefore, for example, if g (x) = x ³ + x + 1, then g ^*
A ^{(x) = x 3 + x} 2 +1.

FIG. 2 is a diagram for explaining the operation of the LFSR based on the above-mentioned porous type, (a) is based on g (x), and (b) is g.
^* Based on (x). In FIG. 2, R _{0 to} R ₂ are shift registers, 11 is an exclusive OR gate, and C is a clock signal. The construction method of LFSR is described in Miyagawa, Iwatare and Imai, "Code Logic" (Shokodo), pages 112-135.

Now, in FIG. 2 (a), the initial value of LFSR is (1,0,
0), when the clock signal C is stepped in sequence, 100 → 01
Seven patterns different from 0 → 001 → 110 → 011 → 111 → 101 can be generated. In general, an LFSR based on a-th order primitive polynomial can generate different 2 ^a −1 patterns.

FIG. 2 (b) shows the case where the registers R _{0 to} R ₂ are left as they are and the direction of shift is reversed, which is equivalent to the LFSR by the reciprocal polynomial. This is referred to as LFSR ^* .
Now, when the LFSR ^* of FIG. 2 (b) is operated with the final value 101 obtained in FIG. 2 (a) as the initial value, the reverse of the LFSR of FIG. 2 (a) as the clock advances. You can see that we are going through the steps. That is, 101 → 111 → 001 → 110 →
It changes from 001 to 010 to 100, and finally returns to the initial value of 100 in Fig. 2 (a).

FIG. 3 shows the functions of (a) and (b) of FIG.
The figure shows a bidirectional LFSR in which R _{0 and} R ₂ are shared by switching gates, and 9 is a 2-input AND gate, 1
0 is a 2-input OR gate, and 11 is an exclusive OR gate.
According to this LFSR, if the R / W pin is set to “1” when writing,
LFSR next to shift to the right, when "0" at the time of reading, equals the LFSR ^* to shift to the left. Therefore,
The R / W pin to "1", sets the initial value "100" in the three shift registers R ₀ to R _2, if shift to the right by the addition of six clock signal C, Fig. 2 The information sequence shown in (a) can be generated, and finally "101" remains. Next, if the R / W terminal is set to "0" and the value is shifted in the opposite direction with "101" as the initial value, this becomes equal to LFSR ^* shown in Fig. 2 (b),
Information on the reverse sequence is obtained and should return to the initial value "100". If the address information All “0” is obtained by resetting the LFSR, it is possible to generate all 2 ^a different addresses.

The address generator 5 of FIG. 1 uses a bidirectional LFSR as shown in FIG. 3, which allows the address sequence to be reversed during writing and reading. That is, the address generator 5 generates an address of the forward sequence in synchronization with the clock signal C by setting the R / W terminal to "1" at the time of writing, and at the time of reading, the R / W terminal becomes "1". By setting to "0", an address in the reverse sequence to that at the time of writing is generated. The address generated by the address generator 5 is decoded by the address decoder 2, the test pattern data of the write data register 3 is written in the memory array 1 in the forward direction address sequence at the time of writing, and the reverse direction at the time of reading. The data is read from the memory array 1 in the address sequence and set in the read data register 4.

The selection circuit 6 switches the input to the information compressor 7 by the R / W signal. When writing (R / W = 1), the output of the write data register 3 is selected, and when reading (R / W = 0). ), The output of the read data register 4 is selected. In this way, the information compressor 7 writes the write address and the write data according to the forward address sequence at the time of writing.
At the time of reading, the read address and read data are input in parallel according to the reverse address sequence.

Next, the operation of the parallel input LFSR will be described with a simple example.

FIG. 4 shows an example of a parallel input LFSR composed of four shift registers R _{0 to} R ₃ . The feedback of the output value of the shift register R _{3 at} the final stage is the primitive polynomial g (x) = x ⁴ +
determined at x + 1, in this case it applied to the exclusive OR gates 11 ₀ and 11 ₁ which is located at the input of the R ₀ and R _1. Also,
Another input of each exclusive OR gate is the output of the preceding shift register, also a data to be added in parallel to the parallel input terminals 12 _{0-12 3.} Data for this 12 _{0-12 3,} 2 ^a
In the case of a word-b bit memory, m = a including both the address information a bit and the write or read data b bit.
This is data corresponding to + b bits. C is a clock, is inputted to the clock whenever the input information 12 _{0-12 3} shifts the contents of shift register R ₀ to R ₃ in the next stage.

Generally, the operation contents of the parallel input LFSR shift register are
It can be expressed by the product of the characteristic matrix determined by the irreducible polynomial g (x) of degree m and the m-th order input data vector I. The irreducible polynomial, Then, T can be expressed by an m × m positive direction matrix as follows.

In the case of the example shown in FIG. 4, the irreducible polynomial g (x) = x ⁴
From + x + 1, it can be expressed as follows.

If n pieces of data of I ₀ , I ₁ , ..., I _n-2 , I _n-1 having an m-bit width are input to this LFSR in this order, S _i , i = 0, 1, ..., N-1 can be generally expressed by the following equation.

S _i = I _i S _i−1 · T (1) i = 0,1, ..., n−1 (S ₋₁ = 0) where S _i and I _i are m-th order row vectors, Indicates exclusive OR. In the example shown in FIG. 4, n = 4 pieces of the following input data are input in the order of I _W1 → I _W2 → I _W3 .

In this example, the address is the first two bits and the write data is the second two bits. The address in this case is x ²
It can be generated by a two-stage LFSR created by a primitive polynomial of + x + 1. At this time, as a result of LFSR at each stage, S _Wi (i
= 0,1,2,3) can be expressed by the following equation (1).

S _W0 = I _W0 = (001
1) S _W1 = I _W1 S ₀ · T = I _W1 I _W0 T = (101
0) S _W2 = I _W2 S ₁ · T = I _W2 I _W1 TI _W0 T ² = (100
0) S _W3 = I _W3 S ₂ · T = I _W3 I _W2 TI _W1 T ² I _W0 T ³ = (111
0) The information compressor 7 shown in FIG. 1 is composed of a bidirectional LFSR like the address generator 5, but a parallel input is further added. m
FIG. 5 shows an operation sequence of the information compressor 7 including the bidirectional LFSR to which the parallel input is applied, in the case of the fourth order.

FIG. 5 (a) shows the same circuit as the example of FIG.
Input the parallel input data as I _W0 → I _W1 → I _W2 → I _W3 . Also, the initial value K _W of the LFSR before adding these parallel inputs is set to All “1”. This can be done by setting the preset terminal P in advance. Next, S _W0 is obtained by adding the first data I _W0 and a clock to shift the contents of the shift registers R _{0 to} R ₃ . S _W0 can be expressed by the formula (1) as S _W0 = I _W0 + K _W · T. Similarly, after applying up to I _W3 , the contents of the shift register are S _W3 =
(1010) Next, set the parallel input to All “0” and set 1
The clock is added only once to advance the LFSR. This action S
It is displayed as _W3 · T, and the result is (0101).

Next, consider an LFSR ^* with the shift direction reversed by the contents of this register. This LFSR ^* is the reciprocal polynomial g
^* (X) = constructed by x ⁴ + x ³ +1. This is shown in FIG. 5 (b). At this time, the initial value is S _W3
T and K _R = (0101). For parallel input, this time input the data in the reverse sequence that was input to the previous LFSR. That is, I _W3 (= I _R0 ) → I _W2 (= I _R1 ) → I _W1
(= I _R2 ) → I _W0 (= I _R3 ). This way,
After the first clock is input and the first shift is executed, S _R0 = I _R0 K _R · T ⁻¹ is obtained. At this time I _R0 = I
_W3 and T ⁻¹ is the inverse matrix of T. Thus, I _R0 →
With I _R1 → I _R2 → I _R3 applied, finally S _R3 = I _R3 S _R2
・ T ⁻¹ = (1011) is obtained. Next, the parallel input is set to All “0” and the clock is added only once to advance the LFSR ^* .
This operation can be expressed as S _R3 · T ^−1, and as a result, it becomes equal to the vector of All “1” of the initial value K _W = (1111) in FIG. 5 (a). Then, it can be proved that S _R3 · T ⁻¹ is equal to K _W as follows.

^{_{S R3 · T -1 = (I}} R3 S R2 · T -1) T -1 = I R3 · T -1 S R2 · T -2 = I R3 T -1 (I R2 S R1 T -1) T - _{^{2 = I R3 T -1 I R2}} T -2 S R1 T -3 = I R3 T -1 I R2 T -2 (I R1 S R0 T -1) T -3 = I R3 T -1 I R2 T - ² I _R2 T ^-2 I _R3 T ^-3 S _R0 T ^-4 = I _R3 T ^-1 I _R2 T ^-2 I _R1 T ^-3 (I _R0 K _R T ^-1 ) T
^-4 = I _R3 T ^-1 I _R2 T ^-2 I _R1 T ^-3 I _R0 T ^-4 K _R T ^-5 Here K _R = S _W3・ T = (I _W3 S _W2・ T) = I _W3・ TS
_W2 / T ² = I _W3 / TI _W2 / T ² S _W1 / T ³ = I _W3 / TI _W2 / T ² I _W1 / T ³ S _W0 / T ⁴ = I _W3 / TI _W2 / T ² I _W1 / T ³ I _W0・ T ⁴ K _W
-T ⁵ This K _R and I _R0 = I _W3 , I _R1 = I _W2 , I _R2 = I _W1 , I _R3 = I _W0
Substituting, the final result of S _R3 · T ^-1 above is

(I _R3 T ^-1 I _R2 T ^-2 I _R1 T ^-3 I _R0 T ^-4 ) (K _R・ T ^-5 ) = (I _W0 T ^-1 I _W1 T ^-2 I _W2 T ^-3 I _W3 T ^-4 ) (I _W3 TI _W2 T ² I _W1 T ³ I _W0 T ⁴ K _W・ T
⁵ ) T ^-5 = (I _W0 T ^-1 I _W1 T ^-2 I _W2 T ^-3 I _W3 T ^-4 ) (I _W3 T ^-4 I _W2 T ^-3 I _W1 T ^-2 I _W0 T ^-1
K _W ) = K _W Next, it will be explained that such an operation can be generally realized by the LFSR having the above configuration. Assuming that the initial value is K and n inputs I ₀ , I ₁ , ..., I _n-1 are added, the contents of the shift register at that time S _W0 , S _W1 ,
…, S _W-1 and S _Wn are as follows. However, S _Wn is a 1-clock shift operation in which the input is "0".

Next, S _Wn is input as the initial value in the opposite direction of I _n-1 , I _n-2 , ..., I ₁ , I _0, and the result of shifting in the opposite direction is S _R-1 , S _R0 , ..., S
_Rn is as follows. However, S _Rn is a 1-clock shift operation in which the input is “0”.

Substituting the S _Wn for the last term in this ^{_{ゝ, S Wn · T - (n}} + 1) = I n-1 · T -n I n-2 · T - (n-1) ... I 1 T - ^{From 2} I ₀ T ^-1 K, S _Rn becomes as follows.

S _Rn = (I ₀ T ^-1 I ₁ T ^-2 I ₂ T ^-3 ... I _n-1 T ^-n ) (I _n-1 T ^-n I _n-2 T- ^(n-1) ... I
₁ T ⁻² I ₀ T ¹ K) = K Therefore, it can be seen that S _Rn is generally equal to the initial value K.

As described above, in the information compressor 7 of FIG. 1, at the time of writing, after inputting the write address and the write data in the normal sequence to the LFSR set to the initial value All “1”, the input is set to “0” and shifted once. Operation, and at the time of reading, use this result as the initial value, input the read address and read data in the reverse direction with LFSR ^* , and finally set the input to "0" and add the shift operation once. Initial value of All
Can be returned to "1". This is a relationship that holds at least when there is no error in the information input at the time of reading.

Now, suppose that the input of LFSR at the time of reading is as follows in the example of FIG.

That is, it is assumed that the read data of I _R1 and I _R3 each have an error of 1 bit (indicated by a circle in the above) due to a memory failure. At this time, the compression values S _R0 , S _R1 , S _R2, etc. operated using the LFSR of FIG. 5 (b) are as follows.

K _R = (0101): Initial value S _R0 = (0000): I _R0 K _R · T ^-1 S _R1 = (0101): I ′ _R1 S _R0 · T ^-1 S _R2 = (0111): I _R2 S _R1 · T ^-1 S _R3 = (0101): I ′ _R3 S _R2 · T ^-1 S _R3 · T ^-1 = (1010) ≠ K _W From now on, S _R3 · T ^-1 is the original initial value K _W There is no All “1”. From this, it is possible to detect an error in the read data.

FIG. 6 shows a specific structure of the bidirectional parallel input LFSR which simultaneously realizes the functions of (a) and (b) of FIG. In FIG. 6, by setting the R / W signal to "1" or "0", the operation is switched to that of FIG. 5 (a) or (b). In addition, using the preset terminal P, the shift registers R _{0 to} R ₃
Set the initial value All “1” to. Note that C is a clock signal.

The AND gate 13 in FIG. 1 generally takes a logical product condition of (a + b) bits, and is bidirectional in the information compressor 7.
Input all register outputs of LFSR in parallel, and output “1” if they are all “1” (normal).
A timing signal t is added to the AND gate 13, and when the test sequence is completed, the timing signal t is set to "1" to confirm the test result.

In the above description, the length of the LFSR as the information compressor 7 is basically (a + b) bits, but in the case of a memory having a large word direction and a large address bit length a, a space is created via an exclusive logical AND gate. Obviously, it can be compressed into shorter LFSR structures. In this case, since the object to be inspected is mainly read data, it is necessary to avoid compressing b.

Further, in the above description, the content of the write data is not particularly mentioned. This write data may use a checkerboard pattern that writes in a checkerboard pattern of "0" and "1" for a two-dimensional memory array in order to test the influence from adjacent memory cells. Data to be written may be determined in advance and input to the write data register 3.

Further, it is easily possible that the address generator 5 used in the present invention further passes through the control signal and the gate so as to be a normal address register during a normal online operation and an LFSR during a test. .

Regarding the bidirectional LFSR used in the present invention,
It was shown earlier that even if the LFSR configuration starts with an arbitrary initial value, it will eventually return to the initial value. Therefore, although "1" is set as the initial value in the embodiment, it is not always necessary to set this value, and any value can be set as the initial value, whereby the AND gate 8 in FIG. Any detection circuit may be used.

〔The invention's effect〕

As described above, according to the present invention, it is not necessary to obtain the signature value in advance, and by using the bidirectional LFSR for the generation of the address information and the compression of the information through the write operation and the read operation of the memory, it is very simple. There is an advantage that various memory test methods can be realized. In particular, according to the method of the invention, the final result is the value of all LFSRs, eg All “1”.
It is possible to inspect the normality of the memory only by confirming, and there is an advantage that it becomes a simpler test method.

Also, to generate address information that changes randomly
Since it uses LFSR, it is also a marginal test of the address decoder due to changes in address information. Further, in the method of the present invention, the address changed at random in the case of writing changes the address in the direction opposite to that in the case of reading, so that there is an advantage that the test can be performed with higher accuracy for the address decoder. is there.

Also, because control is easy and the test circuit has a simple configuration, these circuits can be mounted on a chip in a random access memory, etc., and automatic testing with a built-in chip is relatively easy to configure. it can.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a diagram for explaining an operation sequence of a bidirectional LFSR, and FIG. 3 is a bidirectional
FIG. 4 is a diagram showing a specific example of LFSR, FIG. 4 is a diagram for explaining how input information is compressed by LFSR, FIG. 5 is a diagram for explaining the operation sequence of bidirectional parallel input LFSR, and FIG. 6 is bidirectional parallel input.
It is a figure which shows the specific example of LFSR. 1 ... Memory array, 2 ... Address decoder, 3 ... Write data register, 4 ... Read data register, 5 ... Bidirectional LFSR address generator, 6 ... Input selection circuit, 7 ... Bidirectional parallel Information compressor by input LFSR, 8 …… AND gate.

Claims (1)

(57) [Claims] 1. A memory having ^{a 2a} word-b bit configuration,
From an address generator consisting of an a-bit length bidirectional linear feedback shift register (hereinafter referred to as bidirectional LFSR) and an (a + b) bit length bidirectional parallel input linear feedback shift register (hereinafter referred to as bidirectional parallel input LFSR) First, an initial value K is set to the bidirectional parallel input LFSR of the information compressor, and then the bidirectional LFSR of the address generator is shifted in the forward direction to generate a forward address sequence. At the same time as performing the write operation to the memory with the predetermined write data according to the generated address, the address information and the write data are sequentially input in parallel to the bidirectional parallel input LFSR of the information compressor, and the bidirectional parallel input LFSR is input. When the generation of 2 ^a addresses is completed by shifting in the forward direction and compressing one after another, the input of the bidirectional parallel input LFSR is set to all “0” and set to 1
Shift forward only a number of times, then shift the bidirectional LFSR of the address generator in the reverse direction to generate the address sequence in the reverse direction of the write,
At the same time as the reading operation to the memory is performed according to the generated address, the address information and the read data are sequentially input in parallel to the bidirectional parallel input LFSR of the information compressor, and the bidirectional parallel input LFSR is reverse to the writing operation. Direction, then compresses one after another, and after the occurrence of 2 ^a addresses, the bidirectional parallel input
The input of LFSR is all "0", and it shifts to the opposite direction only once. As a result, the original initial value K is input to the bidirectional parallel input LFSR.
A memory test method characterized by testing the normality of a memory by checking whether or not is generated.