JPS59132500A - 2-bit error correcting system - Google Patents

Abstract

PURPOSE:To attain error correction up to 2-bit by providing an inverted write and re-read means re-reading a data in response to the detection of a bit error and a syndrome generating means generating a specific syndrome from a data read again. CONSTITUTION:Suppose that an error occurs in information bits D0, D8. From the read data, 110101 is generated as shown in a reading data syndrome. All bits D0-C5 of the reading data are inverted to form a rewriting data, this is read again to form a syndrome, then 001101 is obtained and it indicates that the D8 has an error. Thus, the syndrome is formed by the re-reading data and only the bit designated by the syndrome is kept as it is and all remaining re-reading data (only information bit) is inverted, then the data is corrected into the original correct data as shown in the corrected data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction method in a storage device such as an information processing system.

1-bit error correction 2-bit error detection code (SEC-
DED code: Single Error Corre
cti-on Double Error Dete
Conventionally, the following method is known as a method for correcting errors in 2 bits 1 including node errors (fixed errors) using a single error correction double error protection code.

One of them is disclosed in the defective memory tolerance control method described in Japanese Patent Application Laid-Open No. 51-137335, and the other one is:
This is disclosed in the error correction method described in Japanese Patent Laid-Open No. 56-68997.

However, as will be explained later, in the former case, there are special restrictions on the parity generation matrix for generating check pit money, and only a parity generation matrix of a type that does not change the syndrome even if all information pits and check bit money are reversed is used. The disadvantage is that it cannot be done.

In the latter case, information bits and check bits are written into memory using the 5EC-DED code, and if a 2-bit error is found during reading, all the read information bits and check pits are inverted and written into the same memory again. After reading this again, the information bits and check pins are inverted again, and the re-inverted information bits and check pins If are used to generate a syndrome, making it possible to correct errors up to 2 bits including hard errors. However, this has the disadvantage that the number of processing steps is somewhat increased.

The object of the present invention is to provide a system which eliminates all the above-mentioned conventional drawbacks.

The system of the present invention is an error correction system for a companion storage device using a 1-bit error correction, 2-bit error detection code, and is read from an address of the storage device specified by an address signal, and from a plurality of information bits and check bits. an inversion write/reread means for inverting the read data in response to detection of a 2-bit error in the data, writing it to the same address as the read address, and then rereading the take; syndrome generation means for generating a specific syndrome value from the taken data, and correction execution means for inverting the information pin 14 of the information bits of the re-read take other than the bits specified by the syndrome. There is.

Next, the present invention will be described in detail with reference to the drawings.

First, we use the 5EC-DED code to find the hardware error? The principle for correcting errors of up to 2 bits will be explained.

Figure 1 (A), (a and (Q) are diagrams for explaining the entire parity generation matrix. In other words, the information
)'! zD. -D15, 16 bits, and check bit kCo -05, 6 bits, check bits CO to C5 are the first bits based on information bit Do=D1s.
It is generated by each formula shown in Figure (B).

Also, assuming that there are 6 bits of syndrome k So to S5, each of these bits SO-85 is the information bit Do
=Dzs and check bit co-05 based on the equations shown in FIG. 1 (q).

FIG. 1A shows these relationships in matrix form for ease of viewing. For example, check bit 03'fc in Figure 1 (to find it using the equation shown in the equation, trace down to the point where the column gold "l" appears in column 03 of the matrix, and then trace down the row of that point (in this case, count from the top) According to the above formula, the bit where “l” is set among the data bits D-Do 15 of the fourth row) is 03
This is the information bit that should have an exclusive logic when creating . tfC, for example, to find syndrome 83,
Data bit D in the row indicated by S3 (fourth row)
o=D+s and “ of check bit co-05
The bits in which the operation is set become the information bits and check bits to be subjected to exclusive OR when creating the syndrome 83'C according to the formula shown in FIG. 1(C).

All matrices shown as N in FIG. 1 will hereinafter be referred to as parity generation matrices or simply matrices.

Next, error correction using the parity generation matrix shown in FIG. 1(5) will be explained. For example, the information bit D to be written. -Assuming that D15 is all "0", when using the matrix shown in Figure 1 (A),
All check bits Co - Cs become "1".

Therefore, the take to be written to the memory is as shown in the write data in FIG.

When syndromes So to Ss k are generated using the matrix shown in FIG. 1 (5) for this written data, 1
It can be seen that the number of hits from So to S5 is "O".

This fact also holds true when the information focus Do-Dts takes any value. In other words, certain information (pi) Do~D1
5, FIG. 1 (check bit Co=C5k is generated by the matrix of ~, and this is the original information bit) D,
- Added to DI5 and write data Do-Dts Co-
When C5 (Do-Cs after IJ) k is generated, the syndrome for this write take Do-05 is such that all bits are always °゛0'' (so that the equation of the syndrome in Figure 1 (q is constructed) ing).

Now, if we look at the matrix in Figure 1 (~), we can further see the following.

For example, if an error occurs only in the information bit Do, the data bit syndrome So~5stf, which has been all "0" as described above, will be applied to the "l" in it by looking at the vertical line below Do in the matrix. Only the value of the syndrome bit that corresponds to the specified value is inverted. That is, in this case, only the syndrome bits S, , Sl, and S2 are inverted and become "1", and the current situation becomes syndrome So, S5 ball l l 000. Similarly, if an error occurs in the information bit DB, the syndrome becomes 0O1j01, and if an error occurs in 1ch1kbitC3, the syndrome becomes 0.
It turns out that it becomes ooiooo.

The arrangement is such that the sum of "l" in any column is an odd number. Therefore, the total number of "1"s in the syndrome that occurs in response to a 1-bit error is always an odd number.

For this reason, if we limit the number of error bits that occur in write data to 2 bits or less (the probability of more errors occurring is extremely small),
By examining the syndrome, it can be determined that there is no error at all (all syndrome bits are O''), there is an l focus error (the sum of l's in the syndrome is an odd number), and there is a two-bit error ( It is possible to easily identify three cases in which the sum of l'' in the syndrome is an even number.

Moreover, in the case of one bit error among these, by comparing the generated syndrome with the matrix shown in FIG. 1, it is possible to determine which bit of Do-Dxs is an error. You can easily find out what you have created. For example, if the syndrome becomes 0OIIOIK, the total number of °°l" is 3, which is an odd number, so it is known that there is a 1-bit error, and each column under DO-DisQ of the matrix By examining one bit after another, it can be seen that the syndrome of 0O1101 occurs only when the DB causes an error.In this way, in the case of a 1-bit error, using the matrix shown in Figure 1, it is easy to solve the syndrome that occurs. Since it is possible to identify a 1-bit error and specify all error bits to be corrected, it is possible to correct a 1-bit error.

However, if there is a 2-bit error, it can be detected, but it cannot be corrected because it is not possible to specify which bit contains the error.

Thus, by using the matrix in FIG. 1 (~), it can be seen that this is a 5EC-DED code as described above.

Now, using this, an error correction method when there is a 2-bit error including a hard error will be explained.

As an example, the write data is such that all f\DH pins l-D, -D, and 5 are "0°" as shown in FIG.

Its friend all check bits Co − as mentioned above
The case where Cs becomes "l" will be explained.

It is assumed that when such write data is written to the memory and read from the memory, an error occurs in the information bits Do and DB, as shown in the read data in FIG. When a syndrome is created from this read data using the matrix shown in FIG. 1(A), 110101m is generated as shown in the read data syndrome shown in FIG. This syndrome has an even number of “1”s, so
As mentioned above, there is a 2-bit error. Therefore, it cannot be used to correct errors as is. Therefore, when a 2-bit error is detected from the syndrome, all bits I)o, c5i of this read data are inverted to create the rewrite data shown in Figure 2, and this is rewritten to the same memory. Then, this rewritten data is reread.

A series of processes such as inversion, rewriting, and rereading have different effects on hard errors and soft errors. Now 1. Assume that among the above and the 2-bit error in DB, Do is a 7-de error (indicated by two underlines "j") and DB is a soft error (indicated by one underline). In this way, as shown in the re-read data in Fig. 2, the re-read data is a fixed value even though all 0° has been written to Do.
1" appears in the re-read data. Therefore, if the re-read data is regarded as all the data inverted from the original write data, it will be corrected in the 9th key related to the node error Do. On the other hand, a soft error DB appears as "0" in the re-read data.

Only the DB soft error remains.

Now, if we create a syndrome for this re-read data using the matrix of N in Figure 1, it will become Oot tot like the re-read data syndrome in Figure 2, but this syndrome is If you refer to the entire matrix, it is indicating that there is an error in the DB.Therefore, in this case, create a syndrome using the reread data, leave only the bits specified by this syndrome as is, and then reread all the remaining bits. By inverting the data (however, only the information focus is required), it can be corrected to the original correct data as shown in the corrected data in FIG.

The above is a case where there is one hard error, but both
- If there is an error, all the bits of the original written data are reversed at the stage of re-reading the data, and it is created as the memory data, so that all the errors have been corrected. Therefore, all the syndromes caused by this become 0. Therefore, if all the processes similar to those described above are performed, all of this re-read data is inverted and correctly corrected data is obtained.

Now, the reason why the position of the error bit of a 1-bit error can be specified correctly using the syndrome of the inverted re-read data using the method shown in 1 above is that the parity generation matrix used for this purpose (fA) in Figure 1 has a special feature. This is because there are restrictions.

−′f′, that is, “
Since all the numbers of l゛° are the number of layers, the syndrome for certain written data has a characteristic sound that does not change even if all of the written data is inverted. Therefore, if only one soft error is included in the original read data.

By taking this read data syndrome, you can specify the error bit amount of this soft error.

In addition, even if all 111 hard errors are included, by taking the syndrome of the reread data that has been inverted as described above, the syndrome can be made exactly the same as the syndrome of the original read data that does not include the 11 soft errors. . Therefore, it is possible to correct a 2-bit error when a hard error is included by using the syndrome of the re-read data and directly specifying the original soft error as an error trap, and by following the procedure described above.

The use of a special parity generation matrix with the above constraints is disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 51-137335.
This is a feature of the method described in the publication.

However, there may arise a case where it becomes necessary to use a parity generation matrix that is constructed from a 5EC-DED code and does not satisfy the above-mentioned constraints. The above-mentioned method, ie, the method of creating a syndrome at the stage of re-reading data and determining correction bits based on the syndrome, cannot be applied to these parity generation matrices.

For example, Figure 3 shows one 5EC-D in a similar form to Figure 1.
The ED parity generation matrix shown in FIG. However, error correction cannot be performed using the above-described method.

There is an error correction method described in Japanese Unexamined Patent Publication No. 56-68997 as a method that can be applied to such a matrix.

This is as follows. - As an example, as before, use data in which the information bits Do-D15 are all "0" - From this data, check bits Co = C5k are generated using the matrix shown in Figure 3 (~), and all check bits become "1". As a result, the write data becomes like the write data shown in FIG.

Similarly to the above, assuming that there is a hard error in information bit Do and a soft error in information bit D8, the read data and the read data syndrome determined from this will be as shown in FIG. 4. . Since the number of "°1" in this read data syndrome is an even number, it is identified from this that it is a 2-bit error.

Therefore, all bits of the read data are inverted to create rewrite data, which is then rewritten into the same memory, and then reread. When all the pitches of this re-read data are inverted again to create re-read inverted data, as shown in Figure 4, this inverted data is in a form in which hard errors have been removed and only soft errors remain. It becomes data. Therefore, when a syndrome is created from this inverted data, it becomes 011010 as shown in the re-read inverted data syndrome in FIG.
), it is identified that the diadrome occurs when the information bit DsJr bit error occurs, and this bit Da
By inverting the value k, correction of the 2-bit error is completed.

This method differs from the previous method in that all SEs (, −
It can be applied to the DED parity generation matrix, but on the other hand, as mentioned above, the syndrome cannot be taken at the stage of 1 re-read data, and this is inverted again.
).--The disadvantage is that the syndrome must be extracted after generating non-inverted data from which errors have been removed.

On the other hand, the method of the present invention has a total of 5EC-DE
This method is applicable to the D parity generation matrix, and also makes it possible to perform syndrome correction at the stage of re-read data, inversion of the re-read data, and syndrome-based error correction in parallel.

Next, the principle of the present invention will be explained with reference to FIG.
Using the data where l, are all °0'', we can derive from Fig. 3 (
When the check bits Co-C5k are generated using the matrix A), all the check bits become "1" as in the case described above.9 As a result, the write data becomes like the write data shown in FIG.

Similarly to the above, assuming that there is a hard error in information bit Do and a soft error in information bit D8, the read data and the resulting syndrome will be as shown in FIG. 5. Become.

Since the number of "1"s in this syndrome is an even number, it can be determined that this is a 2-bit error.

Therefore, all bits of the read data are inverted and all data is rewritten, thereby rewriting all the data to the same memory and rereading it. The processing up to O is exactly the same as in the above case.

Now, as shown in FIG. 5, this re-read data differs only in the bit of D8 where a soft error occurred when compared with the original written data which does not include an error.

On the other hand, if a syndrome 8o=Ssk is created from this re-read data in FIG. 3 (using an Al matrix), the re-read data syndrome in FIG.
becomes. Using this syndrome and calculating the error bit amount specified by this syndrome from the matrix in Figure 3 (~) using the same method as described above, we get D9.
The reason for not instructing D8 above is as follows.

Figure 3 (The sum of "l" in the rows for each syndrome in the matrix ~ is all 9 odd numbers. Therefore, if you invert the data for all the rows of D, C5, the syndrome will also be inverted. It's put away.

In fact, the above-mentioned re-read data syndrome 1ooto
i 'i reversed, modified syndrome 01 shown in Figure 5
When 1010'11'' is created, it can be seen that this is exactly the desired syndrome specified by D8.

From the above, the following points are clear.

That is, each syndrome 5oLs as shown in FIG.
To create a syndrome that specifies error pit gold for reread data (inverted data) using a parity generation matrix in which the number of l'' in the rows for 5 is all odd numbers, create a syndrome that specifies the error pit amount for reread data , just invert this.

In this way, as shown in FIG. 5, from the reread data syndrome 1ooiot, a modified syndrome 0110'lO' is created by inverting it, and this (data bit specified by the white correction syndrome (in the current case, the new information bit) D
s) By inverting/inverting all of the bits outside 1M, soft errors can be correctly corrected.

As described above, when this method is used, a syndrome (modified syndrome) is created directly from the re-read data (inverted data), and only the bits specified by this syndrome are left unchanged, and the information of other re-read data is By inverting all bits 'r, correctly error-corrected information bits can be obtained.

As an example of further generalizing this method, next we will explain the case where all the parity generation matrixes shown in FIG.
If all D ts are set to "0", then C
o, C5 are all set to "1", and the written data becomes as shown in FIG. 7. As before, assuming that there is a node error in Do and a soft error in DB, the read data will be as shown in the same figure, and the read data syndrome calculated from this will be 110101. Since the numbers are the same or even, it is identified as a 2-bit error. Therefore, in the same manner as described above, the read data is inverted and rewritten data is written into the same memory. When this is re-read to create re-read data, as shown in Figure 7, compared to the inverted version of the original correct written data, the position of the soft error bit is D.
Only 8 is different data.

If we create a re-read data syndrome from this re-read data using the matrix shown in Figure 6 (), it will be 100011.
become. This is shown in Figure 6 (according to the matrix of
Syndrome that indicates bit money of 4 and error bit I) 8'i does not indicate correctly.

The modified syndrome for this matrix can be found as follows.

That is, the number of "I"s in each row of the syndromes S, , S5 of the matrix shown in FIG.
The column corresponding to o is 9 (odd number), and the column corresponding to Sl is 10.
(even number), the column corresponding to S2 is 9 (odd number), the column corresponding to S3 is 9 (odd number), the column corresponding to S4 is 9 (odd number),
Column 8 (even number) corresponds to S5.As mentioned above, for the syndrome where the sum of "l" in this row is an even number, the syndrome bit remains unchanged even if all data is inverted. , on the other hand, the syndrome bit that becomes an odd number is inverted as the data is inverted. Therefore, Fig. 6 (
In the case of the matrix shown in A), when the data is inverted, the bits of So+SL 83.84 are inverted, so the syndrome 5o-8s (1
When only bits So, S2, and 53IS4 in 00011) are inverted to create a modified syndrome 001101k, this modified syndrome correctly specifies error bit D8, as is clear from the matrix in FIG.

Therefore, as described above, by leaving only the focus (currently Da) indicated by this modification syndrome as it is and inverting the other re-read data, the correct original write data can be obtained. Of course, this can be applied only to the information bit D (+-Dzs), leaving only the information bit indicated by the modification syndrome as it is, and inverting the information bits of the other re-read data.

It is clear that the method described above can be generally applied regardless of the groove configuration of the 5EC-DED parity generation matrix. In this way, it is possible to obtain an error correction system that can obtain syndromes and perform error correction at the stage of re-read data (inverted data) without imposing any restrictions on the 5EC-DED parity generation matrix.

In addition, in Fig. 7, the information pin of the write data) D
6-D 15 explained the case where all are "0", but if all are "l", it is shown in Figure 8, and if it is "1010...lO" and includes 21 hard error money, it is shown in Figure 9. In the case of "0101...01", it is shown in Figure 10. The parity generation matrix used for these is the one shown in FIG. 6(A), and therefore, as described above, S, , S2 . A modified syndrome is created by inverting only bits S and S4. Mat1 hard error (2
(indicated by the book's underline) and soft errors (1
Although the bit positions indicated by the underline in the book (j) are different in each figure, it is clearly understood from these figures that the desired error correction can be performed using the principle of this method described above. Dew.

In addition, in order to create all modified syndromes from the normal syndrome using this method, as mentioned above, all bits of the normal syndrome are inverted only for the bits for which the sum of "1" in the row for each syndrome bit in the parity generation matrix is an odd number. good.

Now that the principle of the present system has become clear, one embodiment of the present invention will now be described in detail with reference to the drawings.

FIG. 11 is a block diagram showing one embodiment of the present invention.

This embodiment includes a write register l, a 5EC-DED code generation circuit 2, a selection circuit 3, a memory circuit 4, a read register 5, a syndrome generation circuit 61, a code circuit 7, a correction execution circuit 8, and a control circuit 9.

Now, the operation of this embodiment is as follows.

The write data is DO as explained in Figures 7 to 10.
These information bits DO''-D15 are stored in register l via line 1000 as consisting of the information bits ``-D15''.

The 5EC-DED code generation circuit 2 is shown in FIG.
According to the Ec-DED parity generation matrix, check bits Co-Csff1 are generated from the information bits Do-D and 5 stored in register l. Check bits C8 to Cs k are generated based on the formula shown in FIG. 6(B). ) and convert this into information bit D. -I) Add write data Do, C5 to ts, and select circuit 3 from line 2000.
Output to.

In the case of normal writing, the selection circuit 3 selects all inputs on the line 2000 side in response to a control signal supplied from the control circuit 9 via the line 9003, and selects the above-mentioned write data D.
o=Csk Provided as write data input to memory circuit 4 via k line 3000.

On the other hand, in the memory circuit 4, a signal designating the memory address to be written is supplied to the control circuit 9 via a line 9000, and further supplied from the circuit 9 as a memory address designation signal via a line 9004k. Control circuit 9 also controls memory circuit 4 to write state via line 90o5.

As a result, write data Do to C5 in which check bits Co and C5 are added to information bit D o -D 15
is written to a designated memory address in the memory circuit 4.

Next, when reading the written data from the memory circuit 4, the process is as follows.

A signal specifying the memory address to be read is sent to line 90.
A signal specifying readout is sent via line 90 via 00k.
01e to the control circuit 9, and further via the line 900.
All starting pulses are supplied to the control circuit 9 via 2'e.

As a result, the control circuit 9 starts the read sequence shown below.

First, the designated memory address is supplied to the circuit 4 via the line 9004, and the circuit 4 is set to the read state via the line 9005. As a result, the contents of the designated memory address are read out via line 4000k as the read data shown in FIGS. It is stored in the read register 5.

The contents of register 5 are read on line 5000 as read data.
' is supplied to the syndrome generation circuit 6 via '.

The circuit 6 generates the syndrome 5o-8sk based on the supplied read data shown in FIG. 6; the 18Ec-DED parity generation matrix.

That is, using the read data Do-Csk which is the output of the supplied register 5, each bit S.-8sk of the syndrome is generated according to the equations shown in FIG. 6(q).

If there is “1” in the syndrome s o ” s s
If "°" is included and the number is even, it indicates that there is a 2-bit error in the supplied data as described above, and this information is reported to the control circuit 9 via line 6000'i.

First, the middle 111 of the syndromes So to S5 mentioned above.
A case in which “ is not included at all or the number of included “l”s is an odd number will be explained.

In this case, the read data has no errors or only one error, so the normal 5EC-
Error correction can be easily performed by applying the DED coding method. That is, the syndrome So, S5 generated as described above is supplied to the decoding circuit 7 via the line 6QO1', where the syndrome So -
85 is decoded and output via line 91 7000'e as a correction signal having "1" in the bit position that would cause the syndrome in the event of an error. That is, when the t syndrome SO to S5 supplied from the line 6001 is, for example, 10011O, it is clear from the matrix of FIG. 6(A) that such a syndrome occurs when there is an error in the information bit D9.
In this case, the correction signal output is "1" only at the position of D9 and the other information pins are all "0" at DO-D8 and DIO to DI5.
0k to the correction execution circuit 8. On the other hand, each information bit Do to Dis of the read data from the read register 5 is supplied to the correction execution circuit 8 via a line 5000k, and each of these information bits and each bit of the correction signal corresponding thereto are 5 circuit 8, the signals are combined by exclusive OR. As a result, only the bits in the bit positions specified by the syndrome So, S5 among the information bits are inverted, corrected and output as data read out via line 5ooooi.

When the syndromes So, , S5 are all 0'', all bits of the output of the decoding circuit 7 are also 0, and the information bits in the output of the read register 5 are directly transmitted to the circuit 8 and the line 8000. It is output as data read out via the

The decoding circuit 7 used above has a memory address for each necessary combination of 6 bits of ':ii ## syndrome 80-85, and has a capacity of 16 bits for each memory address. By writing this output signal of all @16 bits for each memory address determined by bits, it can be easily realized as a decoding circuit using a ROM.

Now, the above is the first read data Do, C.
Syndrome S by 5, °°l included in S5
" is 0 or an odd number, read data D, -C
This operation is performed when it is determined that 5 contains only a 1-bit error or less, but if the number of 1's mentioned above is an even number (does not include 0), a 2-bit error is detected. This information is determined to include line 600 (
1' to the control circuit 9, which activates the control circuit 9's handling of the two-bit error.

The processing in this case will be described in detail below.

The current contents of the read register 5, that is, the data D, , C displayed as read data in FIGS. 7 to 1O
5, the inverted output with all its bits inverted is taken out from the register 5 via line 5001' and supplied as one input of the selection circuit 3, while the control circuit 9 When the process is started, a control signal is supplied to the selection circuit 3 via line 9003', which switches to select this inverted output on line 5001 as input, and also via line 9005.
Write is specified to the memory circuit 4 via the .

Note that the address designation signal for the memory circuit 4 on line 9004 is the same as before and designates the same address.

As a result, data obtained by inverting all bits of the read data Do, C5 is transferred to the memory circuit 4 as rewrite data.
is rewritten to the same memory address.

Immediately after this rewriting is completed, the control circuit 9 controls the memory circuit 4 to the read state via the line 9005, and immediately rereads the rewritten data and stores it in the read register 5. This becomes the reread data shown in FIGS. 7 to 1O.

This reread data is inverted data in which only hard errors among the errors contained in the read data are corrected, as explained in FIGS. 7 to 1O. Therefore, if a hard error is included in the original read data, the data will necessarily be completely inverted and will include only the error at 11 pitches below. Therefore, the re-read data currently contained in the read register 5 is used to generate the above-mentioned modification syndrome, thereby leaving only the bit in one specified bit position as it is, and leaving the rest as is. If the bits are collated and inverted, it is possible to obtain an error-corrected output.

Now, in order to create a modified syndrome, it is possible to easily create a modified syndrome because it is only necessary to invert a specific focus position of the normal syndrome as described above.

FIG. 12 is a circuit diagram showing details of the syndrome correction circuit section included in the syndrome generation circuit 6 of this embodiment.

The circuit 6 includes a normal syndrome generation circuit 60 and a syndrome correction circuit 61.

In the present example, the normal syndrome generating circuit 60 is a syndrome generating circuit in which the syndrome 5o=8s fc is generated from the input data D, -, C5 using the formula shown in FIG. 6(C). Each bit of the normal syndrome S, , -85 is on line S-0, respectively.
S-1, 8-2...S-5? output via

Figure 6 shows the 8EC-DED parity generation matrix (
A) To create a modified syndrome when using t, each pitch I of S, , S2, 83 and S4 is
f inversion T is sufficient. As shown in FIG. 12, an exclusive OR circuit is inserted into each 2-in corresponding to the bit to be inverted in the syndrome, and the corresponding output of the circuit 60 is used as one input of these 10 exclusive logic circuits. and the reread control line 9007 from the control circuit 9 as the other input.
Connect. The control line 9007 is controlled by the circuit 9 so that it takes a logic value of "0" during normal reading and takes a logic value of "1" during rereading.

As a result, during the above-mentioned normal reading, the circuit 6 is connected to the circuit 60.
The normal syndrome generated in is output as is and supplied to the decoding circuit 7 as a syndrome specifying the error bit position for the normal data as described above.

In addition, as at present, when rereading, the circuit 6
The normal syndrome that occurred in 0, S and S2 among them
,8. By inverting each pixel of S4 and S4, it is converted into a modified syndrome and supplied to the decoding circuit 7. From this combination, the syndrome that correctly specifies the error focus position is obtained from the inverted data (re-read cheater) currently stored in the read register 5, and is supplied to the circuit 7. As described above, an output is generated in which only the bit at the error bit position is "1" and the others are "0".

Next, a first circuit example of the correction execution circuit 8 in this embodiment will be described.
Shown in Figure 3.

Each tuh bit DO-DI5 pair is provided with a three-man exclusive OR circuit, and each of the three inputs of this circuit is connected to the corresponding bit output (line 7000) of the decoding circuit 7 and the readout register. 5 (line 5000) and the reread control line 90.
07 are supplied respectively.

As a result 5, during normal reading, the error υ correction circuit 8 inverts only the bit in the information bit DO-I) 1a of the read register 5 at the bit position where the decoding circuit 7 outputs "1"'. The aforementioned corrections are made.

(9) At the time of current re-reading, the information stored in the read register 5 and the decode circuit 7 in DoxDls are stored in the read register 5.
circuit 8 outputs "1" and only the bit in the next bit position is not inverted, and all other information bits are inverted.
At the output 8000, as mentioned above, a correctly corrected error will appear.

As described above, according to the fifth embodiment, syndromes can be generated using re-read data without restrictions on the parity generation matrix, and errors of up to 2 bits including hard errors can be corrected. Furthermore, inversion of re-read data can be performed in parallel with syndrome error correction. The next write data will be the 7th lip 7 of the read register 5.
Since the inversion output of the 0-tube circuit can be used as is, a special inversion circuit is not required.

Next, another example partially different from the above-mentioned example will be described in the 14th example.
It is shown as a block diagram in the figure.

The difference from the above embodiment is that a selection circuit 10 is newly provided, and that the correction execution circuit is simplified by using an exclusive OR circuit powered by two people instead of three. There are two points.

Under the control of the re-1 read control 89007, the selection circuit 10 selects the normal output of the read register 5 supplied via the line 5000' during normal read and supplies it to the error correction circuit, and also selects the normal output of the read register 5 supplied via line 5000' during re-read.
The inverted output of the read register 5 supplied via ' is selected and supplied to the error correction circuit. Therefore, during normal reading, the information in register 5 (D o-D 1)
Out of s, the decoding circuit 7 outputs 1'', and only the bit corresponding to the t bit position is inverted and corrected, and when rereading, the decoding circuit 7 of the information pit Do-D15 in the register 5 outputs ``1''. Only the bit corresponding to the bit position where "l" is output is not inverted (it is inverted twice and returns to the original state), and all other information pits are inverted, so that correct correction is similarly performed.

In addition, in any of the above examples, 8EC-DED
Let me explain the case where FIG. 6(A) is used as the property generation matrix.This is an example.

The present invention is not limited thereto.

Furthermore, the syndrome generation circuit 6 in FIG. 12 and the
The correction execution circuit 8 shown in the figure is also an example of the circuit, and the present invention is not limited thereto.

As described above, when the present invention is used, 5EC-DED
Using the code, it is possible to correct errors up to 2 bits (2-bit hard error, 1-bit hard error + 1-bit soft error, or 1-bit error correction). There are no restrictions on the 5EC-DED parity generation matrix used in the present invention, and the syndrome can be directly generated using re-read data that remains inverted.
This re-1 inversion of the re-read data makes it possible to perform error correction due to syndromes in parallel.

This makes it possible to provide a highly flexible and highly efficient error correction method.

[Brief explanation of drawings]

Figure 1 FA), (IIJ, (Q is parity generator)
Figure 2 is a diagram to explain the IJ system.
? Figure 3 fA), (B1. (Q is the second
FIG. 4 is a schematic diagram explaining the parity generation matrix of FIG. 3, and FIG.
9 and 10 are diagrams for explaining the principle of the error correction method of the present invention, and FIG. 6(A). (E9. fQ is a diagram for explaining the third parity generation matrix, FIG. 11 is a block diagram showing an embodiment of the present invention, and FIG. 12 is a diagram for explaining the syndrome generation circuit included in the syndrome generation circuit used in the above embodiment. FIG. 13 is a diagram showing a circuit example of the circuit section, FIG. 13 is a diagram showing a circuit diagram of a correction execution circuit used in the embodiment, and FIG. 14 is a block diagram showing another embodiment of the present invention. , l... Number register, 2...
... 5 EC-DED code generation circuit, 3 ... Selection circuit, 4 ... Memory circuit, 5 ... Read register, 6 ... Syndrome generation circuit ,
7...decoding circuit, 8°...correction execution circuit, 9...control unit, lO...selection circuit, 60... Normal syndrome generation circuit,
61...Syndrome correction circuit. Agent Patent Attorney Susumu Uchihara ゝ・゛・□Pa、′
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Claims (1)

[Claims] In an error correction method for a storage device using a 1-bit error correction and 2-bit error detection code, data consisting of a plurality of information bits and check bits is read from an address of the storage device designated by an address signal. an inverted write/reread means for inverting the focus of the read data in response to detection of a 2-bit error in the read data, writing the data to the same address as the read address, and then rereading the data; A syndrome generation means for generating a specific syndrome from the acquired data. A 2-bit error correction system comprising: a correction executing means for inverting information bits other than the bits designated by the syndrome among the information bits of the re-read data.